Transcript
The following document contains information on Cypress products.
MB9AB40N/A40N/340N/140N/150R/ MB9B520M/320M/120M Series FM3 Family 32-BIT MICROCONTROLLER FLASH PROGRAMMING MANUAL
For the information for microcontroller supports, see the following web site.
http://www.spansion.com/support/microcontrollers/
Publication Number MB9AB40N_MN706-00019
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Revision 3.0
Issue Date September 8, 2014
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Preface Purpose of this manual and intended readers This manual explains the functions, operations and serial programming of the flash memory of this series. This manual is intended for engineers engaged in the actual development of products using this series.
Trademark ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Organization of this Manual This manual consists of the following 3 chapters.
CHAPTER 1 Flash Memory This chapter gives an overview of, and explains the structure, operation, and registers of the Flash memory.
CHAPTER 2 Flash Security The flash security feature provides possibilities to protect the content of the flash memory. This chapter section describes the overview and operations of the flash security.
CHAPTER 3 Serial Programming Connection This chapter explains the basic configuration for serial programming to flash memory by using the Spansion Serial Programmer.
Sample programs and development environment Spansion offers sample programs free of charge for operating the peripheral functions of the FM3 family. Spansion also makes available descriptions of the development environment required for this series. Feel free to use them to verify the operational specifications and usage of this Spansion microcontroller. Microcontroller support information: http://www.spansion.com/Support/microcontrollers/ * : Note that the sample programs are subject to change without notice. Since they are offered as a way to demonstrate standard operations and usage, evaluate them sufficiently before running them on your system. Spansion assumes no responsibility for any damage that may occur as a result of using a sample program.
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How to Use This Manual Searching for a function The following methods can be used to search for the explanation of a desired function in this manual: Search from the table of the contents The table of the contents lists the manual contents in the order of description. Search from the register The address where each register is located is not described in the text. To verify the address of a register, see "APPENDIXES Register Map" of "FM3 Family Peripheral Manual".
Terminology This manual uses the following terminology.
Term
Explanation
Word
Indicates access in units of 32 bits.
Half word
Indicates access in units of 16 bits.
Byte
Indicates access in units of 8 bits.
Notations
The notations in bit configuration of the register explanation of this manual are written as follows. bit : bit number Field : bit field name Attribute : Attributes for read and write of each bit R : Read only W : Write only RW : Readable/Writable : Undefined Initial value : Initial value of the register after reset 0 : Initial value is "0" 1 : Initial value is "1" X : Initial value is undefined The multiple bits are written as follows in this manual. Example : bit7:0 indicates the bits from bit7 to bit0 The values such as for addresses are written as follows in this manual. Hexadecimal number : "0x" is attached in the beginning of a value as a prefix (example : 0xFFFF) Binary number : "0b" is attached in the beginning of a value as a prefix (example: 0b1111) Decimal number : Written using numbers only (example : 1000)
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Table 1 Applicable Products (TYPE6 product list) Flash memory size Type name* 256Kbyte 128Kbyte
64Kbyte
TYPE6
MB9AFB44L MB9AFB42L MB9AFB41L MB9AFB44M MB9AFB42M MB9AFB41M MB9AFB44N MB9AFB42N MB9AFB41N MB9AFB44LA MB9AFB42LA MB9AFB41LA MB9AFB44MA MB9AFB42MA MB9AFB41MA MB9AFB44NA MB9AFB42NA MB9AFB41NA MB9AFB44LB MB9AFB42LB MB9AFB41LB MB9AFB44MB MB9AFB42MB MB9AFB41MB MB9AFB44NB MB9AFB42NB MB9AFB41NB MB9AFA44L MB9AFA42L MB9AFA41L MB9AFA44M MB9AFA42M MB9AFA41M MB9AFA44N MB9AFA42N MB9AFA41N MB9AFA44LA MB9AFA42LA MB9AFA41LA MB9AFA44MA MB9AFA42MA MB9AFA41MA MB9AFA44NA MB9AFA42NA MB9AFA41NA MB9AFA44LB MB9AFA42LB MB9AFA41LB MB9AFA44MB MB9AFA42MB MB9AFA41MB MB9AFA44NB MB9AFA42NB MB9AFA41NB MB9AF344L MB9AF342L MB9AF341L MB9AF344M MB9AF342M MB9AF341M MB9AF344N MB9AF342N MB9AF341N MB9AF344LA MB9AF342LA MB9AF341LA MB9AF344MA MB9AF342MA MB9AF341MA MB9AF344NA MB9AF342NA MB9AF341NA MB9AF344LB MB9AF342LB MB9AF341LB MB9AF344MB MB9AF342MB MB9AF341MB MB9AF344NB MB9AF342NB MB9AF341NB MB9AF144L MB9AF142L MB9AF141L MB9AF144M MB9AF142M MB9AF141M MB9AF144N MB9AF142N MB9AF141N MB9AF144LA MB9AF142LA MB9AF141LA MB9AF144MA MB9AF142MA MB9AF141MA MB9AF144NA MB9AF142NA MB9AF141NA MB9AF144LB MB9AF142LB MB9AF141LB MB9AF144MB MB9AF142MB MB9AF141MB MB9AF144NB MB9AF142NB MB9AF141NB * : These type names are used to group applicable products in FM3 peripheral manual.
Table 2 Applicable Products (TYPE8 product list) Flash memory size Type name* 512Kbyte 384Kbyte
256Kbyte
TYPE8
MB9AF156M MB9AF155M MB9AF154M MB9AF156N MB9AF155N MB9AF154N MB9AF156R MB9AF155R MB9AF154R MB9AF156MA MB9AF155MA MB9AF154MA MB9AF156NA MB9AF155NA MB9AF154NA MB9AF156RA MB9AF155RA MB9AF154RA * : These type names are used to group applicable products in FM3 peripheral manual.
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Table 3 Applicable Products (TYPE9 product list) Flash memory size Type name* 256Kbyte 128Kbyte
M A N U A L
64Kbyte
TYPE9
MB9BF524K MB9BF522K MB9BF521K MB9BF524L MB9BF522L MB9BF521L MB9BF524M MB9BF522M MB9BF521M MB9BF324K MB9BF322K MB9BF321K MB9BF324L MB9BF322L MB9BF321L MB9BF324M MB9BF322M MB9BF321M MB9BF124K MB9BF122K MB9BF121K MB9BF124L MB9BF122L MB9BF121L MB9BF124M MB9BF122M MB9BF121M * : These type names are used to group applicable products in FM3 peripheral manual.
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CONTENTS CHAPTER 1: Flash Memory .............................................................................................. 1 1. Overview ........................................................................................................................... 2 2. Configuration ..................................................................................................................... 3 3. Operation Explanation ..................................................................................................... 11 3.1. Dual Operation Flash Memory Function ....................................................................... 12 3.2. Automatic Algorithm ..................................................................................................... 13 3.2.1. Command Sequences ................................................................................................14 3.2.2. Command Operations ................................................................................................15 3.2.3. Automatic Algorithm Run States .................................................................................17 3.3. Explanation of Flash Memory Operation ..................................................................... 20 3.3.1. Read/Reset Operation ................................................................................................21 3.3.2. Write Operation ..........................................................................................................22 3.3.3. Flash Erase Operation ...............................................................................................23 3.3.4. Sector Erase Operation ..............................................................................................24 3.3.5. Sector Erase Suspended Operation ...........................................................................26 3.3.6. Sector Erase Restart Operation .................................................................................27 3.4. Cautions When Using Flash Memory .......................................................................... 28
4. Registers ......................................................................................................................... 29 4.1. Flash Read Wait Register (FRWTR) ........................................................................... 30 4.2. Flash Status Register (FSTR) ..................................................................................... 32 4.3. Flash Interrupt Control (FICR) ..................................................................................... 34 4.4. Flash Interrupt Status Register (FISR) ........................................................................ 35 4.5. Flash Interrupt Clear Register (FICLR) ....................................................................... 36 4.6. CR Trimming Data Mirror Register (CRTRMM) .......................................................... 37
CHAPTER 2: Flash Security ............................................................................................ 39 1. Overview ......................................................................................................................... 40 2. Operation Explanation ..................................................................................................... 41
CHAPTER 3: Serial Programming Connection ................................................................ 43 1. Serial Programmer .......................................................................................................... 44 1.1. Basic Configuration ..................................................................................................... 45 1.2. Pins Used ...................................................................................................................... 53
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CHAPTER 1 Flash Memory 1. Overview
CHAPTER 1: Flash Memory This series is equipped with Dual Operation Flash memory consisting of 64 KBytes to 512 KBytes of Main area and 32 KBytes of Work area. The Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously. Those operations are not available for the existing series. This chapter gives an overview of, and explains the structure, operation, and registers of the Dual Operation Flash memory.
1.
Overview
2.
Configuration
3.
Operating Description
4.
Registers
CODE：9AB40N_FLASH-E03.0
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CHAPTER 1 Flash Memory 1. Overview
1. Overview The built-in Dual Operation Flash memory could erase data by-sector, or by all-sector collectively (Flash erase), and write programmed data by byte or by half words (16 bits) with the Cortex-M3 CPU. The Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously. Those operations are not available for the existing series.
Dual Operation Flash Memory Features
Two bank structure write/erase operation and read operation could be implemented simultaneously Usable capacity: Minimum configuration: 64 Kbytes (Lower bank of 16 Kbytes and upper bank of 48 Kbytes) Maximum configuration: 512 Kbytes (Lower bank of 16 Kbytes and upper bank of 496 Kbytes) Work area 32 KBytes Detection of write/erase completion with CPU interrupt High-speed flash memory: Up to 40 MHz: 0Wait Up to 72 MHz: 0 Wait by enabling pre-fetch buffer (only for TYPE9 products) Operating mode: 1. CPU mode This mode allows reading, writing, and erasing of flash memory from CPU (automatic algorithm*1). The operation of writing data by byte (8 bits) or by half word (16 bits) is available. To rewrite data, execute a program on RAM or on Flash Memory under Dual Operation. The simultaneous operation of erasing/writing and reading operations in respective banks (upper bank and lower bank) is possible. 2. ROM writer mode This mode allows reading, writing, and erasing of flash memory from a ROM writer (automatic algorithm*1). Built-in flash security function (Prevents reading of the content of flash memory by a third party) See "CHAPTER Flash Security" for details on the flash security function.
This document explains the usage of flash memory in CPU mode. For details on accessing the flash memory from a ROM writer, see the instruction manual of the ROM writer that is being used.
*1: Automatic algorithm=Embedded Algorithm
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CHAPTER 1 Flash Memory 2. Configuration
2. Configuration This series of flash memory consists of 64 KBytes to 512 KBytes Main area, 32 KBytes Work area, a security code area, and a CR trimming data area. Table 2-1 shows the correspondence between Capacity of Flash Memory built into this series and Product TYPE. Figure 2-1 to Figure 2-7 show the address and sector structure of the MainFlash memory built into this series as well as the address of security code / CR trimming area. See "CHAPTER 2 Flash Security" for details on the security. See Section "4.6 CR Trimming Data Mirror Register (CRTRMM)" and "CHAPTER High-Speed CR Trimming" in the "FM3 Family Peripheral Manual" for details on the High-Speed CR trimming data.
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CHAPTER 1 Flash Memory 2. Configuration
Table 2-1 Main area Capacity by Product TYPE Main area Capacity Product TYPE 512Kbyte 384Kbyte 256Kbyte 128Kbyte TYPE6
TYPE8
-
-
-
-
-
-
-
-
MB9AF156M MB9AF156N MB9AF156R MB9AF156MA MB9AF156NA MB9AF156RA
MB9AF155M MB9AF155N MB9AF155R MB9AF155MA MB9AF155NA MB9AF155RA
-
-
-
-
-
-
TYPE9
MB9AFB44L MB9AFB44M MB9AFB44N MB9AFB44LA MB9AFB44MA MB9AFB44NA MB9AFB44LB MB9AFB44MB MB9AFB44NB MB9AFA44L MB9AFA44M MB9AFA44N MB9AFA44LA MB9AFA44MA MB9AFA44NA MB9AFA44LB MB9AFA44MB MB9AFA44NB MB9AF344L MB9AF344M MB9AF344N MB9AF344LA MB9AF344MA MB9AF344NA MB9AF344LB MB9AF344MB MB9AF344NB MB9AF144L MB9AF144M MB9AF144N MB9AF144LA MB9AF144MA MB9AF144NA MB9AF144LB MB9AF144MB MB9AF144NB MB9AF154M MB9AF154N MB9AF154R MB9AF154MA MB9AF154NA MB9AF154RA MB9BF524K MB9BF524L MB9BF524M MB9BF324K MB9BF324L MB9BF324M MB9BF124K MB9BF124L MB9BF124M
64Kbyte
MB9AFB42L MB9AFB42M MB9AFB42N MB9AFB42LA MB9AFB42MA MB9AFB42NA MB9AFB42LB MB9AFB42MB MB9AFB42NB MB9AFA42L MB9AFA42M MB9AFA42N MB9AFA42LA MB9AFA42MA MB9AFA42NA MB9AFA42LB MB9AFA42MB MB9AFA42NB MB9AF342L MB9AF342M MB9AF342N MB9AF342LA MB9AF342MA MB9AF342NA MB9AF342LB MB9AF342MB MB9AF342NB MB9AF142L MB9AF142M MB9AF142N MB9AF142LA MB9AF142MA MB9AF142NA MB9AF142LB MB9AF142MB MB9AF142NB
MB9AFB41L MB9AFB41M MB9AFB41N MB9AFB41LA MB9AFB41MA MB9AFB41NA MB9AFB41LB MB9AFB41MB MB9AFB41NB MB9AFA41L MB9AFA41M MB9AFA41N MB9AFA41LA MB9AFA41MA MB9AFA41NA MB9AFA41LB MB9AFA41MB MB9AFA41NB MB9AF341L MB9AF341M MB9AF341N MB9AF341LA MB9AF341MA MB9AF341NA MB9AF341LB MB9AF341MB MB9AF341NB MB9AF141L MB9AF141M MB9AF141N MB9AF141LA MB9AF141MA MB9AF141NA MB9AF141LB MB9AF141MB MB9AF141NB
-
-
MB9BF522K MB9BF522L MB9BF522M MB9BF322K MB9BF322L MB9BF322M MB9BF122K MB9BF122L MB9BF122M
MB9BF521K MB9BF521L MB9BF521M MB9BF321K MB9BF321L MB9BF321M MB9BF121K MB9BF121L MB9BF121M
Figure 2-1 Memory map of 64 KByte Main area and 32 KByte Work area September 8, 2014, MB9AB40N_MN706-00019-3v0-E
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CHAPTER 1 Flash Memory 2. Configuration
0x0020_8000
0x0020_8000
SA7(8KB)
0x0020_6000 Flash memory 32KB
SA6(8KB)
0x0020_4000
0x0020_0000
SA4(8KB)
0x0020_0000 bit31 +3
0x0010_4000 0x0010_2000 0x0010_0000
Lower Bank
SA5(8KB)
0x0020_2000
bit0 +2
+1
+0
CR Trimming data
Lower Bank
Security code
0x0001_0000
0x0001_0000 SA8(48KB) 0x0000_4000 Flash memory 64KB
SA3(8KB)
0x0000_2000
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SA2(8KB)
0x0000_0000 bit31
0x0000_0000
Upper Bank
+3
bit0 +2
+1
+0
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CHAPTER 1 Flash Memory 2. Configuration
Figure 2-2 Memory map of 128 KByte Main area and 32 KByte Work area 0x0020_8000
0x0020_8000
SA7(8KB)
0x0020_6000 Flash memory 32KB
SA6(8KB)
0x0020_4000
0x0020_0000
SA4(8KB)
0x0020_0000 bit31 +3
0x0010_4000 0x0010_2000 0x0010_0000
Lower Bank
SA5(8KB)
0x0020_2000
bit0 +2
+1
+0
CR Trimming data
Lower Bank
Security code
0x0002_0000
0x0002_0000 SA9(64KB) Upper Bank
0x0001_0000 SA8(48KB) Flash memory 128KB
0x0000_4000
SA3(8KB)
0x0000_2000
bit31
0x0000_0000
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SA2(8KB)
0x0000_0000
+3
bit0 +2
+1
+0
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CHAPTER 1 Flash Memory 2. Configuration
Figure 2-3 Memory map of 256 KByte Main area and 32 KByte Work area 0x0020_8000
0x0020_8000
SA7(8KB)
0x0020_6000 Flash memory 32KB
SA6(8KB)
0x0020_4000
0x0020_0000
SA4(8KB)
0x0020_0000 bit31 +3
0x0010_4000 0x0010_2000 0x0010_0000
Lower Bank
SA5(8KB)
0x0020_2000
bit0 +2
+1
+0
CR Trimming data
Lower Bank
Security code
0x0004_0000
0x0004_0000
SA11(64KB) 0x0003_0000 SA10(64KB) Upper Bank
0x0002_0000 SA9(64KB) Flash memory 256KB
0x0001_0000 SA8(48KB) 0x0000_4000
SA3(8KB)
0x0000_2000
bit31
0x0000_0000
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SA2(8KB)
0x0000_0000
+3
bit0 +2
+1
+0
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Figure 2-4 Memory map of 384 KByte Main area and 32 KByte Work area 0x0020_8000
0x0020_8000
SA7(8KB)
0x0020_6000 Flash memory 32KB
SA6(8KB)
0x0020_4000
0x0020_0000
SA4(8KB)
0x0020_0000 bit31 +3
0x0010_4000 0x0010_2000 0x0010_0000
Lower Bank
SA5(8KB)
0x0020_2000
bit0 +2
+1
+0
CR Trimming data
Lower Bank
Security code
0x0006_0000
0x0006_0000 SA13(64KB) 0x0005_0000 SA12(64KB) 0x0004_0000 SA11(64KB) Upper Bank
0x0003_0000 SA10(64KB) Flash memory 384KB
0x0002_0000 SA9(64KB) 0x0001_0000 SA8(48KB) 0x0000_4000
SA3(8KB)
0x0000_2000
bit31
0x0000_0000
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Lower Bank
SA2(8KB)
0x0000_0000
+3
bit0 +2
+1
+0
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CHAPTER 1 Flash Memory 2. Configuration
Figure 2-5 Memory map of 512 KByte Main area and 32 KByte Work area 0x0020_8000
0x0020_8000
SA7(8KB)
0x0020_6000 Flash memory 32KB
SA6(8KB)
0x0020_4000
0x0020_0000
SA4(8KB)
0x0020_0000 bit31 +3
0x0010_4000 0x0010_2000 0x0010_0000
Lower Bank
SA5(8KB)
0x0020_2000
bit0 +2
+1
+0
CR Trimming data
Lower Bank
Security code
0x0008_0000
0x0008_0000 SA15(64KB) 0x0007_0000 SA14(64KB) 0x0006_0000 SA13(64KB) 0x0005_0000 SA12(64KB) Upper Bank
0x0004_0000 SA11(64KB) Flash memory 512KB
0x0003_0000 SA10(64KB) 0x0002_0000 SA9(64KB) 0x0001_0000 SA8(48KB) 0x0000_4000
SA3(8KB)
0x0000_2000
bit31
0x0000_0000
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Lower Bank
SA2(8KB)
0x0000_0000
+3
bit0 +2
+1
+0
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CHAPTER 1 Flash Memory 2. Configuration
Figure 2-6 Address of security/CR trimming data
Security / CR Trimming data
0x0010_4000 0x0010_2004
CR trimming area
0x0010_2000 0x0010_0004 Security code area
0x0010_0000 bit31
bit0 +3
+2
+1
+0
Figure 2-7 Bit structure of CR trimming area bit Field
31
21 20
Reserved
16 15
CR temperature trimming data*
10 9
Reserved
0 CR Frequency trimming data
*:Only TYPE8 / TYPE9 product.
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CHAPTER 1 Flash Memory 3. Operation Explanation
3. Operation Explanation This section explains the Dual Operation Flash memory operation. 3.1
Dual Operation Flash Memory Function
3.2
Automatic Algorithm
3.3
Explanation of Flash Memory Operation
3.4
Cautions When Using Flash Memory
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.1. Dual Operation Flash Memory Function This section explains the Dual Operation Flash memory functions.
Dual Operation Flash Memory Functions The Dual Operation Flash memory has two banks (upper bank/lower bank). The banks operate in the following conditions.
Upper Bank
Lower Bank Reading
Reading
Writing/Sector Erasing
Writing/Sector Erasing
Reading
Flash Erasing (Collective Erasing)
Dual Operation Flash Memory Interrupt The Dual Operation Flash memory can control the writing operation with interrupt by executing a program on flash memory. The interrupt could be generated at the writing/erasing operation completion or at the "HANG" status detection. The interrupt vector, however, cannot be read during writing/erasing operation to a bank with an interrupt vector. So, the vector address should be written to that of a different bank or RAM by using "Vector Table Offset Register" of Cortex-M3. The flash memory cannot implement writing and reading operation to the same bank simultaneously. To write/erase data in the flash memory, copy the writing/erasing program in on-chip SRAM or a different bank and execute the program.
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.2. Automatic Algorithm Writing to and erasing Dual Operation Flash memory is performed by activating the automatic algorithm. This section explains the automatic algorithm. 3.2.1
Command Sequences
3.2.2
Command Operations
3.2.3
Automatic Algorithm Run States
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.2.1.
Command Sequences
The automatic algorithm is activated by writing data to the Dual Operation Flash memory in the specified method. This is called a command. Table 3-1 shows the command sequences. Table 3-1 Command sequence chart Command
1st write 2nd write 3rd write 4th write 5th write 6th write Number of writes Address Data Address Data Address Data Address Data Address Data Address Data
Read/ Reset
1
Write
4
Flash erase
6
Sector erase (No Sector added) Sector erase (Sector added) Sector erase suspended Sector erase restarting
X PA SA PD *:
6
0xXXX 0xF0
--
0xAA8 0xAA 0x554
--
--
--
--
--
--
--
--
--
0xA0
PA
PD
--
--
--
--
0xAA8
0x10
0x30
0x55 0xAA8 0x80 0xAA8 0xAA 0x554
0x55 SA
6 and on
0xE0 *
1
0xXXX 0xB0
--
--
--
--
--
--
--
--
--
--
1
0xXXX 0x30
--
--
--
--
--
--
--
--
--
--
: Any value : Write address : Sector address (Specify any address within the address range of the sector to be erased) : Write data To add sectors to be erased, repeat the 6th write operation for the required times. By writing 0x30 in the last sector address, the erase operation is started.
The data notation in Table 3-1 only shows the lower 8 bits. The upper 8 bits can be set to any value. Write commands in a byte (8 bits) or half-words The address notation in Table 3-1 only shows the lower 12 bits. The upper 20 bits should be set to any address within the address range of the target flash memory. When the address outside the flash address range is specified, the command sequence would not be executed correctly since the flash memory cannot recognize the command. Specify 0x0010_0000 to the address to set a flash security code. Specify 0x0010_2000(CR Frequency trimming data) or 0x0010_2002(CR temperature trimming data) to the address to set or erase CR trimming data.
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.2.2.
Command Operations
This section explains the command operations.
Read/Reset Command The flash memory can be read and reset by sending the read/reset command. When a read/reset command is issued, the flash memory maintains the read state until another command is issued. When the execution of the automatic algorithm exceeds the time limit (HANG), the flash memory is returned to the read/reset state by issuing the read/reset command. The read/reset command issued during each command operation is valid. In this case, commands previously issued are cleared. So, the commands issued should be issued again from the first command. See Section "3.3.1 Read/Reset Operation" for details on the actual operation.
Program (Write) Command The data is written in the address specified at the fourth time by issuing the write command to the target sector for four consecutive times. Data can be written in a byte (8 bits) or a half-word (16 bits).according to the data width specified at the fourth time. For the first to third commands, the data width is not judged. Once the forth command issuance has finished, the automatic algorithm is activated and the automatic write to the flash memory starts. After executing the automatic write algorithm command sequence, there is no need to control the flash memory externally. See Section "3.3.2 Write Operation" for details on the actual operation. Only a single byte or half-word of data can be written for each write command sequence. To write multiple pieces of data, issue one write command sequence for each piece of data.
Flash Erase (All Sector Batch Erase) Command All of the sectors in flash memory can be batch-erased by sending the flash erase command in six consecutive writes. Once the sixth sequential write has finished, the automatic algorithm is activated and the flash erase operation starts. By flash erase command, the security/CR trimming data value can also be erased.
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CHAPTER 1 Flash Memory 3. Operation Explanation
Sector Erase Command By sending the sector erase command in six consecutive writes, the single sector specified by sixth write can be erased. When the sixth write data is "0x30", the automatic algorithm is activated and the sector erase operation begins. To erase multiple sectors, issue the sector erase code (0xE0) which is the sixth write data. To erase more sectors, write the sector erase code, "0xE0" to sector codes added in the seventh time and later. By writing the sector erase code, "0x30" in the last write data, the automatic algorithm is activated and the sector erase operation begins. There is no restriction on number of sectors added to be erased and all sectors can be erased collectively. The sector erase is started only by writing 0x30 to the sector erase command. 0xE0 cannot start the erase operation.
Sector Erase Suspended Command By issuing the sector erase suspended command during sector erase, sector erase can be suspended. In the sector erase suspended state, the read and write operations of memory cells of the sector not to erase is possible. (It is also possible even in the same sector.) See Section "3.3.5 Sector Erase Suspended Operation" for details on the actual operation. This command is only valid during sector erase. It is ignored even if it is issued during flash erase or during write. During the sector erase suspended state, the flash erase and the erase of sectors other than erase target sectors is not executed.
Sector Erase Restart Command In order to restart the erase operation in the sector erase suspended state, issue the sector erase restart command. Issuing the sector erase restart command returns the flash memory to the sector erase state and restarts the erase operation. See Section "3.3.6 Sector Erase Restart Operation" for details on the actual operation. This command is only valid during sector erase suspended. It is ignored even if it is issued during sector erase.
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.2.3.
Automatic Algorithm Run States
Writing and erasing of Dual Operation flash memory is performed by the automatic algorithm. Whether or not the automatic algorithm is currently executing can be checked by using the Flash Status Register (FSTR).
Flash Status Register This indicates the status of the automatic algorithm. Figure 3-1 shows the bit structure of the Flash Status Register.
Figure 3-1 Bit structure of the Flash Status Register bit
7 Reserved
6 Reserved
5 PGMS
4 SERS
3 ESPS
2 CERS
1 HNG
0 RDY
Because the correct value might not be read out immediately after issuing a command, ignore the first value of the Flash Status Flag that is read immediately after issuing a command.
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CHAPTER 1 Flash Memory 3. Operation Explanation
Status of each bit and Main Flash memory For the correspondence between each bit of the Flash Status register and the status of the flash memory, see Table 3-2.
Table 3-2 List of Flash Status Flag Register State
Running
Time limit exceeded
(Note)
Automatic write operation Internal operation before Flash memory erasing erase Erasing Sector erase Program write operation Sector erase (Sector not to erase) suspended Other than above Program write operation Internal operation before Flash memory erasing erase Erasing Sector erase Sector erase Program write operation suspended (Sector not to erase)
PGMS SERS ESPS CERS HNG RDY 1
0
0
0
0
0
0
0
0
0
0
0
0 0
0 1
0 0
1 0
0 0
0 0
1
1
1
0
0
0
0 1
1 0
1 0
0 0
0 1
1 0
0
0
0
0
1
0
0 0
0 1
0 0
1 0
1 1
0 0
1
1
1
0
1
0
See " Bit Descriptions" for the values that can be read.
Bit Descriptions [bit7:6] Reserved bits [bit5] PGMS: Program Write Operation Status flag bit After issuing the program write operation command, RDY bit becomes "0" and this bit is set to "1". This bit of "1" means the Program write operation status. After the Automatic Write Operation is finished, this bit is cleared to "0" and RDY bit becomes "1". [bit4] SERS: Sector Erase Status flag bit After issuing the Sector Erase command, RDY bit becomes "0" and this bit is set to "1". This bit of "1" means the Sector Erase status. After the Sector Erase Operation is finished, this bit is cleared to "0" and RDY bit becomes "1". When the Sector Suspend command is issued during sector erasing, the erasing operation is suspended. During this suspended status, this bit continues to be "1". [bit3] ESPS: Sector Erase Suspend Status flag bit When the Sector Erase Suspend command is issued during sector erasing, the erasing operation is suspended, RDY bit becomes "1", and this bit is set to "1". This bit of "1" means the Sector Erase Suspend Status. By issuing the Sector Erase Restart command, this bit is cleared to "0" and the Sector Erase Operation is restarted. In the Sector Erase Suspend Status, the automatic write operation command can be issued to the sectors not to erase. By issuing the command, the RDY bit is set to "0" and PGMS bit is set to "1" to transfer to "Program write operation status". [bit2] CERS: Flash Memory Erase Status flag bit When the Flash Erase command is issued, RDY bit becomes "0" and the Flash Memory is transferred to Pre-erasing Internal Operation Status. In this status, this bit is not set to "1" yet. After the Pre-erasing Internal Operation is completed, the Flash erasing is started and this bit is set to "1". This bit of "1" means Flash Erasing Status. After the Flash Erasing operation is completed, this bit is cleared to "0" and RDY bit becomes "1".
[bit1] HNG: HANG Status flag bit The Internal Timer is mounted on the Flash Memory to provide the execution limit time of the Automatic September 8, 2014, MB9AB40N_MN706-00019-3v0-E
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CHAPTER 1 Flash Memory 3. Operation Explanation Algorithm. When the Automatic Algorithm is not completed within the executing limit time specified by the internal timer, the Flash Memory becomes HANG Status and this bit is set to "1". To clear this bit and to return to the normal status, it is required to generate the reset or to issue the reset command. [bit0] RDY: RDY Status flag bit This bit indicates whether the Automatic Algorithm is being executed or not. When the Flash Memory is being written or erased, this bit is set to "0" and the execution command cannot be accepted in this status. When this bit is "1", the execution command can be accepted (except the Sector Suspend command during sector erasing.)
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.3. Explanation of Flash Memory Operation The operation of the Flash memory is explained for each command. 3.3.1
Read/Reset Operation
3.3.2 Write Operation 3.3.3
Flash Erase Operation
3.3.4
Sector Erase Operation
3.3.5
Sector Erase Suspended Operation
3.3.6
Sector Erase Restart Operation
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.3.1.
Read/Reset Operation
This section explains the read/reset operation. To place the flash memory in the read/reset state, send read/reset commands to an arbitrary address within the address range of the flash memory. Because the read/reset state is the default state of the flash memory, the flash memory always returns to this state when the power is turned on or when a command finishes successfully. When the power is turned on, there is no need to issue a data read command. Furthermore, because data can be read by normal read access and programs can be accessed by the CPU while in the read/reset state, there is no need to issue read/reset commands.
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.3.2.
Write Operation
This section explains the write operation. Writes are performed according to the following procedure. 1. The program (write) command is issued sequentially. The automatic algorithm activates and the data is written to the flash memory. After the write command is issued, there is no need to control the flash memory externally. 2. Confirm Flash Status Register (FSTR) After issuing the program write command, RDY bit and PGMS bit of the Flash Status Register are set to "0" and "1" respectively. After the write operation is completed, RDY bit and PGMS bit are set to "1" and "0" respectively. See Figure 3-2 for an example of a write operation to the flash memory.
Figure 3-2 Example write operation Start of writing
Write command sequence
1. Addr:00XX_XAA8 2. Addr:00XX_X554 3. Addr:000X_XAA8 4. Write Address
Data:XXAA Data:XX55 Data:XXA0 Write Data
Read FSTR (Dummy)
Read FSTR
Next address
1 HNG?
0 No Write error
PGMS=0 & RDY=1?
Yes
No
Last address Yes End of writing
See Section "3.2 Automatic Algorithm" for details on the write command. Because the value of the flash memory is read correctly immediately after the command issued, ignore the first read value of Flash Status Register (FSTR) after the command issued. Although the flash memory can be written in any sequence of addresses regardless of crossing sector boundaries, only a single byte or a single half-word of data can be written with each write command sequence. To write multiple pieces of data, issue one write command sequence for each piece of data. All commands issued to the flash memory during the write operation are ignored. If the device is reset while the write is in progress, the data that is written is not guaranteed.
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.3.3.
Flash Erase Operation
This section explains the flash erase operation. All sectors in flash memory can be erased in one batch. Erasing all of the sectors in one batch is called flash erase. The automatic algorithm can be activated and all of the sectors can be erased in one batch by sending the flash erase command sequentially to the target sector. See Section "3.2 Automatic Algorithm" for details on the flash erase command. 1. Issue the flash erase command sequentially The automatic algorithm is activated and the flash erase operation of the flash memory begins. 2. Confirm Flash Status Register (FSTR) After Flash Erase Command issued, RDY bit of Flash Status Register becomes "0". At this time, the flash memory, becomes pre-erasing internal operation status and CERS bit is held to be "0". After erasing operation is started, RDY bit and CERS bit are cleared to "1" and "0" respectively.
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.3.4.
Sector Erase Operation
This section explains the sector erase operation. Sectors in the flash memory can be selected and the data of only the selected sectors can be erased. Multiple sectors can be specified at the same time. Sectors are erased according to the following sequence. 1. Issue the sector erase command sequentially to the target sector The automatic algorithm activates and the sector erase operation begins. To erase multiple sectors, write 0xE0 as the 6th write data (command data). By writing 0xE0 to the 7th sector address and later, sectors could be added to be erased. Write 0x30 in the last sector address, then the automatic algorithm is activated and the erase operation of multi sectors specified is started. There is no restriction on number of sectors added to be erased and all sectors can be erased collectively. 2. Confirm Flash Status Register (FSTR) After issuing Sector erase command, RDY bit and SERS bit of the Flash Status Register are set to "0" and "1" respectively. After that, when the erase operation of all sectors specified are completed, RDY bit and SERS bit are set to "1" and "0" respectively. For an example of the sector erase procedure, see Figure 3-3.
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CHAPTER 1 Flash Memory 3. Operation Explanation
Figure 3-3 Example of sector erase procedure Start of erase
Sector erase command sequence 1. Addr:00XX_XAA8 2. Addr:00XX_X554 3. Addr:00XX_XAA8 4. Addr:00XX_XAA8 5. Addr:00XX_X554
Data:XXAA Data:XX55 Data:XX80 Data:XXAA Data:XX55
No There is another sector to be erased? Yes
Write erase code (0xXXE0) to sector to be erased 消去コード ()
Write erase code (0xXX30) to sector to be erased Read FSTR (dummy)
Read FSTR 1
HNG? 0
No
SERS=0 & RDY=1 ?
Failure of erase
Yes
End of erase
Once the sector erase operation has finished, the flash memory returns to read/reset mode. See Section "3.2 Automatic Algorithm" for details on the sector erase command. Because the value may not be read correctly immediately after issuing a command, ignore the first read value of the Flash Status Register (FSTR) after issuing the command.
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.3.5.
Sector Erase Suspended Operation
This section explains the sector erase suspended operation. When the sector erase suspended command is sent during sector erase or in the command timeout state, the flash memory makes a transition to the sector erase suspended state and temporarily suspends the erase operation. By sending the erase restart command, the flash memory is returned to the sector erase state and can restart the suspended erase operation.
Sector Erase Suspended Operation Sector erase is suspended in the following steps: 1. Write the sector erase suspended command to an arbitrary address within the address range of the flash memory during the erasing operation. 2. Confirm Flash Status Register (FSTR). Issuing the sector erase suspended command, RDY bit and ESPS bit are set to "0" and "1" respectively. Under this condition, memory cells of a sector other than a sector to be erased are could be read and written.(even in the same bank, they could be erased) See Section "3.2 Automatic Algorithm" for details on the sector erase suspended command. When a sector to be erased is read after a sector erase suspend, the value of the sector is undefined.
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.3.6.
Sector Erase Restart Operation
This section explains the operation for restarting sector erase during sector erase suspended. When the sector erase restart command is issued to an arbitrary address in the address range of the flash memory while sector erase is suspended, sector erase can be restarted. When the sector erase restart command is issued, the sector erase operation during sector erase suspended is restarted. See Section "3.2 Automatic Algorithm" for details on the sector erase restart command. The sector erase restart command is only valid during sector erase suspended. Even if the sector erase restart command is issued during sector erase, it is ignored.
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CHAPTER 1 Flash Memory 3. Operation Explanation
3.4. Cautions When Using Flash Memory This section explains the cautions when using Flash memory. If this device is reset during the write, the data that is written cannot be guaranteed. Moreover, It is necessary to prevent an unexpected reset like Watchdog Timer from occurring during the writing and deleting. Immediately after issuing the automatic algorithm command to the flash memory, always perform a dummy read before reading the data that is actually wanted. If the device is forced to transfer to the low power consumption mode, ensure the operations of the flash memory automatic algorithm is completed. See "CHAPTER Low Power Consumption Mode" of the "FM3 Family Peripheral Manual" for details on the low power consumption mode. During the automatic algorithm operation, an address in the bank where the automatic algorithm is being executed cannot read correctly. So, it is required to prevent an interrupt occurring in a bank where an interrupt vector exists during writing /erasing, or to rewrite a vector address to that of a different bank or RAM by using "Vector Table Offset Register" of Cortex-M3.
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CHAPTER 1 Flash Memory 4. Registers
4. Registers This section explains the registers.
List of Registers Abbreviated Register Name
Register Name
Reference
FRWTR
Flash Read Wait Register
4.1
FSTR
Flash Status Register
4.2
FICR
Flash Interrupt Control Register
4.3
FISR
Flash Interrupt Status Register
4.4
FICLR
Flash Interrupt Clear Register
4.5
CRTRMM
CR Trimming Mirror Register
4.6
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CHAPTER 1 Flash Memory 4. Registers
4.1. Flash Read Wait Register (FRWTR) FRWTR register specifies the wait cycle for flash memory.
TYPE6 and TYPE8 products bit
7
6
Field
5
4
3
2
1
Reserved
0 RWT
Attribute Initial value
RW 0
RW 1
[bit7:2] Reserved: Reserved bits The read values are undefined. Ignored on write. [bit1:0] RWT: Read Wait Cycle Specifies the read wait cycle for the Flash Memory.
bit1
bit0
Description
0
0
0 cycle wait mode This setting can be used when HCLK is 20 MHz or less.
0
1
0/1 cycle wait mode(Initial value) This setting should be specified when HCLK is 20 MHz or more.
1
0
1
1
Setting prohibited
Do not set RWT to "00" if HCLK exceeds 20 MHz. While RWT setting is "00", be sure that HCLK must not exceed 20 MHz for a moment. Perform a dummy read to this register after changing the register.
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CHAPTER 1 Flash Memory 4. Registers
TYPE9 products bit
7
6
Field
5
4
3
2
1
Reserved
0 RWT
Attribute Initial value
RW 1
RW 0
[bit7:2] Reserved: Reserved bits The read values are undefined. Ignored on write. [bit1:0] RWT: Read Wait Cycle Specifies the read wait cycle for the Flash Memory.
bit1
bit0
Description
0
0
0 cycle wait mode This setting can be used when HCLK is 20 MHz or less.
0
1
0/1 cycle wait mode This setting could be specified when HCLK is more than 20 MHz and 40 MHz or less.
1
0
Pre-fetch mode (Initial value) This setting should be specified when HCLK is 40 MHz or more.
1
1
Setting prohibited
Do not set RWT to "00" if HCLK exceeds 20 MHz. While RWT setting is "00", be sure that HCLK must not exceed 20MHz for a moment. Do not set RWT to "00" and "01" if HCLK exceeds 40 MHz. While RWT setting is "00" or "01", be sure that HCLK must not exceed 40 MHz for a moment. Perform a dummy read to this register after changing the register.
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CHAPTER 1 Flash Memory 4. Registers
4.2. Flash Status Register (FSTR) FSTR register is a status register of flash memory.
bit
7
Field
6 Reserved
5
4
3
2
1
0
PGMS
SERS
ESPS
CERS
HNG
RDY
R 0
R 0
R 0
R 0
R 0
R X
Attribute Initial value
[bit7:6] Reserved bits The read values are undefined. Ignored on write. [bit5] PGM: Flash Program Status Indicates the program (writing operation) status of the flash memory.
bit
Description
0
The program is not being written to the flash memory.
1
The program is being written to the flash memory.
[bit4] SERS: Flash Sector Erase Status Indicates the sector erase status of the flash memory.
bit
Description
0
The sector is not being erased.
1
The sector is being erased or the sector erase is being suspended.
[bit3] ESPS: Flash Erase Suspend Status Indicates the sector erase suspend status of the flash memory.
bit
Description
0
The sector erase is not being suspended.
1
The sector erase is being suspended.
[bit2] CERS: Flash Chip Erase Status Indicates the all sector erase status of the flash memory.
bit
Description
0
The flash memory is not being data erased.
1
The flash memory is being data erased.
[bit1] HNG: Flash Hang September 8, 2014, MB9AB40N_MN706-00019-3v0-E
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CHAPTER 1 Flash Memory 4. Registers Indicates whether the flash memory is in the HANG state. Flash memory enters the HANG state if the timing is exceeded. If this bit becomes "1", issue a reset command (See Section "3.2.1 Command Sequences").
bit
Description
0
The flash memory HANG state has not been detected.
1
The flash memory HANG state has been detected.
[bit0] RDY: Flash Ready Status Indicates whether flash memory write or erase operation using the automatic algorithm is in progress or finished. While an operation is in progress, data cannot be written and the flash memory cannot be erased.
bit
Description
0
Operation in progress (cannot accept write/erase command)
1
Operation finished (can accept write/erase command)
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CHAPTER 1 Flash Memory 4. Registers
4.3. Flash Interrupt Control Register (FICR) FICR register specifies the interrupt enable setting of FLASH memory.
bit
7
6
Field
5
4
3
Reserved
Attribute Initial value
2
1
0
HANGIE
RDYIE
RW 0
RW 0
[bit7:2] Reserved bits The read values are undefined. Ignored on write. [bit1] HANGIE: HANG Interrupt Enable This bit enables the flash HANG status interrupt. When the HANGIF bit of FISR register and this bit are both "1", an interrupt to CPU is generated.
bit
Description
0
FLASH HANG interrupt is prohibited.(Initial value)
1
FLASH HANG interrupt is permitted.
[bit0] RDYIE: RDY Interrupt Enable This bit enables the flash RDY status interrupt. When the RDYIF bit of FISR register and this bit are both "1", an interrupt to CPU is generated.
bit
Description
0
FLASH RDY interrupt is prohibited.(Initial value)
1
FLASH RDY interrupt is permitted.
Clear the bit in question of FISR register and set the bit of this register to "1" to enable the interrupt.
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CHAPTER 1 Flash Memory 4. Registers
4.4. Flash Interrupt Status Register (FISR) FISR register indicates the interrupt status of FLASH memory.
bit
7
6
5
Field
4 Reserved
Attribute Initial value
3
2
1
0
HANGIF
RDYIF
RW 0
RW 0
[bit7:2] Reserved bits The read values are undefined. Ignored on write. [bit1] HANGIF: HANG Interrupt Flag This bit is set to "1" when the flash HANG status is detected. This bit is set with the rising edge of HANG signal. This bit is cleared by writing "1" to HANGC bit of FICLR register.
bit
Description
0
FLASH HANG status is not detected. (Initial value)
1
FLASH HANG status is detected.
[bit0] RDYIF: RDY Interrupt Flag This bit is set to "1" when the flash RDY status is detected. This bit is set with the rising edge of RDY signal. This bit is cleared by writing "1" to RDYC bit of FICLR register.
bit
Description
0
FLASH RDY status is not detected. (Initial value)
1
FLASH RDY status is detected.
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CHAPTER 1 Flash Memory 4. Registers
4.5. Flash Interrupt Clear Register (FICLR) FICLR register clears the interrupt flag of flash memory.
bit
7
6
Field
5
4
3
2
Reserved
Attribute Initial value
1
0
HANGC
RDYC
W 0
W 0
[bit7:2] Reserved bits The read values are undefined. Ignored on write. [bit1] HANGC: HANG Interrupt Clear This bit is the clear bit of HANG interrupt flag. This bit clears the HANGIF bit of FISR register by writing "1" to this bit.
bit
Description 0
FLASH HANG interrupt flag (HANGIF) is not changed.
1
FLASH HANG interrupt flag (HANGIF) is cleared.
At Write At Read
"0" is read.
[bit0] RDYC: RDY Interrupt Flag Clear This bit is the clear bit of RDY interrupt flag. This bit clears RDYIF bit of FISR register by writing "1" to this bit.
bit
Description 0
FLASH RDY interrupt flag (RDYIF) is not changed.
1
FLASH RDY interrupt flag (RDYIF) is cleared.
At Write At Read
"0" is read.
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CHAPTER 1 Flash Memory 4. Registers
4.6. CR Trimming Data Mirror Register (CRTRMM) CRTRMM register is the mirror register of the CR trimming data. A value of this register can be used in the user mode and the serial writer mode.
TYPE6 products bit
31
10
Field
Reserved
9
0 TRMM
Attribute Initial value
R *
[bit31:10] Reserved bits The read values are undefined. Ignored on write. [bit9:0] TRMM : CR Trimming Data Mirror Register After a reset is released, bit[9:0](CR Frequency Trimming Data) of Address "0x0010_2000" in Flash Memory area are stored in this bit. For details of CR Frequency Trimming data, see Chapter "High-speed CR Trimming Data" in "FM3 Family Peripheral Manual" .
Field TRMM
bit 9:0
Description *: Reads bit[9:0] of Address "0x0010_2000".
After deleting the flash memory data and issuing "Reset" signal inside the chip, this register is cleared. At this time, the stored CR trimming data is deleted. So, save the stored CR trimming data to RAM etc. before the data is deleted.
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CHAPTER 1 Flash Memory 4. Registers
TYPE8 and TYPE9 products bit
31
Field
21
20
Reserved
Attribute Initial Value
16
15
TTRMM
10 Reserved
9
0 TRMM
R
R
*
*
[bit31:21] Reserved bits The read values are undefined. Ignored on write. [bit20:16] TTRMM : Temperature CR Trimming Data Mirror Register After a reset is released, bit[4:0](CR Temperature Trimming Data) of address "0x0010_2002" in Flash Memory area are stored in this bit. For details of CR Temperature Trimming data, see Chapter "High-speed CR Trimming Data" in "FM3 Family Peripheral Manual".
Field
bit
TTRMM
20:16
Description *: Reads bit[4:0] of Address "0x0010_2002".
[bit15:10] Reserved bits The read values are undefined. Ignored on write. [bit9:0] TRMM : CR Trimming Data Mirror Register After a reset is released, bit[9:0](CR Frequency Trimming Data) of Address "0x0010_2000" in Flash Memory area are stored in this bit. For details of CR Frequency Trimming data, see Chapter "High-speed CR Trimming Data" in "FM3 Family Peripheral Manual" .
Field
bit
TRMM
9:0
Description *: Reads bit[9:0] of Address "0x0010_2000".
After deleting the flash memory data and issuing "Reset" signal inside the chip, this register is cleared. At this time, the stored CR trimming data is deleted. So, save the stored CR trimming data to RAM etc. before the data is deleted.
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CHAPTER 2 Flash Security 1. Overview
CHAPTER 2: Flash Security The flash security function protects contents of the flash memory. This section describes the overview and operations of the flash security.
1. 2.
Overview Operation Explanation
CODE : 9BF510RSECURITY-E01.1
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CHAPTER 2 Flash Security 1. Overview
1. Overview This section explains the overview of the flash security. If the protection code of 0x0001 is written in the security code area of flash memory, access to the flash memory is restricted. Once the flash memories are protected, performing the flash erase operation only can unlock the function otherwise read/write access to the flash memory from any external pins is not possible. This function is suitable for applications requiring security of self-containing program and data stored in the flash memory. Table 1-1 shows the address and the protection code of the security code.
Table 1-1 Address of security code and protection code Address
Protection Code
0x0010_0000
0x0001
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CHAPTER 2 Flash Security 2. Operation Explanation
2. Operation Explanation This section explains the operation of the flash security.
Setting Security Write the protection code 0x0001 in address of the security code. The security is enabled and set after all the reset factors are generated or after turning on the power again.
Releasing Security The security is released by all the reset factors or power-on after the execution of flash erase.
Operation with Security Enabled The operations with security enabled vary depending on each mode. Table 2-1 shows the security operations in each mode.
Table 2-1 Flash Operation with Security Enabled Mode pin
Access to flash
MD1
MD0
Flash erase
Other commands
Read
Access from JTAG pins
User mode
-
0
Enabled
Enabled
Valid data
Disabled
Serial writer mode
0
1
Enabled
Disabled
Invalid data
Disabled
Mode
Writing the protection code is generally recommended to take place at the end of the flash programming. This is to avoid unnecessary protection during the programming. In user mode, there is no limit to flash memory even during security is enabled. However, JTAG pins are fixed not to access internally from these pins during security is enabled. To release security, perform the flash erase operation using a serial writer because the security cannot be released through JTAG pins. When security enabled, the obstruction analysis of the flash memory cannot be performed.
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CHAPTER 2 Flash Security 2. Operation Explanation
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
CHAPTER 3: Serial Programming Connection This series supports serial onboard write (Spansion standard) to flash memory. This chapter explains the basic configuration for serial write to flash memory by using the Spansion Serial Programmer.
1.
Serial Programmer
CODE : 9AB40NFSP-E03.0
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
1. Serial Programmer Spansion Serial Programmer (software) is an onboard programming tool for all microcontrollers with built-in flash memory. Two types of Serial Programmer are available according to the PC interface (RS-232C or USB) used. Choose the type according to your environment. Onboard write is possible with the product which USB function is installed by connecting the PC and microcontroller directly without performing USB-serial conversion. 1.1
Basic Configuration
1.2
Pins Used
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
1.1. Basic Configuration This section explains the basic configuration.
Basic Configuration of Spansion MCU Programmer (Clock Asynchronous Serial Write) Spansion MCU Programmer writes data, through clock asynchronous serial communication, to built-in flash memory of a microcontroller installed in the user system when the PC and the user system are connected through RS-232C cable. In these series, serial programming (UART communication mode) is possible by any clock, crystal oscillator or built-in High-speed CR oscillator. Figure 1-1 shows the basic configuration of Spansion MCU Programmer, and configuration.
lists the system
Figure 1-1 Basic Configuration of Spansion MCU Programmer *
User system
RS-232C
* RS-232C driver IC is required separately.
Table 1-1 System Configuration of Spansion MCU Programmer Name
Specifications
Spansion MCU Programmer
Software (In case you request the data, contact to Spansion sales representatives.)
RS-232C cable
Sold on the market.
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
Connection Example of Spansion MCU Programmer The following shows a connection example of Spansion MCU Programmer.
When Crystal oscillator is used as the source oscillation clock Figure 1-2 shows a connection example of Spansion MCU Programmer when a crystal oscillator is used as a source oscillation clock and Table 1-2 O available frequencies and communication baud rates.
Figure 1-2 Connection example when using a crystal oscillator User system
Source oscillation clock
VCC MD1
Serial write: 0 10kΩ Serial write: 1
X0
X1
MD0
Device INITX 10kΩ Serial write at UART communication mode: 0 RS-232C driver
P60/INT15_1
10kΩ
10kΩ P21/SIN_0 P22/SOT0_0
RS-232C
VSS Note: The pull-up resistance values shown are for example. Select the most appropriate resistance values for each system.
Table 1-2 Oscillating frequency and communication baud rate available for clock asynchronous serial communication Source Oscillating Frequency
Communication Baud Rate
4MHz
9600bps
8MHz
19200bps
16MHz
38400bps
24MHz
57600bps
48MHz*
115200bps
*: TYPE9 Product Only
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
When built-in high-speed CR oscillator is used as a source oscillation clock Figure 1-3 shows a connection example of Spansion MCU Programmer when a built-in high-speed CR oscillator is used as a source oscillation clock. When neither crystal oscillator nor external clock is connected to X0/X1 pins, the built-in high-speed CR oscillator is connected for communication. The communication baud rate is 9600[bps] when built-in high-speed CR oscillator is used The following are the restrictions when built-in high-speed CR oscillator is used ・Because the oscillation frequency of the built-in high-speed CR oscillator would fluctuate due to temperature and voltage change, the allowable baud rate error range might be exceeded. ・For using the built-in high-speed CR oscillator, see "Built-in CR Oscillation Specifications" in "Data Sheet" of the product used.
Figure 1-3 Connection Example When Built-in High-speed CR Oscillator is used User system
VCC MD1
Serial write: 0 10kΩ Serial write: 1
MD0
Device INITX
RS-232C driver
10kΩ P21/SIN_0 P22/SOT0_0
RS-232C
VSS
Note: The pull-up resistor values shown are for example. Select the most appropriate resistor values for each system.
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
Basic Configuration of Spansion USB DIRECT Programmer (USB Serial Write) Spansion USB DIRECT Programmer writes data, through USB communication mode, to built-in flash memory of a microcontroller when the PC and the user system are connected through a USB cable. Figure 1-4 shows the basic configuration of Spansion USB DIRECT Programmer, and Table 1-1 lists the system configuration.
Figure 1-4 Basic Configuration of Spansion USB DIRECT Programmer USB serial communication
USB User system
Table 1-1 System Configuration of Spansion USB DIRECT Programmer Name
Specifications
Spansion USB DIRECT Programmer
Software (In case you request the data, contact to Spansion sales representatives.)
USB cable
Sold on the market.
For connection examples, see the manual (help section) of Spansion USB DIRECT Programmer.
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
Figure 1-5 Connection example using Spansion USB DIRECT Programmer (own power supply is used, for TYPE6 and TYPE8 products) User system
VCC
10kΩ Serial write: 1
Serial write at USB communication mode 4MHz : 0 48MHz : 1
Level Shifter
27Ω
P60/INT15_1 51kΩ UDM0
10Ω
Level Shifter
100kΩ
P61/UHCONX UDP0
27Ω GND
X1
MD0
INITX
3.3V
1.5kΩ D+
P22/SOT0_0
10kΩ
Vbus
X0
Device
10kΩ
USB connector
D-
4MHz or 48MHz
MD1
Serial write: 0
VSS
Note: The pull-up and pull-down resistance values shown are for example. Select the most appropriate resistance values for each system. Insert a level shifter for each system.
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
Figure 1-6 Connection example using Spansion USB DIRECT Programmer (own power supply is used, for TYPE9 products) User system
VCC
10kΩ Serial write: 1
Serial write at USB communication mode 4MHz : 0 48MHz : 1
Regulator 3.3V output
27Ω
INITX
P60/INT15_1 51kΩ UDM0
10Ω
Level Shifter
100kΩ
P61/UHCONX UDP0
27Ω GND
X1
MD0
P22/SOT0_0
3.3V
1.5kΩ D+
USBVCC Level Shifter
Vbus
D-
X0
Device
10kΩ
10kΩ
USB connector
4MHz or 48MHz
MD1
Serial write: 0
VSS
Note: The pull-up and pull-down resistance values shown are for example. Select the most appropriate resistance values for each system. Insert a level shifter for each system.
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
Figure 1-7 Connection example using Spansion USB DIRECT Programmer (bus power supply is used, for TYPE6 and TYPE8 products) User system
VCC
10kΩ Regulator 3.3V output
Serial write : 1
Serial write USB communication mode 4MHz : 0 48MHz : 1
X1
MD0
P22/SOT0_0
10kΩ
X0
Device
10kΩ
USB connector Vbus
4MHz or 48MHz
MD1
Serial write : 0
INITX
P60/INT15_1 51kΩ
D27Ω
1.5kΩ D+
UDM0
3.3V
10Ω
Level Shifter
100kΩ P61/UHCONX UDP0
27Ω GND
VSS
Note: The pull-up and pull-down resistance values shown are for example. Select the most appropriate resistance values for each system.
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
Figure 1-8 Connection example using Spansion USB DIRECT Programmer (bus power supply is used, for TYPE9 products) User system
VCC
10kΩ Serial write : 1
Serial write USB communication mode 4MHz : 0 48MHz : 1 USB connector Vbus
X0
X1
MD0
Device
10kΩ
P22/SOT0_0
10kΩ
INITX
Regulator 3.3V output
4MHz or 48MHz
MD1
Serial write : 0
USBVCC
P60/INT15_1 51kΩ
D27Ω
1.5kΩ D+
UDM0
3.3V
10Ω
Level Shifter
100kΩ P61/UHCONX UDP0
27Ω GND
VSS
Note: The pull-up and pull-down resistance values shown are for example. Select the most appropriate resistance values for each system.
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CHAPTER 3 Serial Programming Connection 1. Serial Programmer
1.2. Pins Used This section explains the used pins. Table 1-2 Pins used for serial write Pins
Function
Supplement
MD0, MD1
Mode pin
Performing an external reset or turning on the power after setting MD0=H and MD1=L enters the serial write mode. When attaching a pull-up or pull-down resistor, avoid long wiring.
X0, X1
Oscillation pin
See the "Data Sheet" of a product used for the source oscillation clock (main clock) frequencies that can be used in serial write mode. (Restrictions apply to clock asynchronous communication. For details, see Table 1-2.) In UART communication mode, the write operation is available without main clock.
P22/SOT0_0
UART serial data output pin/ USB source oscillating frequency select pin
When the communication mode is set to UART, this pin becomes a serial data output pin when communication begins after the serial write mode is activated. When the communication mode is set to USB, this pin controls the frequency for source oscillation clock. P22=L : source oscillation frequency : 4MHz P22=H : source oscillation frequency: 48MHz
P21/SIN0_0
Clock synchronous/ asynchronous select pin/UART serial data input pin
Setting the input level of this pin to "H" until the start of communication enables the clock asynchronous communication mode, and setting it to "L" enables the clock synchronous communication mode. When the communication mode is set to UART, this pin can be used as a serial data input pin when communication begins after the serial write mode is activated.
P60/INT15_1
Communication mode select pin
The communication mode is determined by the input level of this pin at reset to shift to the serial write mode. Setting this pin to "H" enables the USB communication mode, and setting it to "L" enables the UART communication mode.
P61/UHCONX Pull-up control pin for UDP0
This pin controls the pull-up of USB side (D+) when the communication mode is USB. UHCONX=L : Connect the pull-up resistor UHCONX=H : Disconnect the pull-up resistor
UDP0
USB I/O pin
This pin becomes an input/output pin of USB side (D+) when the communication mode is set to USB.
UDM0
USB I/O pin
This pin becomes an input/output pin of USB side (D-) when the communication mode is set to USB.
INITX
Reset pin
-
VCC
Power supply pin
For writing, supply power to the microcontroller from the user system.
USBVCC
Power supply pin for USB I/O
USBVCC pin is available only for TYPE9 product.
VSS
GND pin
-
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F L A S H
P R O G R A M M I N G
M A N U A L
MAJOR CHANGES Page
Section
Revision 1.0 Revision 2.0 -
2 4 7, 8
Change Results
-
Initial release
-
TYPE8 and TYPE9 products are added. For TYPE6 products, product type with A added.
CHAPTER 1: Flash Memory 1. Overview Dual Operation Flash Memory Features
The following description added: "When the pre-fetch buffer function is enabled at the operation of up to 72 MHz, 0 wait could be realized (only for TYPE 9 product)".
2. Configuration
Figure 2-1 added. Figure 2-4 and Figure 2-5 added.
15
3.2.2. Command Operations Sector Erase Command
Description on sectors to be erased added.
16
3.2.3. Automatic Algorithm Run State
Figure 3-1 corrected. Undefined bit --> Reserved bit
17
Bit explanation
Reference mark changed to (Note) from 1). bit17 --> bit7 Undefined bits --> Reserved bits
21
3.3.2. Write Operation
Bit name corrected. PGRM --> PGMS
22
3.3.3. Flash Erase Operation
Corrected from "CES" to "CERS".
4.1 FRWTR (Flash Read Wait Register)
TYPE6 and TYPE8 products added. Changed from "0 to 1 cycles wait mode" to "Pre-fetch mode". Description on TYPE9 for Freesia product is added.
CHAPTER 3: Serial Programming Connection 1. Serial Programmer 1.1. Basic Configuration
Table 1-2 in columns of "Source Oscillating Frequency 48MHz" deleted.
29, 30
44 47, 49 Revision 2.1 Revision 3.0 4 - 10
Figure 1-5 and Figure 1-7 added. -
Company name and layout design change
-
Part number added to TYPE6 and TYPE8 products.
CHAPTER 1: Flash Memory 2.Configuration
Corrected Title of Table 2-1 and Figure2-1 to 2-6.
11
3. Operation Explanation
Corrected Title of 3.4.
14
3.2.1.Command Sequences
Added notes pertaining to CR Temperature Trimming Data.
30
4.Registers 4.1. Flash Read Wait Register (FRWTR)
Corrected description of RWT = 01.
38
4.6.CR Trimming (CRTRMM)
Split a description for each product. Added description of “CR Temperature TYPE8/TYPE9 product.
10
Data
Figure 2-7 added.
Mirror
Register
Trimming
Data”
to
Corrected description of “Basic Configuration of Spansion MCU Programmer (Clock Asynchronous Serial Write)”
46
CHAPTER 3: Serial Programming Connection 1.Serial Programmer 1.1.Basic Confuguration
53
1.2.Pins Used
Corrected description of “X0,X1”
45
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F L A S H
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CONFIDENTIAL
P R O G R A M M I N G
M A N U A L
MB9AB40N_MN706-00019-3v0-E, September 8, 2014
MN706-00019-3v0-E Spansion・Controller Manual
32-BIT MICROCONTROLLER MB9AB40N/A40N/340N/140N/150R/ MB9B520M/320M/120M Series FLASH PROGRAMMING MANUAL September 2014 Rev. 3.0
Published: Edited:
Spansion Inc. Corporate Communications Dept.
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Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2012-2014 Spansion. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
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