Transcript
Information Societies Technology (IST) Program
AMDREL Architectures and Methodologies for Dynamic Reconfigurable Logic Contract No IST-2001-34379
Deliverable D39 Dissemination and Use Plan (DUP) including web site by DUTH
Editor: Status - Version: Date: Confidentiality Level: ID number:
INTRACOM Final – v.6 11 February 2005 CONFIDENTIAL IST-2001-34379/WP7/D39/ICOM/R
© Copyright by the AMDREL Consortium The AMDREL Consortium consists of: INTRACOM S.A. (ICOM) STMicroelectronics Belgium (STMB) Interuniversity Microelectronics Centre (IMEC vzw) Democritus Univ. of Thrace (DUTH) Aristotle University of Thessaloniki (AUTH)
Prime Contractor Contractor Contractor Contractor Subcontractor
Greece Belgium Belgium Greece Greece
Deliverable D39
Page 2 of 77
DISCLAIMER The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability.
1.
ACKNOWLEDGEMENTS
The editor (INTRACOM) acknowledges contributions by IMEC, STMB, and DUTH.
2. 07/12/04 13/12/04 17/12/04 04/01/05 12/01/05 11/02/05
Date
DOCUMENT REVISION HISTORY
Version 1 2 3 4 5 6
IST-2001-34379/WP7/D39/ICOM/R
Editor/Contributor INTRACOM INTRACOM/IMEC INTRACOM/DUTH INTRACOM/STMB INTRACOM INTRACOM/IMEC
Comments 1st Draft version IMEC contribution DUTH contribution STMB contribution Pre-final version Final version
AMDREL Consortium
Deliverable D39
Page 3 of 77
3.
PREFACE
The main objectives of the AMDREL project are: Development of systematic methodologies for high level design tasks (such as behavioural optimisation with respect to different implementation related factors and especially with respect to power consumption, partitioning of targeted functionality to different types of reconfigurable hardware), Development of reusable intellectual properties (including coarse granularity dynamically reconfigurable hardware blocks, low power fine-granularity configurable logic blocks, etc.), Instantiation of tools for implementation tasks, Establishment of a dynamically reconfigurable SOC platform with mixed granularity components (fine and coarse grain), Validation through demonstrators, and Use and dissemination of the results. The expected results of the project are: A mixed granularity dynamically reconfigurable SoC architecture template, Systematic methodologies for behavioural optimisation and partitioning, High level tools and reusable IPs, Fine and coarse grain reconfigurable SoC components/interconnect network, Real-life applications/demonstrators, Dissemination to a wider community and use concluding activities. The AMDREL project has started its activities in March 2002 and is planned to be completed by the end of June 2005. It is led by M.Sc. Konstantinos Potamianos and Dr. Konstantinos Masselos of INTRACOM. Four contractors (INTRACOM, STMB, IMEC vzw and DUTH) and one subcontractor (AUTH) participate in the project. The total budget is 4.015 k€.
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 4 of 77
4.
ABSTRACT
This deliverable of the AMDREL project addresses the consortium dissemination activities and use strategy. There is also a description of dissemination and use plans per partner. This document is the second version of the Dissemination and Use Plan according to project’s work plan. It describes the results from the AMDREL project and contains an update on the procedures and methods that are and will be used to disseminate them to a broader audience. Finally, there is an update on how the project’s results will be exploited by the partners to further develop their business activities. First, the AMDREL’s common vision is described and how each partner shares this vision. Then an updated overview is given of the market and also the results that will be publicly disseminated. Tables with statistics of various dissemination events (confererences, courses, etc.) are also provided. Afterwards an overview is given of the consortium confidential results that will be exploited by one or more project partners. Among the dissemination activities the following methods can be distinguished: presentations at several technical conferences, workshops; publications; journals; the construction of a project web site; postgraduate courses and seminars. It must be noticed that, none of the participating companies has the commercialisation of design tools as a core business activity. Since neither RSoCs nor systems using RSoCs are available today, the industrial partners expect to incorporate them (as a result of AMDREL activities) in their future wireless telecom products improving their competitiveness. The academic partners will exploit the project results through their inclusion into the IP portfolio of solutions offered to their clients when called upon for consultancy or similar contractual activity, thereby strengthening their market position and competitiveness in this field. In addition, the know-how will be used as training material in postgraduate courses and seminars.
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 5 of 77
5. ALU AMDREL BFWA CAD DCM DLC DMT DSP DVD ETSI FFT FIFO FPGA FSM Hiperlan-2 HW IC IP IEEE 802.11 IFFT ISM ISO ISP LAN MAC MCU OFDM OSI PDU: PHY QoS RAM RF RISP SoC SOHO SW TDMA Viterbi WLAN
LIST OF ABBREVIATIONS
Arithmetical and Logical Unit Architectures and Methodologies for Dynamic Reconfigurable Logic Broadband Fixed Wireless Access computer aided design Digital Clock Multiplier data link control discrete multi-tone digital signal processing digital versatile disk European telecommunications standards institute fast fourier transform first-in first-out buffer or memory field programmable gate array Finite state machine Specification of a wireless LAN standard based on OFDM, published by ETSI hardware integrated circuit Intellectual Property Family of standards for wireless LAN published by the American IEEE inverse fast fourier transform industrial, scientific and measurement band International Standards Organisation internet service provider or Instruction-Set Processor (context dependent) local area network media access control micro-controller unit orthogonal frequency-division multiplex Open System Interface. Seven-layer communications protocol stack description model standardised by the ISO protocol data unit physical communication layer (OSI Layer 1) quality of service Random Access Memory radio frequency reconfigurable instruction-set processor system on chip small office/home environment software time-division multiple access an algorithm for maximum likelihood sequence estimation, used for decoding convolutional forward error correction codes wireless local area network
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 6 of 77
6.
LIST OF TABLES
Table 1: Main considerations for multimode operation ................................................................. 14 Table 2: Main characteristics of several WLAN market segments.............................................. 15 Table 3 Comparison between the different on-chip communication solutions.......................... 23 Table 4 Stats for 2003 and 2004 about AMDREL website traffic............................................... 37 Table 5 . Stats for 2003 and 2004 about AMDREL website traffic (#hits) ................................. 37 Table 6 : #hits of the first ten publications 2003............................................................................. 37 Table 7 : #hits of the first ten reports 2003 ..................................................................................... 38 Table 8 : #hits of the first ten publications 2004............................................................................. 38 Table 9 : #hits of the first ten reports 2004 ..................................................................................... 39 Table 10: Statistics of AMDREL website for 2003......................................................................... 39 Table 11: Statistics of AMDREL website for 2004......................................................................... 41 Table 4 Worldwide BWA unit shipments forecast for Backhaul applications ............................ 61 Table 5 Percentage of the unlicensed bands ................................................................................. 61 Table 6 Worldwide outdoor bridge unit shipments forecast ......................................................... 61 Table 7 Fixed cost of the bridge product......................................................................................... 66 Table 8 BOM of the bridge product.................................................................................................. 67 Table 9 Summary of the variable costs per bridge........................................................................ 67 Table 10 Percentage of the wireless outdoor market covered by the EEMEA area ................ 68 Table 11 Bridge unit shipments forecast in the EEMEA area...................................................... 68 Table 12 Bridge’s ASP (Average Selling Price in €) forecast for indoor/outdoor architecture 68 Table 13 Scenarios for INTRACOM’s percentage of the bridges market in the EEMEA area69 Table 14 INTRACOM’s bridge unit shipments forecasts (aggressive and moderate scenarios) ........................................................................................................................................... 70 Table 15 INTRACOM’s total unit shipments, cost, profit and revenue forecasts at the end of each year (aggressive scenario).................................................................................. 71 Table 16 INTRACOM’s total unit shipments, cost, profit and revenue forecasts at the end of each year (moderate scenario) .................................................................................... 71 Table 17 Break-even point details and ROI percentage for both aggressive and moderate scenarios ......................................................................................................................... 72
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 7 of 77
7.
LIST OF FIGURES
Figure 1: The AMDREL project aim at providing the necessary technologies to efficiently map applications on adequate reconfigurable system-on-chip............................... 10 Figure 2: Wireline vs. Wireless infrastructure development ......................................................... 13 Figure 3: Total WiFi Revenue by protocol (US$ millions), 2000-2008 ....................................... 15 Figure 4: Total WLAN chipset shipments (thousands)and revenue (M$), 2001-2007............. 16 Figure 5: Hotspots, World Market (thousands), 2003-2007 ........................................................ 17 Figure 6: Worldwide sub-11GHz subscriber base – 802.16a and proprietary .......................... 19 Figure 7: BWA Equipment Forecast, 2004-2008 (units)............................................................... 20 Figure 8: BWA Equipment Revenues by Frequency Forecast, 2004-2008............................... 20 Figure 9: Overall use plan for AMDREL project............................................................................. 30 Figure 10: AMDREL’s web site......................................................................................................... 36 Figure 11: INTRACOM wireless systems ....................................................................................... 49 Figure 12: INTRACOM’s turnover 1999-2003................................................................................ 50 Figure 13: WLAN Silicon Market Evolution, 802.11Summary (Shipments by Technology).... 54 Figure 14: INTRACOM’s wireless access network systems ........................................................ 60 Figure 15: INTRACOM’s plans to fill the frequency gap............................................................... 60 Figure 16: Worldwide outdoor bridge unit shipments forecast .................................................... 61 Figure 17: Point-to-point wireless link through Ethernet bridges with indoor/outdoor architecture...................................................................................................................... 66 Figure 18: Block diagram of the wireless Ethernet bridge product ............................................. 66 Figure 19: Bridge unit shipments forecast in the EEMEA area ................................................... 68 Figure 20: Bridge’s ASP (Average Selling Price) forecast for indoor/outdoor architecture..... 69 Figure 21: INTRACOM’s bridge unit shipments forecast per year (aggressive & moderate scenarios) ........................................................................................................................ 70 Figure 22: INTRACOM’s total cost, profit and revenue forecasts as functions of time (aggressive scenario) .................................................................................................... 71 Figure 23: INTRACOM’s total cost, profit and revenue forecasts as functions of time (moderate scenario)....................................................................................................... 72
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 8 of 77
8.
TABLE OF CONTENTS
Disclaimer .............................................................................................................................................. 2 1. Acknowledgements....................................................................................................................... 2 2. Document revision history ........................................................................................................... 2 3. Preface ........................................................................................................................................... 3 4. Abstract .......................................................................................................................................... 4 5. List of Abbreviations ..................................................................................................................... 5 6. List of Tables ................................................................................................................................. 6 7. List of Figures ................................................................................................................................ 7 8. Table of Contents.......................................................................................................................... 8 9. Vision ............................................................................................................................................ 10 10. PART 1: Overview .................................................................................................................. 12 10.1. Market Overview ........................................................................................................... 12 10.1.1. Market Drivers ........................................................................................................... 12 10.1.2. Market Projections.................................................................................................... 15 10.1.3. Competition Analysis................................................................................................ 20 10.2. Benchmarking................................................................................................................ 22 10.3. Overview of expected results ...................................................................................... 28 10.3.1. Results to be disseminated ..................................................................................... 28 10.3.2. Results to be used.................................................................................................... 29 10.3.3. Approach to Dissemination ..................................................................................... 29 10.3.4. Approach to use........................................................................................................ 29 11. Part 2: Description of Dissemination Activities................................................................... 31 11.1. Conferences................................................................................................................... 31 11.2. Publications.................................................................................................................... 34 11.3. Web presence................................................................................................................ 36 11.4. Clustering and Standardization (inputs from partners)............................................ 43 11.5. Other ............................................................................................................................... 43 12. Part 3: Description of the Use Plan (by results) ................................................................. 45 12.1. Overview of Results...................................................................................................... 45 12.2. Detailed description of result D11............................................................................... 45 12.2.1. Description of result D11 ......................................................................................... 45 12.2.2. Market size of result D11......................................................................................... 45 12.2.3. Approach, timing for use of result D11 .................................................................. 47 12.3. Detailed description of result D14............................................................................... 47 12.3.1. Description of result D14 ......................................................................................... 47 12.3.2. Market size of result D14......................................................................................... 47 12.3.3. Approach, timing for exploitation of result D14 .................................................... 47 12.4. Detailed description of result D15............................................................................... 48 12.4.1. Description of result D15 ......................................................................................... 48 12.4.2. Market size of result D15......................................................................................... 48 12.4.3. Approach, timing for exploitation of result D15 .................................................... 48 12.5. Detailed description of result D18,21 ......................................................................... 49 12.5.1. Description of result D18,21.................................................................................... 49 12.5.2. Market size of result D18,21 ................................................................................... 49 12.5.3. Approach, timing for exploitation of result D18, 21.............................................. 51 12.6. Detailed description of result D23............................................................................... 52 12.6.1. Description of result D23 ......................................................................................... 52 12.6.2. Market size of result D23......................................................................................... 52 12.6.3. Approach, timing for exploitation of result D23 .................................................... 52 12.7. Detailed description of result D25............................................................................... 53 12.7.1. Description of result D25 ......................................................................................... 53 IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 9 of 77
12.7.2. Market size of result D25......................................................................................... 53 12.7.3. Approach, timing for exploitation of result D25 .................................................... 54 12.8. Detailed description of result D26,27,28,29,30 ........................................................ 56 12.8.1. Description of result D26,27,28,29,30 ................................................................... 56 12.8.2. Market size of result D26,27,28,29,30................................................................... 56 12.8.3. Approach, timing for exploitation of result D26,27,28,29,30 .............................. 56 ANNEX I ............................................................................................................................................... 58 Abstract ................................................................................................................................................ 59 1. Introduction .................................................................................................................................. 59 2. Market Overview ......................................................................................................................... 61 3. System Overview and Architectures........................................................................................ 65 4. System Costs............................................................................................................................... 66 5. INTRACOM Business Case ...................................................................................................... 67 ANNEX II .............................................................................................................................................. 73
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 10 of 77
9.
VISION
The consortium envisages that current design techniques will not satisfy future applications’ needs in terms of area, power and design time. The consortium is convinced that reconfigurability will be an important contributor to improved efficiency of designs, though state of the art does not show how this can be achieved in practice. Therefore, to address the stated problem, the project develops: An architectural template of a dynamic, mixed granularity reconfigurable SoC platform, supported by a set of building blocks (fine-grain, coarse-grain, interconnect) A methodology to map applications on such a mixed granularity template yielding efficient SoC design platforms
Application Application
Application Application requirements requirements
AMDREL AMDREL Generic Generictemplate template AMDREL AMDREL Blocks Blocks
AMDREL AMDREL
Application Applicationefficiently efficiently mapped mappedon onaa Reconfigurable Reconfigurable System-On-Chip System-On-Chip
Application Application executable executable Spec. Spec.
Application Applicationspecific specific Platform Platforminstance instance
AMDREL AMDREL mapping mapping methodology methodology
Figure 1: The AMDREL project aim at providing the necessary technologies to efficiently map applications on adequate reconfigurable system-on-chip Figure 1 depicts the components that will be addressed in the AMDREL project. Starting from the application requirements, an application designer will use the generic template together with the building blocks developed in AMDREL to instantiate an application (domain) specific platform. The application functional description, together with the knowledge of the instantiated platform, will be used in turn with the AMDREL mapping methodology to end up with an efficient mapping of the application on the application (domain) specific reconfigurable SoC. Partner 01: INTRACOM shares the AMDREL vision INTRACOM considers that heterogeneous reconfigurable SoC platforms (as the one targeted by AMDREL) are the best choice for realizing flexible and efficient wireless communication systems. Methodologies to support the mapping of targeted systems on the platform are vital in achieving this. Currently, INTRACOM uses platforms based on off-the-shelf reconfigurable components (FPGAs) for IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 11 of 77
the realisation of targeted systems. However, as the telecom market evolves rapidly with new products supported by a variety of standards and the complexity of systems increases, the company faces significant obstacles in keeping up with the competition and offering cost-effective products in time. This is mainly due to the current system design approach, which leads to limited design flexibility and non-optimal implementations from a cost point of view (and thus decreased competitiveness) of company’s products. It is of strategic importance for the company to overcome this situation. The AMDREL platform allows INTRACOM to evaluate the complete mixed granularity reconfigurable solution, including coarse and fine grain reconfigurable blocks, reconfigurable interconnect network and highly optimised application specific blocks for the realization of a WLAN system. Partner 02: ST Microelectronics Belgium shares the AMDREL vision STMB subscribes fully to the AMRDEL vision. It is STMB’s firm belief that top-down design methodologies, with executable specification as the primary method of system architecture exploration, are the most useful approach in addressing the extreme complexity of modern IC design. Such methodologies are neither static, nor can they stand on their own. AMDREL’s vision on the use of reconfigurability as an aid to achieving efficient designs is a new and important component in such a methodology. The implementation aspects covered by AMDREL provide at the same time the opportunity of developing blocks using the new techniques, as proof of concept, for subsequent incorporation into industrial-strength prototypes, as well as providing insights into how best these techniques can be incorporated into the prevailing SystemC-based design methodology presently in use by the WLAN IC designers. Partner 03: IMEC vzw shares the AMDREL vision IMEC’s vision on future reconfigurable SoC platforms, the heart of their Reconfigurable Systems IIAP (IMEC’s industrial affiliation program), is based on an "architecture consisting of tiles communicating via an on-chip interconnect network, where every tile contains a combination of instruction-set processors, memories, fine or coarse-grain reconfigurable hardware, application specific components, ...". This is strongly supported by the AMDREL architecture template view. The flexible interconnect network, as developed in AMDREL, is the main expertise of IMEC. However, an in-depth knowledge of the other components (fine-grain block, coarse-grain block, typical application requirements, application design and mapping methods) is required if the network has to provide an efficient communication mechanism for the platform. Sharing AMDREL’s vision with the other partners is therefore crucial for the success of IMEC’s research. Partner 04: DUTH shares the AMDREL vision DUTH believes that a synthetic, dual approach, combining top-down and bottom-up methods, is a powerful answer to complex SoC design issues. AMDREL’s vision offers a framework for applying both methods by using a novel mixed-granularity architecture template and supporting blocks. In order to support the template-based approach, methodologies and hardware blocks need to be developed. A common view on an architecture template, such as provided by AMDREL, is important in structuring the top-down approach, e.g. behavioural level optimisation, starting from the high-level specification code. On the other hand, the implementation of custom fine-grain reconfigurable hardware and their supporting tools supports the bottom-up approach. The AMDREL project will allow the integration of these supporting models into an architecture template instantiation as proof of concept. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 12 of 77
10. PART 1: OVERVIEW 10.1.
Market Overview
10.1.1.
Market Drivers
Reconfigurable Platforms Reconfigurable hardware solutions are very crucial in the domain of telecom application where standards are emerging and high degree of flexibility is needed. Application Specific ICs (ASICs) will continue to be an important design technology for a smaller and smaller set of high performance applications and will continue to be the design technology of choice when the problem is closer to the core of the network. However, as the problem moves closer to the access side programmable technologies, whether they involve programmable standard products or field programmable chips, will and are becoming a desirable choice. The need for absolute performance gives way to the need for design flexibility, multiprotocol functionality and fast time-to-market. When highest performance is the requirement, then ASIC SoC customized products or standard products (ASSPs) are the choice but they suffer from poor design flexibility and poor time-to-market. When flexibility to respond to technology and market changes is required then programmable technologies are chosen: a) b) c)
Design Houses can achieve fast-embedded system customization (reduced time-to-design changes). Chip Manufacturers can quickly develop ‘new’ systems based on new protocols and standards. System Integrators can address the demands of the market by adding sew features to their systems.
Wireless vs. Wireline Solutions Over the last decades, competition has opened up many sectors of the telecom and entertainment markets. Broadband wireless communication systems rapidly emerged as important competitive enablers for communicators in the global telecommunications market place. One of the most significant advantages of such systems concerns their installation and maintenance cost. Several studies propose that the cost for deployment of fixed wireless networks is the lowest of all currently available transport streams and has the potential to provide connectivity solutions to remote areas in less time. Besides, with no physical transmission media between the transmitter and receiver, maintenance of wireless systems is limited to tasks such as network monitoring, diagnosis, and tuning. Comparable wireline systems, however, require extensive maintenance and rewire about every ten years, as well as on-going, routine maintenance. The “cheaper-than-wired” solutions are linked to the quick entering of the market. Fixed wireless access stations are faster, easier and cheaper to roll out than the equivalent coverage which cable or fiber would allow. A new broadband wireless access network can be active within a fraction of the time of a new fixed line network. (figure 2). The majority of the required capital investment is spent when a wireless customer is set up, enabling the service provider to build the network as customers come online. This means that return on investment is rapid and directly related to the number of customers.
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 13 of 77
Equipment expenditure
Wireline network investment Wireless network investment
N
b um
er
o
e rib c s b f su
rs
Time Figure 2: Wireline vs. Wireless infrastructure development Broadband wireless will be particularly successful in satisfying the demand for new services – from basic telecommunications and TV services in developing countries, to advanced interactive services in developed countries. Technological advances in the long-term will likely enable providers to add enough uplink channel capacity to facilitate wireless telephony service. Besides, with very large bandwidth, wireless access have the long-term potential to deliver a wide range of new Internet services including residential video telephony, business video conferencing, wireless remote LAN access, internet access, and even an ability to download software. It is significant that high capacity enables service providers to support the exponential growth in data communications traffic being driven by use of Internet, corporate intranets and extranets. All these factors are related to improved customer satisfaction due to lower cost and the lower downtime. With few costs associated with network maintenance, providers of wireless service can pass these savings onto customers. Also, while extensive downtime of wired cable networks often leave customers dissatisfied with their provider, the marginal disruption inherent to wireless service has a positive impact on customer satisfaction.
Multimode Operation Within the project two partners (INTRACOM and STMB) are focusing on wireless communications market segment for outdoor use. According to a report by Texas Instruments (http://www.ti.com, November 2002) the stage is set for a multimode marketplace. Two sets of dynamic forces argue for a multimode ‘wireless environment’. First, it can be stated with some surety that not all standards are created equal. Each of the several versions of the wireless standards has its own strengths and advantages and set of operational and economic characteristics. A multimode model ensures that the strengths of all of the modes of operation will persist in the market place. Second, the various market segments, such as the enterprise, the so-called hotspot or public access segment and the home and embedded market segments each have a distinct set of demands and requirements that differ from each other. Again, a multimode model of operation is best suited to meeting all of these needs across the broad spectrum of a diverse wireless communications marketplace. The following tables summarize the critical points that lead to multimode operation and the specific characteristics of each market segment. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 14 of 77
Characteristic
Reason for multimode operation
Cost
Forecasts for equipment costs prove that multistandard capable equipment will have costs at the same level of single standard when SoC.
Transmission speeds
Need to support both high and low speeds at least for a transitional period to allow operation of low speed equipment Different transmission speed requirements per market segment
Power Consumption
Discrepancy in power consumption among different wireless communication modes Need to accommodate requirements of battery driven systems and of unlimited power supply driven systems
Range
Increased range leads to reduced deployment cost due to the smaller Access Points required. Applications requiring increased range (covering large facilities) should support coming and going users (possibly operating in different modes) Table 1: Main considerations for multimode operation
Market Segment
Key Features/Requirements
Reason for Multimode Operation
Enterprise
Highest guaranteed speed possible Clients: Non mobile desktop users
Need to support already installed 802.11b access points and clients in a transitional phase to 802.11a and 802.11g Unpredictable type of 802.11 clients (to evolve) Need to support both 802.11a and 802.11g both from access point and client point of view Take advantage of two frequency bands to maximize throughput
“Hotspots” Public Access
Accommodation of a diversity of mobile device types and WLAN modes Almost always used for Internet access (limited speed) No great need for high speed clients: Mobile devices enter and leave frequently the WLAN/short time of access
Operational mode of client devices cannot be anticipated Ability to handle the most diverse set of clients and service requirements
Home
Cost/ease of use/ease of installation Data centric applications sharing Internet access Limited speed requirement Ability to connect rich content devices at the highest possible speed Number and types of devices accessing home WLAN are small and fairly constant
When price advantage of 802.11b narrows move to higher speeds 802.11a and 802.11g Appearance of new entertainment technologies like digital TV at home with increased rate requirements move to higher speeds 802.11a and 802.11g
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Embedded
Page 15 of 77
Power, Size, Cost
Requirements currently covered by 802.11b. Situation expected to change when 802.11g becomes comparable
Table 2: Main characteristics of several WLAN market segments
10.1.2.
Market Projections
WLAN market situation after the end of 2002 The dominance of IEEE802.11 standards has been given a further push in recent years. The early establishment of the “WiFi” brand-mark of the similarly named industry alliance, which gives end users confidence in the interoperability of terminal equipment and access points, is also a strong driver for the early commercial success of the IEEE standard. The major weakness of any Ethernet-based network (like IEE802.11) is the intrinsic lack of support for QoS, specifically the ability to modulate the network parameters to offer the most appropriate mix of speed, error-rate and delay, required by speech and multi-media applications. Though, despite the apparent technical disadvantage for wide-scale adoption, most players are now conceding to the dominance of the IEEE family standards. This is being further strengthened by the adoption of improved features for the support of QoS in IEEE802.11a derived standards such as ‘802.11g and ‘802.11i. The adoption of IEEE802.11 as the most-likely internationally accepted standard being given, the requirement to offer support of the several IEEE802.11 flavours in one solution (dual band chipsets), is now being seen as the key market driver (Fig. 3). In terms of standardisation, IEEE802.11g was ratified in June 2003. WiFi certification extended to cover 802.11g, as well as establishing label for public “hotspots”. According to Allied Business Intelligence (http://www.alliedworld.com, February 2003) more than 50% of the WLAN revenue by 2005 will come from dual-mode chipsets, and that in addition, beyond 2004, a significant portion of the WLAN terminal devices will target embedded WLAN solutions, which will be therefore be integrated into the terminal electronics.
Figure 3: Total WiFi Revenue by protocol (US$ millions), 2000-2008 Source: Allied Business Intelligence, February 2003 IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 16 of 77
It is worth mentioning, that these systems are mend for indoor use only (i.e. Access Points and NICs) due to regulatory issues, namely transmit power limitations for outdoor use and allocated spectrum. With the resent proposal for extra bandwidth in the 5 GHz unlicensed band for wireless communications from FCC, this picture is subject to changes. The following curves show the market forecast as seen by iSuppli Corp, as of March 2003. The growth of WLAN shipments is predicted to continue strongly, though the growth of revenue will flatten (or even decline) due to the equally significant erosion of the ASP, as shown in the second graph (Source – iSuppli Corp, March 2003).
1000
100 90
900 U n it S h ip m e n t s
80
R e ve n u
800
70
700
60
600
50
500
40
400
30
300
20
200
10
100
0
Revenue (M$)
Unit Shipments (Thousands)
W L A N W o r ld w id e C h ip s e ts M a r k e t F o r e c a s t
0 2001
2002
2003
2004
2005
2006
2007
Figure 4: Total WLAN chipset shipments (thousands)and revenue (M$), 2001-2007 Source: iSuppli Corp, March 2003 From this, the total volume of semiconductor shipments for the WLAN market has been slightly moderated, but more importantly, the tailing-off of the revenues while the market volume continues to grow indicates a very strong price erosion. As this market is becoming highly consumer-oriented, one can be certain that suppliers who are unable to follow this aggressive price trend will be efficiently excluded from participating. Hotspot roll-out was not as fast as predicted, due to market uncertainty, the uncertainty of viable business models, technical issues such as lack of harmonization of the different WLAN standards, and regulators (particularly in Europe) delaying the availability of the 2.4GHz spectrum for public WLAN use. Pricing levels were set too high forcing many hotspot providers to reduce subscription fees and introduce discounts (e.g. to its GSM subscribers). However, despite the relatively small absolute size of the public WLAN market, it represents a significant proportion of the revenue achievable from forthcoming high-speed mobile data services, as well as of wireline revenue. According to Allied Business Intelligence, the revenue generated by this market will grow with a Compound Annual Growth Rate (CAGR) of 121% over the next 5 years while hotspot will grow to nearly over 160.000 locations by 2007 (Fig. 5). It must be remembered that the roll-out of public hot-spots affects only quite a small part of the total market for WLAN devices. Even without the GSM-like “roaming” capability which can be offered by public WLAN hot-spot operators, private hot-spot exploitation for one-off “nomadic” use (exemplified by the “coffee-shop” model), as well as the usual domestic and business applications for WLAN, will account for the most significant part of the market. The appearance of WLAN-enabled multi-media equipment for the home (e.g. Internet radios, Hi-Fi MP3-players, and even video distribution equipment) will further drive the market for domestic use of WLAN technology. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 17 of 77
Figure 5: Hotspots, World Market (thousands), 2003-2007 Source: Allied Business Intelligence, April 2003 Much of the market growth for WLAN has been attributed to broadband gateway devices (such as access points for public WLAN use), where the WLAN functionality has now become a necessary item for participation in the DSL CPE market. However, also driven by the very low price such units can attract in the consumer market place, alternative deployment architectures for home broadband access are now being investigated. The perceived value of a broadband (DSL, Cable) wireless LAN router, once installation has been completed, is extremely low: the functionality it provides offers no visible benefits to the user. The emergence in recent years of digital, multi-media services over DSL or other broadband data access technologies open new possibilities. By integrating the access and networking technology into units which do have a high perceived value, such as set-top boxes for interactive TV, the price pressure can (at least initially) be countered by offering very visible added value. Such features as PVR (personal video recording), time-shift (delayed playing of live programmes to account for interruptions in viewing), decryption for pay-TV etc… offer value with a potential price premium. It is already common for such units to offer best-effort (WLAN-based) Internet service in parallel to the broadcast / multicast TV service (examples include “Freebox” already available in parts of France today – end 2004). To quantify this, Instat predicts that the TAM for DSL set-top box installations will grow from 1.3MU world-wide in 2004 to 7M units in 2008. BFWA system Analysts have put forward a number of factors to explain the financial difficulties experienced in 2001 and 2002 by some telecommunication carriers. In some cases, market exit results because of decreasing demand for a product or service. On the whole this is not the case for the telecommunications market. While the telecommunications market grew more slowly in 2001 than in previous years, the overall size of the market expanded. Throughout 2002, the available evidence suggested that demand for telecommunication services did not decline. In some cases, of course, there may be a shift in demand between services. Examples might include DSL or cable modems replacing second residential lines, Internet protocol (IP) telephony substituting for public switched telecommunication network (PSTN) telephony or cellular mobile substituting for some fixed network services. To date, change in telecommunications has occurred at a relatively slow pace compared to what might be expected in the future. The factors that have resulted in market exit or extreme financial distress have not been, in large part, due to the shifting demand between services for a variety of reasons: IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 18 of 77
As the changes begin to impact telecommunication carriers, changes in pricing and service strategies have taken place in response to these challenges. Many telecommunication carriers operate across all market segments. Accordingly, they may well be providing the services that are substituting for traditional services. The telecommunication sector continues to generate new services. Nonetheless, the longer-term change resulting from technological development is having an impact. If IP networks are less expensive to build and operate than PSTNs, carriers will need to make that transition if they are to be competitive. At the same time liberalization has curtailed tremendously the monopoly rents extracted from long distance services, international services and leased lines. The transition to lower prices for some telecommunication services and the availability of new services, such as broadband access, are extremely beneficial for users and overall economic development. Understanding the root causes of any “financial bubble” is a complex matter. While many factors are involved, the basic premise of the bubble was that the telecommunication market would continue to grow at the very high rates experienced as liberalization increased across the OECD (Organization for Economic Cooperation and Development) countries. While the telecommunications market, including the Internet, did continue to grow, it did not do so at the pace projected by many of the business models assembled by new entrants or in the strategic plans of incumbents. Much of the financial community appears to have had an unrealistic understanding of a) the time it would take new entrants to establish a competitive presence in local access and b) the ease with which multiple entrants could enter backbone markets. Contributing to this lack of understanding was the lack of reliable data in areas such as Internet traffic growth. Moreover, it now appears that some information was misleading and fraudulent. The result was that the financial community provided capital for unrealistic business models both in terms of entry into new geographical markets and new service markets. In the latter case, this involved providing financing that resulted in very high amounts being paid for UMTS licenses. In terms of geographical expansion, telecommunication carriers paid very high prices to acquire operators outside their traditional markets. At the close of 2002, the telecommunications sector had experienced two years of slower growth than many had expected at the end of the 1990s. While basic access to fixed and cellular mobile had stabilized in countries with high penetration rates, the development of new services was making steady progress in an increasing number of countries. The number of broadband subscribers in OECD countries, for example, surpassed 50 million by the beginning of 2003. At the same time it was of concern that in some countries service had not yet commenced or that in others prices were far higher than in countries with high growth rates. Those telecommunication carriers taking a proactive role in developing broadband appear to be best placed to be competitive as markets continued to develop following liberalization. European telecoms liberalisation in the late 1990s was supposed to usher in a new era of 'last mile' competition. It never happened. ILECs (Incumbent Local Exchange Carriers) still dominate the local loop and face little competitive pressure to lower their leased line tariffs. The main reason why Europe's ILECs still have a stranglehold on the last mile is that the CLECs (Competing Local Exchange Carriers) have wasted too much time and money on interconnection issues with the incumbent. What the CLECs should have done is to focus on rolling out an alternate fixed wireless access network. By doing so they would have gained immunity from ILEC spoiling tactics over local loop unbundling (LLU) and have a much healthier business case as a consequence. Enterprises, ISPs and Mobile Network Operators are looking for cost-effective ways to move voice and data among multiple, separate locations at broadband speeds. Copper and fiber optics solutions often fall short due to up-front costs, recurring leases from telecommunication companies and lack of flexibility to scale with the operating organization. Broadband wireless has emerged as a mean to fill IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 19 of 77
these gaps and provide a lower total cost of ownership than wired solutions, while maintaining or exceeding the reliability and performance of those technologies. In recent years, the use of BWA solutions to solve connectivity needs for both commercial and residential applications has surged in popularity. Overall system costs have dropped dramatically from the initial BWA deployments made using Multichannel Multipoint Distribution Service (MMDS) technology in the early 1990’s. the use of license-exempted radio frequency spectrum has enabled thousands of service providers to offer competitive services to leased lines, ISDN, DSL and cable modems. Today, the BWA market is shifting from initial small-scale installations to large-scale regional and national deployments as confidence in the technologies and the ability to achieve profitable business models accelerate. According to Proxim Corporation (www.proxim.com), accelerating demand for broadband connectivity around the world in residential and commercial settings continues to drive the BWA market.
Figure 6: Worldwide sub-11GHz subscriber base – 802.16a and proprietary Source: Intel Capital According to Maravedis Inc. (www.maravedis-bwa.com), Fixed Broadband Wireless market (sub11Ghz) will grow from $430 million in 2003 to more than $1.6 billion by the end of 2008. In 2003, BWA shipments increased 45% over 2002. Vendors have announced both multi-million dollar contracts and hefty growth earnings compared to 2002. Technology news editors are now talking about a BWA come back with the emergence of millions of WiFi access points connected by more flexible and less costly fixed wireless solutions. Despite the 2001-2002 market slowdown, the steady demand for bandwidth, coupled with wider access to the Internet and data in general, provide sound fundamentals for expecting future growth in both telecom services and equipment sales in the first/last mile. In other words, both residential and business subscribers worldwide are demanding faster connections for their applications and operators are struggling to give them that access. According to the ITU, there were almost a 100 million broadband subscribers worldwide at the end of 2003. Although DSL and Cable are poised to remain the dominant broadband access technologies worldwide, wireless access technologies are becoming a reliable and cost effective complement or alternative to providing data, voice and video services. Governments worldwide are also driving the growth of Broadband through continuing frequency allocation and programs to subsidize broadband deployments in order to reduce the digital divide between regions of high and low density areas. Some key findings include: There were over 10,000 P-MP BWA (sub 11Ghz) base stations and 1.2 Million CPEs IST-2001-34379/WP7/D39/ICOM/R AMDREL Consortium
Deliverable D39
Page 20 of 77
installed worldwide providing 256Kbps+ broadband services to over 1.5 million subscribers and their number will grow with a CAGR of 41% and 53% respectively. While the EMEA region representing the 32% of the overall market in 2003 continues to represent the largest market opportunity, Asia will outpace it by 2005. 3.5Ghz, the most allocated frequency band for BWA, represents the largest opportunity for BWA representing 40% of total sales followed by the 5.2-5.8Ghz band. We believe the 2.3 and 2.5-2.7Ghz market share will grow to 25% of the market by 2008
Figure 7: BWA Equipment Forecast, 2004-2008 (units) Source: Maravedis Inc., February 2004
Figure 8: BWA Equipment Revenues by Frequency Forecast, 2004-2008 Source: Maravedis Inc., February 2004
10.1.3.
Competition Analysis
A large number of reconfigurable hardware technologies are either commercially available or at their early stages to enter the market. They can be roughly classified to three major categories: a) Field Programmable Gate Arrays, b) devices with coarse grain reconfigurable resources and c) embedded reconfigurable cores. Field Programmable Gate Arrays (FPGAs) currently represent the most popular and mature segment of reconfigurable hardware market. Technology advances keep increasing the gates counts and IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 21 of 77
memory densities of FPGAs while they also allow the integration of functions ranging from hardwired multipliers to high speed transceivers and all the way up to (hard or soft) CPU cores with associated peripherals. There are a number of companies building FPGAs including Actel, Altera, Atmel, Lattice Semiconductor, Quicklogic and Xilinx with Xilinx and Altera being the market leaders. In order to differentiate, FPGA vendors have introduced devices to address different intersections of performance, power, integration and cost targets. The strategy adopted by both key players (Xilinx and Altera) is to have one line of sophisticated but also higher cost devices (Xilinx Virtex 4 and Altera Stratix II) and one line of low cost devices (Xilinx Spartan 3 and Altera Cyclone II) but also with a lower set of capabilities. Despite technology progresses and the combination of conventional FPGA architectures with hardwired functions FPGAs are still lagging ASICs in terms of area and power efficiency. Furthermore their per gate cost is still prohibitively high for their use in large volume products. Integrated circuits with embedded coarse grain reconfigurable resources represent an alternative to FPGA ICs. These architectures are in principle based on a combination of a programmable CPU and a reconfigurable array of word level (coarse grain) data path units. Such devices mainly target DSP applications and are competitors of conventional DSP instruction set processors. The technology is less mature than FPGAs however promises important advantages over FPGAs such as power and silicon area efficiency. In this direction QuickSilver Technology offers Adapt2000 system platform (architecture template and tools). The platform is based on adaptive computing technology and a coarse grain architecture template and attempts to integrate the silicon capability of ASIC, DSP, FPGA, and microprocessor technologies within a single IC, an Adaptive Computing Machine (ACM). Triscend’s A7 32-bit user programmable Configurable System-on-Chip (CSoC) combines the highly popular 32-bit ARM7TDMI processor core with programmable logic, a robust memory subsystem, a high-performance dedicated internal bus, and many other system functions onto a single chip. IPFlex also tried to address the “hardware performance under software flexibility” objective through the DAPDNA dynamically reconfigurable processor. The DAPDNA-2 dynamically reconfigurable processor is a dual-core processor, comprised of IPFlex's own DAP high-performance RISC core, paired with the DNA two-dimensional processing matrix (an array of processing elements comprised of computation units, memory, synchronizers, and counters). The MRC6011 device is the first reconfigurable compute fabric device from Freescale Semiconductor. It is a highly integrated system on a chip that combines six reconfigurable compute fabric (RCF) cores into a homogeneous compute node. The programmable MRC6011 device aims at offering system-level flexibility and scalability similar to a programmable DSP while achieving the cost, power consumption, and processing capability of a traditional ASIC-based approach. The picoArray combines hundreds of array elements, each with a versatile 16 bit RISC processor. The PC102 is the 2nd generation of the picoArray highly parallel processing architecture developed by picoChip. The solution can be described as a “Software System on Chip” (SSoC): fast enough to replace FPGAs or ASICs but with the flexibility and ease of programming of a processor. Toshiba also introduced an IC device based on Toshiba’s MeP processor and Elixent’s DFA reconfigurable IP. As the System-on-Chip (SoC) world began to develop at the end of the 1990s, it was recognised that, to make the devices more useful, some form of programmable fabric would be needed. The industry responded in an enthusiastic fashion and a number of reconfigurable hardware cores that can be embedded in SoCs/ASICs have been proposed since late 1990s. Two major architectures have been mainly considered: embedded FPGAs (fine grain) and reconfigurable arrays of word level data paths (coarse grain). Despite the initial enthusiasm several of these attempts failed commercially (Adaptive Silicon disappeared while Actel stopped their embedded FPGA technology activities). Major reasons were the high silicon area (it could require half the chip area to put a decent amount of programmable logic on it) and power overheads of embedded FPGAs and the immature compilation techniques for the coarse grain reconfigurable arrays. In October 2004 during the EDA Tech Forum in San Jose, it was projected that until the first quarter of 2005 two embedded FPGA cores for ASICs/SoCs will be put on the market - one by a combination of IBM and Xilinx and the other by STMicroelectronics. The major reason that could lead these attempts to commercial success is the use of 90 nm technologies. There is still a number of commercial reconfigurable cores that can be integrated on systems-on-Chip. Leopard Logic Gladiator configurable logic device (CLD) family represents the only digital logic IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 22 of 77
device that combines Field Programmable Gate Array (FPGA) technology with hardwired Application Specific Integrated Circuit (ASIC) logic. Gladiator CLD aims at achieving much lower NRE charges than ASICs in combination with dramatically lower unit cost than complex FPGAs. The basic building blocks of Gladiator CLD are the HyperBlox FP (field programmable) and MP (mask programmable) fabrics, which are combined with optimized memories, Multiply-Accumulate units (MACs) and flexible high-speed I/Os. Morpho technologies MS1 family of reconfigurable DSP cores is fully autonomous IP (soft, firm or hard) cores that function as co-processors to a host processor in a system. The MS1 rDSP architecture consists of a 32-bit RISC with 5 pipeline stages and built-in directmapped data and instruction cache, an RC Array with 8 to 64 Reconfigurable Cells (each having an ALU, MAC, and optional complex correlator unit). The cores are available as is, or may be custom designed and/or quickly integrated into any SoC, to fit the needs of the customer and application(s). An XPP processor or coprocessor from PACT can be integrated in a System-on-Chip (SoC) and can be designed from a small set of macro blocks of which the largest (ALU-PAE) is in the range of 90 kgates. The homogeneous architecture of XPP allows synthesizing each of the blocks separately and, in the second step, arranging the synthesized blocks hierarchically to the final array. The basis for Elixent's DFA1000 accelerator is the D-Fabrix processing array - a platform that realises the potential of Reconfigurable Algorithm Processing. The structure of D-Fabrix is simple - the components are 4bit ALUs, registers and the "switchbox". Two of each are combined into a building block, the "tile". Hundreds or thousands of tiles are combined to create the D-Fabrix array. Special functions can be distributed through the array - for example, memory is always distributed to give fast, local storage with massive bandwidth. Embedded coarse grain reconfigurable cores are also available by SiliconHive a spin-off of Philips. Compared to all the above devices and IP cores the AMDREL approach utilizes the two major reconfigurable hardware architectures (fine grain in the form of embedded FPGAs and coarse grain in the form of customizable VLIW engines). This hybrid approach differentiates AMDREL from all the existing approaches described above. The aim is to achieve a pareto point in the two dimensional design space of implementation efficiency and flexibility, compared to the existing approaches.
10.2.
Benchmarking
The consortium will adopt a two-level benchmarking approach: Individual level (fine, coarse grain and interconnect network) Global level DUTH DUTH focuses its effort on: a) Development of novel design high-level methodologies, ii) Design and Implementation of critical functional blocks of RSoC architecture and iii) Development of prototype design support software for the above two activities. We selected benchmarks in a such way that provide sufficient and accurate evaluation results regarding with the novel design methodologies and techniques. We will also use the same benchmarks implemented by existing approaches/techniques for qualitative and quantitative comparative exploration study. Depending on the chosen task, we will study different parameters, not only power consumption area and performance. Various benchmarks will be used for evaluation methodologies and design techniques. More specifically, for each task we will use widely-accepted benchmarks, as follows: Task 2.1 (methodology for behavioural optimization) & 2.2 (software for source-to-source behavioral optimization): Benchmarks from NetBench and CommBench (e.g. DRR, Route) Task 2.3 (methodology for partitioning fine/coarse grain) & 2.4 (software for partitioning fine/coarse grain) .: Benchmarks from MediaBench Task 4.2 (design/implementation of fine grain reconfigurable blocks) & 4.3 (tools supporting implementation of fine grain reconfigurable hardware): Benchmarks from i) ISCAS ’89 benchmarks, ii) MCNC Benchmarks, iii) FIR (from task 2.5), iv) FFT butterfly (from task 2.5) and (v) Various parts of OFDM base band. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 23 of 77
STMB The performance of a design methodology, irrespective of any underlying optimization technique, is determined by the time it takes to make a successful circuit design. “Successful” means here that the design is functionally correct and meets all characteristic parameters, and is also testable once transferred to a manufacturing environment. It also means that the design is optimum in terms of it’s use of silicon real-estate, and that it meets the power consumption specifications as defined and refined during the design process. For benchmarking of the efficiency of a course-grained reconfigurable implementation, the following objective parameters can be used: Design effort to create and to validate (part of) a complex design. This is indicative of the “timeto-market capability” of the design process. Design complexity reduction, as measured in equivalent gate-count and processing steps required to implement a given function Power-budget margin compared to estimates of system requirements. This is rather more difficult to evaluate at steps prior to initial floorplanning in the back-end flow, as routing losses have a major impact on the total consumption. However, the gate-count and toggle-rate estimates may serve as a reference quantity. Benchmarking is only meaningful when data from pre-existing designs exists. As such designs may not always be available (a block is not typically fully designed more than once in a specific application), comparison may be made using data from the design experience of similar functions. However, a value-judgment may be required in order to normalize the results to allow fair comparison. An important issue which cannot easily be measured, yet which is a major advantage of reconfigurable systems, is the ability of the design to be modified “on the fly” to meet movements in system specification. The can be due either to internal forces, such as work-arounds for design errors, or due to external influences such as the introduction of new variants of existing standards. In certain cases, a classic “hard-wired” design may occupy less chip resources than a reconfigurable equivalent, yet this will require a major re-design, including a complete new mask set to address any changes. With maskset costs in excess of 1M€, it is easy to justify an additional expenditure of 10 MY in favour of any reprogrammable structure. For this reason, the consideration of design flexibility per se will not be used as a benchmark. IMEC This section discusses the different implementations that are possible for the communication layer, it gives a motivation of our design choices and a comparison between the different solutions proposed by commercial companies, universities and research centres for implementing it. The data are compiled from published literature, no actual tests have been performed except for our own network. Table 3 shows a comparison between the different solutions proposed in literature or commercially available. Name Sonics[1] Proteo[2] SPIN [3] Aethereal [4] IMEC NoC [5][6]
Topology Bus Hierarchical Fat-Tree Bidirectional Arbitrary
Routing n/a Deterministic Adaptive Determ/Adap Deterministic
Switching n/a Wormhole Circuit-like SF, VCT, WS VCT
QoS Yes BE BE Yes OS
Interface OCP VCI VCI Prop Prop
Debug Yes No No No Yes
Table 3 Comparison between the different on-chip communication solutions. Topology From the point of view of the topology, the proposed solutions cover the whole spectrum from a IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 24 of 77
simple bus, hierarchy of buses, fixed topology networks, hierarchical networks and arbitrary topologies. The bus family is particularly numerous: AMBA, CoreConnect, CoreFrame, HIBI, Lotterybus, Marble, VCI, PI bus, Wishbone, SiliconBackplane. Some of these are commercial solutions already integrated in different products some are university proposals. The first two were developed to connect Instruction Set Processors to the rest of the system and although they were initially implemented on a PCB and connecting discrete components they can be found now also in SoCs like Virtex2Pro and Excalibur. However they suffer from the same limitations as all the other buses (i.e. inherently non-scalable, unstructured and highly asymmetric solution that makes intellectual property blocks (referred to hereafter as IP) reuse difficult and offers only a limited increase in bandwidth) and do not offer any support for QoS services. Sonics µNetwork was designed from the beginning with a dual scope: to offer both on-chip and on PCB connectivity. The IP cores communicate with each other over SiliconBackplane™ µNetwork bus. SiliconBackplane™ µNetwork is a fully pipelined, fixed latency bus using a Time Division Multiple Access (TDMA) bandwidth allocation scheme. The second category of solutions is network on chip. Almost all networks proposed until now are packet-switched networks, in the effort of optimising the bandwidth usage. Also all these solutions are still in research and, to our knowledge, there is no commercial solution using packet-switched networks. Proteo network is implemented as a library containing router and links components, which allows different topologies to be built. Examples of possible topologies are trees, meshes and hierarchical topologies, combining a bi-directional main ring with bus, ring and star sub-networks. IPs can be directly connected to the main ring or can be grouped in sub-networks that connect to the main ring. SPIN has a fat-tree topology. The advantage is that the network is non-blocking as long as there is no conflict in the destination. The disadvantage is the large area taken by the network. Another issue related to the implementation of SPIN is that its basic router has 8 inputs and 8 outputs implying that networks with the total number of nodes not a multiple of 4 will not be implemented very efficiently. Aethereal will also support a large spectrum of topologies. What it is already defined is the router, which can have a variable number of inputs and outputs. The only topology restriction is that every link should be reversible, therefore bi-directional. The IMEC network is built using a very flexible router that allows not only variable number of inputs and outputs but by decoupling the input block from the output one it can have a different number of inputs and outputs. With such a design we can easily build and explore virtually any kind of topology, in order to choose the one that is best suited for a certain application. Our router is built in such a way that all the ports are identical no matter if they connect to another router or to an IP. All the extra functionality required by the communication with the IPs has been implemented in the interfaces. This allows us to connect multiple IPs to the same router and to group IPs in star sub-networks. Subnetworks can be used to exploit traffic locality by connecting together IPs that frequently exchange information. Another advantage is that it makes better use the available link bandwidth with respect to required hardware, when grouping together IPs that require less bandwidth than it is offered by one link. Routing algorithm A second issue closely related to the topology is the routing algorithm. For buses no routing is needed, the information is broadcasted over the whole bus and reaches every IP that is connected to it. The IP checks if the address present on the bus is his and if not it ignores the packet. SiliconBackPlane uses a separate address and data bus to reduce latency. In packet-switched networks, the destination address is always placed in the header of the packet. Each router will then decide to which output port it should direct the packet based on this address. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 25 of 77
There are two major classes of routing algorithms: deterministic and adaptive. Deterministic algorithms will route the packets always on the same route irrespective of the route loading. Adaptive algorithms will try to choose alternative routes if the shortest route is blocked. Adaptivity comes at the cost of higher hardware requirements, and its advantages are relative. It increases the saturation limit in the network, but this increase has to be compared to the area cost. Another issue with adaptive algorithms is packet ordering. Extra hardware is needed to make sure that the packets are read at destination in the same order as they were sent. Aethereal will support both adaptive and deterministic routing algorithms, SPIN uses adaptive routing algorithms, Proteo and IMEC networks deterministic. Both, Proteo and the IMEC networks implemented the routing algorithm using look-up tables. In the IMEC network, the content of the table can be changed by an operating system (OS), dynamically, at run time. This is a higher level form of adaptivity, that can work well in networks with a known traffic pattern. The different IPs can be characterized in terms of the required data rate, and knowing the senders and the receivers for each IP, the routing tables can be modified to balance the network traffic. Each time a task that produces a change in the communication between the IPs is started, a new optimum can be computed and the tables changed accordingly. The update of the routing tables cannot be made on a per clock cycle basis, and this type of adaptivity does not offer all the power of a hardware implemented adaptive algorithm. However, for systems with a relatively small number of IPs and a well-known communication pattern, this type of flexibility will be adequate for many situations, at much lower hardware requirements than true adaptive routing algorithms. Switching technique The switching technique refers to the way packets are forwarded by the routers after they are received and what happens in the case the packet is blocked. Wormhole Switching (WS) and Virtual Cut Through (VCT) forward the packets immediately, before the entire packet is received. Store and Forward (SF) waits until the entire packet is received then it forwards it to the next router. VCT and SF buffer the entire packet if it is blocked while WS buffers only a few flits and signals to previous routers to stop sending. The advantage of VCT and WS is that packets have a very low latency compared to SF. VCT and SF allow a higher network utilization than WS, but at the cost of more hardware resources. We chose for VCT because in systems where the size of the payload is relatively large a wormhole switching network would saturate much faster than the virtual cut-through one. The disadvantage is that it requires large buffer sizes. Quality of Service QoS means that the application receives certain guarantees in terms of how fast can it transmit data, how long does it take to reach destination and what will be the maximum time difference between two consecutive packets reach destination. These parameters translate to requirements in terms of guaranteed bandwidth, maximum latency and jitter. From the solutions considered here only SiliconBackplane and Aethereal make provisions for offering QoS services. Both implement them using Time Division Multiple Access and putting in place a mechanism through which the applications can reserve slots and therefore bandwidth. In these way virtual channels guaranteeing a certain throughput, latency and jitter can be closed between IPs. Virtual circuits tend to decrease bandwidth utilization, moreover not all traffic requires QoS. Therefore both SiliconBackplane and Aethereal provide also best effort services. SPIN, Proteo provide only a best effort service. In the IMEC network QoS services can be provided at a higher level through the functionality already implemented in the interfaces. The usage of communication resources on the data network is monitored by the interface of each IP. Figures such as number of messages coming in and out of a specific IP are gathered in real time and made available to the OS. Another important figure available IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 26 of 77
is the average number of messages that have been blocked due to lack of buffer space in the interface. These figures allow the OS to keep track of the communication usage on the network. The maximum amount of messages an IP is allowed to send on the network per unit of time can be controlled by the OS. The injection rate controller adds an extra constraint on the time period when the messages may be injected in the network. This simple system introduces a guarantee on average bandwidth usage in the NoC and allows the OS to manage QoS on the platform. Interfaces The IPs connect to the communication infrastructure through interfaces. SiliconBackplane uses interface that implement Open Core Protocol, an extended version of the Virtual Component Interface standard. Proteo and SPIN networks implement the VCI standard while Aethereal and the IMEC interfaces have their own design. The role of the interface is to translate the data as presented by the applications to a format that is accepted by the communication layer. They also take care of the addressing, by placing the physical address of the destination in the packet header or on the address bus. Besides these general services that are implemented by all the solutions under discussion there are also other present only in some of them. Testing and debugging facilities are offered only by SiliconBackplane and the IMEC network. In the Sonics case all the IP core communication passes through the SiliconBackplane µNetwork, making all data and control traffic observable and controllable. In our case the interfaces are all connected through a control bus that allows data monitoring, debugging, control of the IP block, exception handling. The interfaces perform also sanity checks on the messages circulating on the network and notify the OS when problems occur. We check whether the message length is smaller than the maximum transfer unit and that messages are delivered in order. Like in the case of the SiliconBackplane µNetwork all IPs can be addressed in a uniform manner. The interfaces realize a translation from the system wide task ID to the physical address of the computing resource in the network. Performance and implementation Performance in terms of absolute numbers is difficult to assess. Although data have been published for almost all the systems under consideration they are impossible to compare because they resulted from very different implementations. We will try to show however what is the impact of the different design decisions on performance. a)
Bandwidth For SiliconBackplane µNetwork the bandwidth is reported to be between 50-4000 MB/s depending on choices of the different parameters. These numbers show what is the fundamental limitation of the bus-based systems. No matter how many IPs are connected to it the maximum bandwidth is fixed. In the case of the networks the bandwidth scales as the number of nodes increases, though the exact amount is depending on the topology. Certain topologies have a higher degree of interconnectivity than others and therefore can have more bandwidth per node. Our design allows to build a network with the most appropriate topology for a given system and to dimension the width of the interconnection links in order to achieve the desired bandwidth per node.
b)
Area With respect to the area taken by the different implementations the comparison is even more
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 27 of 77
difficult than for the bandwidth. Sometimes only data for one router are available, sometimes for a whole network, some authors have published data for the router and the interfaces, some only for router. The targeted technology also differs each time. Moreover there are differences in topologies, bandwidth and offered services, which make the comparison practically impossible. Nevertheless, some general remarks can be made. Networks using VCT switching require a large amount of buffer space that will consume a considerable area. This has to be weighted against the advantages of VCT. For Proteo it is reported that the buffers account for 81% of the total silicon area. In our the network was implemented for Virtex2Pro devices and it is estimated that the buffers account for over 90% of the total number of gates. However, this is due to the particular architecture of Virtex2Pro devices that force us to use buffers of a fixed given size, much larger than it would be required by the most area efficient implementation. Area will depend also on the topology of the network. Multi-dimensional topologies have a large number of connections and therefore require routers with a large number of ports. All routers contain a switching element that it is known to scale as O(N2), where N is the number of ports. Besides the switching element there can be also other modules that scale according to the same law, arbiters for instance. It is therefore expected that routers scale over linear with N, and that network with multidimensional topologies will take more area than 2D networks like meshes or toruses. On the other hand multi-dimensional networks offer also more bandwidth per node than their 2D counterparts. Buses are known to take less resource than networks. However, SiliconBackplane µNetwork requires a pair of interfaces for each IP connected to the bus and although concrete figures are missing judging by the services offered it has the same degree of complexity as a network’s router offering best-effort and guaranteed services. c)
Power Concrete power numbers are missing in the literature. It is expected however that driving long lines like in the case of buses will result in large power consumption. SiliconBackplane µNetwork is the only solution among the presented ones that uses long wires that possibly span the whole chip and connect to multiple IPs. In the case of the networks, the routers connect through much shorter wires and realize only point-to-point connections. Power and area are expected to go down in this case because the wires are shorter and need smaller drivers. All presented solutions allow decoupling the clock of the routers and interfaces from the clock of the IPs. In this way the IPs can be clocked for optimum power consumption while the communication layers takes care of the message flow control.
INTRACOM INTRACOM is going to evaluate the complete AMDREL Reconfigurable System-on-Chip platform through the realization of a wireless communication system. A suitable instance of the AMDREL platform will be selected for the realization of the targeted system. The instance will include all the reconfigurable building blocks i.e. reconfigurable interconnect, coarse grain blocks and fine grain block alongside necessary application specific blocks that will be developed in the context of AMDREL. The AMDREL methodology will be used to partition and map the targeted functionality on the AMDREL platform instance. The realization of the selected application on the AMDREL platform will be compared to realization of the same functionality on a platform including discrete reconfigurable components (FPGAs). The comparison will be performed in terms of development effort, realization cost and market suitability (as far as INTRACOM is concerned). References [1] http://www.sonicsinc.com/sonics/products/siliconbackplane/ IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 28 of 77
[2] I. Saastamoinen, D. Siguenza-Tortosa, J. Nurmi, An IP-Based On-Chip Packet-Switched Network, Kluwer Academic Publishers, Dordrecht, Netherlands, p193-213 , 2003 [3] Pierre Guerrier and Alain Grenier, A generic architecture for on-chip packet switched interconnections, In Proceedings of DATE 2000 [4] E. Rijpkema et al.: Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for Networks On Chip, in Proceedings of DATE 2003, pages 350-355, Munich, March 2003 [5] T.A. Bartic, J-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, R. Lauwereins, Highly Scalable Network on Chip for Reconfigurable Systems, submitted to SOC 2003. [6] T. Marescaux, J.-Y. Mignolet, A. Bartic, W. Moffat, D. Verkest, R. Lauwereins: Networks on Chip as Hardware Components of an OS for Reconfigurable Systems, Proc. 13th Int. Conf. on FieldProgrammable Logic and Applications, Lisabon, September 2003 (accepted)
10.3.
Overview of expected results
This section distinguishes results, which are for general dissemination (public results), which are for the benefit of the research community at large, and the specific results (of a confidential nature) which form the core know-how developed by the project, and which is the basis for the exploitation of the results by the various partners
10.3.1. Results to be disseminated The following list summarises the project’s deliverables which will be publicly disseminated. These deliverables are therefore, by definition, public reports or demonstrators, which do not require specific permission, non-disclosure or other confidentiality agreements to be established prior to their being made public (The baseline reference M1 is March 2002). D1: Behavioral optimization opportunities for wireless LAN systems, Date M6, Report. D2: Behavioral optimization requirements of reconfigurable platforms, Date M6, Report. D3: Requirements for interconnection networks in a dynamically reconfigurable context, Date M6, Report. D5: Refined mixed granularity dynamically reconfigurable target architecture template, Date M9, Report. D7: Existing functional level reconfigurable implementation platforms, Date M9, Report. D8: Critical functions from the target application domain suitable for implementation as reconfigurable blocks, Date M9, Report. D9: Survey of existing fine-grain reconfigurable hardware platforms, Date M9, Report. D16: Quality Assurance Plan, Date M18, Report. D18: Behavioral optimization methodology for wireless LAN systems realized on reconfigurable platforms, Date M24, Report. D19: Strategy for functionality partitioning between mixed granularity reconfigurable hardware blocks, Date M24, Report. D25: Systematic methodology for implementation on the functional reconfigurable hardware blocks, Date M24, Report. D36: Demonstrator based on processor for critical parts of the baseband function of wireless LAN system, Date M36, Demonstrator. D37: Demonstrator based on multimedia application processor for wireless terminals, Date M36, Report. D38: Evaluation of AMDREL approach, Date M36, Report. D40: Technology Implementation Plan (TIP), Date M36, Report
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 29 of 77
10.3.2. Results to be used The following deliverables form the core knowledge generated by the AMDREL project. They embody the intellectual property of the various project partners, and are thus confidential. Information contained in these results may only be made available to external parties (i.e. parties who are not partners in the project) under the terms of the mutually agreed Project Cooperation Agreement. The table in section 12.1 summarises these results, and identifies the IPR owner. The following list reiterates these items, giving an indication of their expected availability (The baseline reference M1 is March 2002). i) D11: Network building blocks, Date M12, Prototype and Report. ii) D14:Power efficient configurable logic block, Date M18, Prototype and Report. iii) D15:Interconnect network simulation model and interconnect network instance generator, Date M18, Prototype and Report. iv) Combination of D18 (Behavioral optimization methodology for wireless LAN systems realized on reconfigurable platforms) and D21 (Prototype source-to-source behavioral optimiser): Behavioural optimisation methodology and tool, Date M28, Prototype and Report. v) D23: Optimized reusable soft intellectual properties for critical tasks of the target application domain, Date M28, Prototype and Report. vi) D25: Systematic methodology for implementation on the functional reconfigurable hardware blocks, Date M24, Report. vii) Combination of D26 (Structure and organization of fine grain reconfigurable hardware), D27 (Fine grain reconfigurable hardware generator), D28 (Tool for technology mapping), D29 (Placement and routing tools) and D30 (Configuration bitstream generator): Fine grain reconfigurable block and supporting tools, Date M24, Prototype and Report.
10.3.3. Approach to Dissemination Dissemination of the results through publications in workshops, seminars, conferences and magazines by all partners. Construction of a project web site, containing an overview of the project and to make available all public reports, and, journal and conference publications. Dissemination of the survey of fine-grain reconfigurable hardware, AMDREL methodology, design flows, and prototype tools through DUTH’s M.Sc. and Ph.D. programme. Seminars are organized by DUTH regularly every six months for the local university community (professors, undergraduate and graduate students), where members of VLSI Design and Testing Centre present their research results about the running projects. Finally, INTRACOM is considering Athens Information Technology (AIT) educational institute as another possible route for dissemination.
10.3.4. Approach to use The following picture presents the overall use strategy for AMDREL’s results. In the next sections there is a more detailed description of each result.
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 30 of 77
!
"#
%$*+
&'()
,
-
.(.
/
Figure 9: Overall use plan for AMDREL project Use plan shall for the most part be through internalisation of the recommendations and associated methodology by the partners in their own product design flows. The commercial added value will appear as improved product development performance and market leadership in the chosen application field, which is a vital consideration for companies active in very fast-moving markets such as wireless networks. The academic partner and the research institute will largely exploit the project results through their inclusion into their portfolio of solutions. These are offered to their strategic partners via several contractual ways. This allows them to strengthen further their recognition as centers of excellence.
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 31 of 77
11. PART 2: DESCRIPTION OF DISSEMINATION ACTIVITIES 11.1.
Conferences
INTRACOM and DUTH INTRACOM with DUTH worked very closely in the preparation and submission of the following papers to be presented in conferences. In D12 (previous DUP) report, it was mentioned that ICOM/ DUTH submitted and planned one and nine conference papers respectively for the second year of AMDREL. The current situation is as follows: Accepted Papers From the eight planned papers of D33, we submitted six papers, where four of them are accepted for publication and presentation and two papers are still under review. Two remaining two “planned papers” were not prepared for submission due to the re-organization of the publishing schedule of DUTH research team. These two papers will be submitted as journals papers. 1)
K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris, and A. Thanailakis, “A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development,” accepted for presentation in in Proceedings of 13th International Conference on Field Programmable Logic and Applications (FPL) August 30-September 1, 2004, Antwerp, Belgium, pp. 1116-1118.
2)
K. Masselos, S. Blionas, J-Y. Mignolet, A. Foster, D. Soudris and S. Nikolaidis, "Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform, in Proc. of 14th International Workshop, Power and Timing Modeling, Optimization and Simulation (PATMOS), Santorini, Greece, September 15-17, 2004, pp. 613-622.
3)
D. Atienza, S. Mamagkakis, M. Leeman, F. Catthoor, J. M. Mendias and D. Soudris, “Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems,” in Proc. of 14th International Workshop, Power and Timing Modeling, Optimization and Simulation (PATMOS), Santorini, Greece, September 15-17, 2004, pp. 510 - 520.
4)
M.D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris, and C.E. Goutis, "Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path,” accepted for presentation in in Proceedings of 13th International Conference on Field Programmable Logic and Applications (FPL) August 30-September 1, 2004, Antwerp, Belgium, pp.868-873.
Submitted Papers 1) G. Koutroumpezis, K. Tatas, D. J. Soudris and A. Thanailakis “A Reconfigurable FIR Filter Architecture For Data-Intensive Applications,” submitted for review in ISCAS 2005. 2)
A. Bartzas, G. Pouiklis, S. Mamagkakis, D.Soudris, F. Catthoor, and A. Thanailakis, “Performance-Energy Trade-offs Exploration inDynamic Data Types for Network Applications, submitted for review in WWIC 2005
From the list of submitted papers of D33 DUP report: Rejected Papers 1) S. Mamagkakis, D. Atienza, F. Catthoor, J. Mendias, and D. Soudris, “Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications” submitted in Conference: DAC 2004, USA. There are ten additional accepted conference publications, which were not included in the “planned IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 32 of 77
publications” of D33. These publications are: 1)
D. Atienza, S. Mamagkakis, M. Leeman, F. Catthoor, J. M. Mendias and D. Soudris, “PowerAware Tuning of Dynamic Memory Management for Embedded Real-Time Multimedia Applications accepted for presentation in DCIS2004, Bordeaux, 24-26 November 2004.
2)
S. Mamagkakis, D. Atienza, C. Poucet, F. Catthoor, D. Soudris, and J. M. Mendias, “Custom Design of Multi-Level Dynamic Memory Management Subsystem for Embedded Systems,” in Proc. of IEEE Workshop on Signal Processing Systems (SIPS’04) October 13-15, 2004, Austin, Texas, USA, pp. 170-175.
3)
D. Atienza, S. Mamagkakis, F. Catthoor, J.M. Mendias, D. Soudris, "Reducing Memory Accesses with a System-Level Design Methodology in Customized Dynamic Memory Management,” ESTIMedia 2004, 2nd Workshop on Embedded Systems for Real-Time Multimedia, September 6-7th, 2004, Stockholm, Sweden.
4)
M.D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris, and C.E. Goutis, “A Novel Data-Path for Accelerating DSP Kernels,” in Proc. of Workshop SAMOS IV: Systems, Architectures, MOdeling, and Simulation, Samos, Greece, July 19-21, 2004, pp. 363-372.
5)
M.D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris and C.E. Goutis, “Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path,” in Proc. of 14th International Workshop, Power and Timing Modeling, Optimization and Simulation (PATMOS), Santorini, Greece, September 15-17, 2004, pp. 652-661.
6)
I. Pappas, N. Vassiliadis, V. Kalenteridis, H. Pournara, S. Nikolaidis, S.Siskos, K. Siozios, G. Koutroumpezis, K. Tatas, D. J. Soudris, A. Thanailakis, «Fine-Grain Reconfigurable Platform: FPGA Hardware Design and Software Toolset Development,” accepted in Microelectronics Microsystems and Nanotechnology, between 14 and 17 November 2004, Greece.
7)
M.D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris and C.E. Goutis, “A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms,” accepted for presentation in DATE ’05 Designers Forum, Messe, Mnuich, Germany.
8)
M.D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris, And C.E. Goutis A High Performance Data-Path to Accelerate DSP Kernels,” accepted for presentation in 11th Int. Conf. on Electronics, Circuits and Systems, ICECS ’04, 13-15 December 2004, Tel-Aviv, Israel.
9)
D. Soudris, S. Nikolaidis, S. Siskos, K. Tatas, K. Siozios, G. Koutroumpezis, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, and A. Thanailakis, “AMDREL: A NOVEL LOWENERGY FPGA ARCHITECTURE AND SUPPORTING CAD TOOL DESIGN FLOW,” accepted for presentation in Design Contest of ASP-DAC 2005, Asia South Pacific – Design Automation Conference, January 18-21, 2005, Shanghai, China.
10) S. Mamagkakis, C. Mpaloukas, D. Atienza, F. Catthoor, D. Soudris J. M. Mendias, and A. Thanailakis “Reducing Memory Fragmentation with Performance-optimized Dynamic Memory Allocators in Network Applications, accepted for presentation in 3rd Int. Conference on Wired/Wireless Internet Communications (WWIC) May 11-13, 2005, Xanthi, Greece. 11) K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris and A. Thanailakis “DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and its Software Tool Implementation,” accepted for presentation in Reconfigurable Architectures Workshop, RAW 2005, April 4-5, 2005, Denver, Colorado, USA.
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 33 of 77
Rejected 1) K. Siozios, G. Koutroumpezis, K. Tatas, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, D. Soudris, A. Thanailakis, S. Nikolaidis, and S. Siskos, “An Open Source-based CAD Framework for Implementing Applications onto FPGA Platform,” submitted for review in RAW 2005 There are two additional submitted conference publications, which were not included in the “planned publications”. These submitted papers are: 1) 2)
S. Mamagkakis, D. Atienza, F. Catthoor, D. Soudris and J. M. Mendias, “Automated Exploration of Pareto-optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems submitted for review in DAC 2005. S. Mamagkakis, D. Atienza, F. Catthoor, D. Soudris and J. M. Mendias, “IMEC-Universities Network for System Level Design of Emebedded Systems: Dymanic Memory Allocation,” submitted in 2005 IEEE International Systems Education, June 12-13, Anaheim, USA.
Here, we provide some quantitative information we extracted from the organizing committees of the aforementioned conference events:
N/A 0 29 0
Acceptance/Rejection ratio N/A 18% 53.3% 62.6%
15
0
46%
168 99 full paper, 86 short papess 144 34 40
N/A
79%
95
40%
N/A 0 0
N/A 34.4% 41%
DATE 2005 PATMOS 2004 FPL 2004 SIPS 2004 ESTIMEDIA 2004 ICECS 2004
825 85 285 107
Accepted Papers NA 45 123 67
32 212
ASP-DAC 2005
692
DCIS 2004 WWIC 2005 RAW 2005
N/A 117 97
Conference
Submitted Papers
Posters
Awards 1. 4th Position of the paper entitled «AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow» in the Design Contest ASP-DAC 2005, Shanghai, China, January 18-21, 2005. 2. «Honorable mention for design contest entry» of «AMDREL: A novel low-energy FPGA architecture and supporting CAD tool design flow» in the Design Contest of 18th International Conference on VLSI Design, Kolkata, India, January 3-7, 2005. IMEC Accepted papers 1) J-Y. Mignolet, V. Nollet, P. Coene, D.Verkest, S. Vernalde, R. Lauwereins, “Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-onChip”, Proceedings of the DATE'03 conference, pages , Munich, March 2003 2) V. Nollet, P. Coene, D.Verkest, S. Vernalde, R. Lauwereins, “Designing an Operating System IST-2001-34379/WP7/D39/ICOM/R AMDREL Consortium
Deliverable D39
Page 34 of 77
for a Heterogeneous Reconfigurable SoC”, Proceedings of the RAW'03 workshop, Nice, April 2003. 3)
V. Nollet, J-Y. Mignolet, T. A. Bartic, D. Verkest, S. Vernalde, R. Lauwereins, ““Hierarchical Run-Time Reconfiguration Managed by a Operating System for Reconfigurable Systems”, Proceedings of the International Conference on Engineering Reconfigurable Systems and Algorithms 2003, pages 81-87, Las Vegas, June 2003.
4)
T. Marescaux, J-Y. Mignolet, A. Bartic, W. Moffat, D. Verkest, S. Vernalde, R. Lauwereins, “Networks on Chip as Hardware Components of an OS for Reconfigurable Systems”, Intl. Conf. on Field Programmable Logic and Applications (FPL), pages 595-605, Lisbon, Portugal, September 2003.
5)
T. A. Bartic, J-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, R. Lauwereins, “Highly Scalable Network on Chip for Reconfigurable Systems Systems”, Proceedings of the International Conference on System-On-Chip 2003, Tampere, November 2003.
6)
V. Nollet, T. Marescaux, D. Verkest, J.-Y. Mignolet, S. Vernalde, “Operating System controlled Network-on-Chip”, Proc. Of DAC 2004, pp. 256-259, San Diego, June 2004
7)
V. Nollet, T. Marescaux, P. Avasare, D. Verkest, J.-Y. Mignolet, “Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles”, accepted at DATE 2005, Munich, March 2005.
Here, we provide some quantitative information from the aforementioned conference events: Conference DATE 2003 RAW 2003 FPL 2003 SOC 2003
Submitted Papers 489 75 218 52
Accepted Papers 155 23 90 16
Posters 47 22 56 17
Submitted papers 1) P. Avasare, V. Nollet, D. Verkest, J.-Y. Mignolet, “Centralized Run-Time Traffic Management in a Network-on-Chip”, rejected at DATE 2005, improved and resubmitted to DAC 2005.
11.2.
Publications
INTRACOM/DUTH In D12 report, it was mentioned that ICOM/DUTH planned six journals papers for submitting for the second year of AMDREL. The current situation is as follows: from the planned papers, we submitted five papers while the sixth planned for the third year of project. In addition, we plan journals for the third year of project. Accepted Journals 1)
D. Atienza, S. Mamagkakis, F. Poletti, J.M. Mendias, F. Catthoor, L. Benini and D. Soudris, “Efficient System-Level Prototyping of Power-Aware Dynamic Memory Managers for Embedded Systems” accepted in “Integration, The VLSI Journal”.
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 35 of 77
2)
V. Kalenteridis, H. Pournara, K. Siozos, K. Tatas, I. Pappas, S. Nikolaidis, S.Siskos, D. J. Soudris and A. Thanailakis “A Complete Platform and Toolset for System Implementation on Fine-Grain Reconfigurable Hardware” accepted in Microprocessors and Microsystems, Special Issue on Field-Programmable Gate Arrays (FPGAs): Applications, Algorithms and Tools, Elsevier Publishers.
3)
K. Tatas, G. Koutroumpezis, D. Soudris and A. Thanailakis, “Architecture Design of a CoarseGrain Reconfigurable Multiply-accumulate unit for Data Intensive Applications” accepted in “Integration, The VLSI Journal.
Submitted Journals 1) D. Atienza, S. Mamagkakis, F. Catthoorz,, J. M. Mendias, and D. Soudris, “Systematic Dynamic Memory Management Design Methodology for Reduced Memory Footprint.” in ACM Transactions on Design Automation of Electronic Systems. From the five planned journal papers from the last DUP, three of them were submitted (following list) and one was postponed and one was cancelled: 1)
K. Siozios, G. Koutroumpezis, K. Tatas, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas,D. Soudris, S. Nikolaidis and S. Siskos, “A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications,’ Special Section on “Recent Advances in Circuits and Systems” IEICE Trans. Information and Systems.
2)
D. Soudris, S. Nikolaidis, S. Siskos, K. Tatas, K. Siozios, G. Koutroumpezis, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, and A. Thanailakis, “A Novel Low-Energy FPGA Reconfigurable Architecture and an Integrated Framework of CAD Tools for Implementing Applications,” submitted in IEEE Trans. On VLSI Systems.
3)
M.D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris and C.E. Goutis, “A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms,” submitted in IEEE Trans on CAD.
Rejected Journal 1) D. Atienza, S. Mamagkakis, M. Leeman, F. Catthoor, J.M. Mendias, D. Soudris, “Power-Aware Tuning of Dynamic Memory Subsystem in Embedded Real-Time Multimedia Applications” submitted in IEEE DESIGN. & TEST - Special Issue On Embedded Systems For Real-Time Multimedia. IMEC 1) Title: “Enabling Run-time Task Relocation on Reconfigurable Systems” Authors: J.-Y. Mignolet, V. Nollet, P. Coene, D. Verkest, S. Vernalde, R. Lauwereins Journal: Chapter in “New Algorithms, Architectures and Applications for Reconfigurable Computing”, Kluwer Academic Publishers Status: accepted 2)
Title: “Run-Time Support for Heterogeneous Multitasking on Reconfigurable SoCs” Authors: T. Marescaux, V. Nollet, J.-Y. Mignolet, A. Bartic, W. Moffat, P. Avasare, P. Coene, D. Verkest, S. Vernalde, R. Lauwereins Journal: the VLSI Journal (Elsevier Science) Status: accepted
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39 3)
Page 36 of 77
Title: “Topology Adaptive Network-on-Chip Design and Implementation” Authors: A. Bartic, J.-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, R. Lauwereins Journal: IEE Proc. Computers and Digital Techniques Status: accepted
11.3.
Web presence
AMDREL website http://vlsi.ee.duth.gr/amdrel was updated regularly with the public and restricted material. More specifically, published conference and journal papers, public and restricted deliverable reports were stored in AMDREL web server. In addition, the graphical user interface (GUI) for designing fine-grain reconfigurable processors, which include new and existing software tools for mapping applications onto the full-custom designed fine-grain reconfigurable platform, is accessible from the external users to build their own fine-grain designs., through the AMDREL website. The potential users can also access each tool manual and can ask DUTH’s personnel for support in specific issues/problems, during their project implementation. The next figure shows the homepage of AMDREL project.
Figure 10: AMDREL’s web site
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 37 of 77
We compiled all the available information in Table 10 and 11 regarding the traffic of AMDREL website the last two years 2003 and 2004. Table 4 Stats for 2003 and 2004 about AMDREL website traffic Stats for 2003 and 2004 about AMDREL website traffic Tthe most downloaded report/publication 893 /amdrel/pdf/d9_final.pdf The most downloaded report
893
/amdrel/pdf/d9_final.pdf
The most downloaded publication
680
/amdrel/papers/FPL2002.pdf
Table 5 . Stats for 2003 and 2004 about AMDREL website traffic (#hits)
#hits for publications
1553
#hits for reports
1290
#hits others
2905
#hits total
5748
#hits for publications
5011
#hits for reports
2118
#hits others
4489
#hits total /amdrel/Democritus_FPGA_Tools/
11618 28
Table 6 : #hits of the first ten publications 2003 /amdrel/papers/FPL2002.pdf /amdrel/papers/24510229_patmos_2002.pdf /amdrel/papers/patmos_2003_amdrel.pdf /amdrel/papers/Designing_Reconf_Embedded_Structures.pdf /amdrel/papers/fpl2003.pdf /amdrel/papers/patmos2003_2.pdf /amdrel/papers/date03.pdf /amdrel/papers/fpl2003_imec.pdf /amdrel/papers/raw2003.pdf /amdrel/papers/fpga2004.pdf
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 38 of 77
Table 7 : #hits of the first ten reports 2003 /amdrel/pdf/d9_final.pdf /amdrel/pdf/d2_final.pdf /amdrel/pdf/d8_final.pdf /amdrel/pdf/d1_final.pdf /amdrel/pdf/d7_final.pdf /amdrel/pdf/d12_final.pdf /amdrel/pdf/d5_final.pdf /amdrel/pdf/d3_final.pdf /amdrel/deliverable/d11_final.pdf /amdrel/deliverable/d10_final.pdf
Table 8 : #hits of the first ten publications 2004 /amdrel/papers/HighlyScalableNoC_SOC2003.pdf /amdrel/papers/Designing_Reconf_Embedded_Structures.pdf /amdrel/papers/fpga2004.pdf /amdrel/papers/wwic04.pdf /amdrel/papers/raw2003.pdf /amdrel/papers/fpl2003_imec.pdf /amdrel/papers/raw2004.pdf /amdrel/papers/melecon2004vasiliadis.pdf /amdrel/papers/patmos2004masselos.pdf /amdrel/papers/patmos2003_2.pdf
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 39 of 77 Table 9 : #hits of the first ten reports 2004 /amdrel/pdf/d9_final.pdf /amdrel/pdf/d33.pdf /amdrel/pdf/d8_final.pdf /amdrel/pdf/d7_final.pdf /amdrel/pdf/d1_final.pdf /amdrel/pdf/d12_final.pdf /amdrel/pdf/d2_final.pdf /amdrel/pdf/d3_final.pdf /amdrel/pdf/d16_final.pdf /amdrel/pdf/d19.pdf
Additional , important element from AMDREL website is the fact the deliverable report D33 (Design and Use Plan) of last year downloaded 231 times.
Below, we provide Table 10 and 11 with the statistics of AMDREL website for 2003 and 2004. This information concerns, among others, the number of hits of a specific link. The traffic quantification of each specific link is very useful to see which results/deliverable reports/journalconference publications have the largest influence to website users. Table 10: Statistics of AMDREL website for 2003
$ %
! "#
% & '
/amdrel/ /amdrel/pdf/d9_final.pdf /amdrel/papers/FPL2002.pdf /amdrel/documents_overview.html /amdrel/publications.html /amdrel/papers/24510229_patmos_2002.pdf /amdrel/papers/patmos_2003_amdrel.pdf /amdrel/papers/Designing_Reconf_Embedded_ Structures.pdf /amdrel/deliverables.html /amdrel/partners.html /amdrel/calendar.html
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 40 of 77
/amdrel/Welcome.html /amdrel/papers/fpl2003.pdf /amdrel/pdf/d2_final.pdf /amdrel/login.php /amdrel/pdf/d8_final.pdf /amdrel/pdf/d1_final.pdf /amdrel/pdf/d7_final.pdf /amdrel/pdf/d12_final.pdf /amdrel/papers/patmos2003_2.pdf /amdrel/pdf/d5_final.pdf /amdrel/objectives.html /amdrel/downloads.html /amdrel/tech_approach.html /amdrel/pdf/d3_final.pdf /amdrel/goals.html /amdrel/papers/date03.pdf /amdrel/links.html /amdrel/news.html /amdrel/contact.html /amdrel/pdf/ /amdrel/test/login.php /amdrel/deliverable/ /amdrel/disclaimer.html /amdrel/papers/fpl2003_imec.pdf /amdrel/test.htm /amdrel/test/ok.php /amdrel/papers/raw2003.pdf /amdrel/papers/fpga2004.pdf /amdrel/deliverable/list.html /amdrel/papers/ersa2003.pdf /amdrel/deliverable/d11_final.pdf /amdrel/ok.php /amdrel/papers/ /amdrel/ksiop.php /amdrel/deliverable/d10_final.pdf /amdrel/deliverable/d6_final.pdf /amdrel/images/logo/mail-small.zip /amdrel/pdf/d16_final.pdf /amdrel/images/logo/print-large.zip /amdrel/papers/HighlyScalableNoC_SOC2003.p df /amdrel/images/logo/mail-large.zip /amdrel/login2.php /amdrel/pdf/_vti_cnf/ /amdrel/pdf/_vti_cnf/d12_final.pdf /amdrel/pdf/d16_final.PDF /amdrel/deliverable/d12_final.pdf /amdrel/deliverable/d1_final.pdf /amdrel/test/
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 41 of 77
/amdrel/deliverable/d15_final.pdf /amdrel/deliverable/minutes-4.pdf /amdrel/forward.php /amdrel/images/logo/print-small.zip /amdrel/deliverable/d7_final.pdf /amdrel/secure/ /amdrel/deliverable/d5_final.pdf /amdrel/deliverable/minutes-1.pdf /amdrel/test.php /amdrel/deliverable/d14_final.pdf /amdrel/pdf/_vti_cnf/d2_final.pdf /amdrel/pdf/_vti_cnf/d9_final.pdf /amdrel/deliverable/d9_final.pdf
Table 11: Statistics of AMDREL website for 2004
(
!
$ % #
% & '
/amdrel/ /amdrel/papers/24510229_patmos_2002.pdf /amdrel/publications.html /amdrel/papers/patmos_2003_amdrel.pdf /amdrel/documents_overview.html /amdrel/pdf/d9_final.pdf /amdrel/papers/fpl2003.pdf /amdrel/papers/date04.pdf /amdrel/papers/FPL2002.pdf /amdrel/papers/HighlyScalableNoC_SOC20 03.pdf /amdrel/deliverables.html /amdrel/papers/Designing_Reconf_Embedd ed_Structures.pdf /amdrel/papers/colp2003.pdf /amdrel/papers/fpga2004.pdf /amdrel/partners.html /amdrel/pdf/d33.pdf /amdrel/pdf/d8_final.pdf /amdrel/Welcome.html /amdrel/calendar.html /amdrel/papers/wwic04.pdf /amdrel/pdf/d5_final.pdf /amdrel/pdf/d7_final.pdf /amdrel/pdf/d1_final.pdf /amdrel/pdf/d12_final.pdf /amdrel/pdf/d2_final.pdf /amdrel/tech_approach.html
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 42 of 77
/amdrel/objectives.html /amdrel/papers/raw2003.pdf /amdrel/downloads.html /amdrel/pdf/d3_final.pdf /amdrel/papers/fpl2003_imec.pdf /amdrel/goals.html /amdrel/news.html /amdrel/papers/melecon2004vasiliadis.pdf /amdrel/papers/raw2004.pdf /amdrel/papers/patmos2004masselos.pdf /amdrel/papers/patmos2003_2.pdf /amdrel/pdf/d16_final.pdf /amdrel/papers/iscas2004.pdf /amdrel/papers/ersa2003.pdf /amdrel/links.html /amdrel/papers/date03.pdf /amdrel/papers/fpl2004siozios.pdf /amdrel/pdf/d19.pdf /amdrel/contact.html /amdrel/papers/melecon2004pournara.pdf /amdrel/papers/ /amdrel/papers/samos2004galanis.pdf /amdrel/disclaimer.html /amdrel/papers/fpl2004galanis.pdf /amdrel/papers/estimedia2004atienza.pdf /amdrel/papers/patmos2004atienza.pdf /amdrel/papers/sips2004.pdf /amdrel/pdf/ /amdrel/Democritus_FPGA_Tools/ /amdrel/papers/integration2004.pdf /amdrel/images/logo/mail-large.zip /amdrel/Democritus_FPGA_Tools/Democritu s_FPGA_Tools.htm /amdrel/deliverable/ /amdrel/papers/date2004.pdf /amdrel/deliverable/d30.pdf /amdrel/deliverable/d27.pdf /amdrel/deliverable/d20.pdf /amdrel/pdf/_vti_cnf/ /amdrel/publications1.html /amdrel/deliverable/d14_final.pdf /amdrel/deliverable/d32.pdf /amdrel/papers/_vti_cnf/ /amdrel/images/logo/print-large.zip /amdrel/images/logo/mail-medium.zip /amdrel/deliverable/d15_final.pdf /amdrel/images/logo/print-medium.zip /amdrel/deliverable/d28.pdf /amdrel/papers/dcis2004.pdf
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 43 of 77
/amdrel/deliverable/d24.pdf /amdrel/images/logo/print-small.zip /amdrel/deliverable/d25.pdf /amdrel/deliverable/d23.pdf /amdrel/deliverable/d26.pdf /amdrel/images/logo/mail-small.zip /amdrel/pdf/d16_final.PDF /amdrel/deliverable/d29.pdf /amdrel/papers/_vti_cnf/FPL2002.pdf /amdrel/deliverable/d22.pdf http://vlsi.ee.duth.gr/amdrel/disclaimer.html http://vlsi.ee.duth.gr/amdrel/calendar.html http://vlsi.ee.duth.gr/amdrel/goals.html /amdrel/deliverable/d16_final.pdf http://vlsi.ee.duth.gr/amdrel/objectives.html http://vlsi.ee.duth.gr/amdrel/Welcome.html /amdrel/deliverable/d31.pdf /amdrel/deliverable/d21.pdf http://vlsi.ee.duth.gr/amdrel/documents_over view.html http://vlsi.ee.duth.gr/amdrel/contact.html /amdrel/pdf/_vti_cnf/d1_final.pdf http://vlsi.ee.duth.gr/amdrel/tech_approach.h tml /amdrel/deliverable/d9_final.pdf /amdrel/papers/_vti_cnf/Designing_Reconf_ Embedded_Structures.pdf http://vlsi.ee.duth.gr/amdrel/partners.html http://vlsi.ee.duth.gr/amdrel/news.html http://vlsi.ee.duth.gr/amdrel/ /amdrel/papers/_vti_cnf/HighlyScalableNoC_ SOC2003.pdf http://vlsi.ee.duth.gr/amdrel/links.html /amdrel/deliverable/d18_final.pdf
!
11.4.
) *"
+, ( -*%
(, .(/ Created by awstats
Clustering and Standardization (inputs from partners)
AMDREL will share experience and results along with IST-2000-30049 ADRIATIC project.
11.5.
Other
DUTH presented results from WP2 in MARLOW network of excellence workshop (Sept. 14th 2004, Santorini, Greece) with two lectures. The attached program of MARLOW Workshop shows the titles IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 44 of 77
and the name of presenters. MARLOW Workshop Program: 08:00 - 09:00
Registration
09:00 - 09:30
Welcome
Vassilis Paliouras, U. of Patras
Introduction to MARLOW
Rene Van Leuken , DIMES
09:30 - 10:15
10:15 - 10:45
Dynamic Memory Embedded Systems
Management
in St.Mamagakis, Prof. D. Soudris, DUTH D.Atienza, IMEC, Dr. S. Blionas, Intracom, S.A.
Coffee Break
10:45 - 11:30
Low-power Cryptography
11:30 - 12:30
MARLOW Roadmap presentation and Johan Vounckx, IMEC Discussion
12:30 - 14:30 14:30 - 16:00 16:00 - 16:30 16:30 - 18:00
Prof. Odysseas Koufopaulou, Patras
U. of
Lunch Reconfigurable tutorial
System
Design:
A Prof. S. Siskos, AUTH and Prof. D. Soudris, Univ.. of Thrace
Coffee Break Computer Arithmetic Algorithms and Prof. Mark Arnold, Lehigh University Applications
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 45 of 77
12. PART 3: DESCRIPTION OF THE USE PLAN (BY RESULTS) 12.1.
Overview of Results
The following table lists the key results of the project and the owner of the rights to these. Each result has been allocated a reference number corresponding to their deliverable identifier as listed in the Description of Work. This shall be used to refer to each result in the following paragraphs. Result
Description
Owner
Participants
Network building blocks (associated with D11)
IP blocks
IMEC
ALL
Power efficient configurable (associated with D14)
IP block
DUTH
ALL
Interconnect network simulation model and interconnect network instance generator (associated with D15)
Tool
IMEC
ALL
Behavioural optimisation methodology and tool (associated with D18, D21)
Methodology and tool
INTRACOM, DUTH
ALL
Optimised reusable soft intellectual properties for critical tasks of the target application domain (associated with D23)
IP blocks
INTRACOM, DUTH
ALL
Systematic methodology for implementation on the functional reconfigurable hardware blocks (associated with D24 and D25)
Methodology
STMB
ALL
Fine grain reconfigurable block and supporting tools (associated with D26-D30)
IP block and tools
INTRACOM, DUTH
ALL
logic
block
All results of the project are relevant to the market sector of Computer Aided Design (CAD) for design of integrated circuits and systems. The results will thus be of most interest to companies involved in electronic system development and CAD tools development as well as to silicon manufacturing.
12.2.
Detailed description of result D11
12.2.1. Description of result D11 This result is an IP library of VHDL building blocks that can be used to build interconnect networks with different topologies on reconfigurable architectures. Such networks enable the dynamic creation and deletion of tasks on the reconfigurable hardware through their unified application interface. They form the basic components to explore and implement different interconnect networks depending on the requirements of the applications 12.2.2. Market size of result D11 IMEC’s business strategy is based upon their Intellectual Property (IP) Portfolio. The abovementioned result will be an extension of this ‘IP Portfolio’ and will be exploited via several ways: IMEC’s Industrial Affiliation Programs (IIAP) (e.g. IIAP on Reconfigurable Systems); Bilateral contracts with the national and international industry and universities; Technology transfers and licensing to industry or spin-off companies. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 46 of 77
The targeted customers of this result are fine-grain reconfigurable hardware (FPGA) semiconductor companies, coarse-grain reconfigurable hardware semiconductor and fabless companies, system design houses and micro-electronics companies with an interest in using reconfigurable hardware for optimal implementation of dynamic hardware applications. The extension of the ‘IP Portfolio’ will also be used as ‘Pre-existing knowledge’ for future research and development projects and PhD topics. Because the primary business model for IMEC is the IIAP model, this will now be explained in more detail. Introduction IMEC's Industrial Affiliation Program is IMEC's premium R&D cooperation formula for joint R&D between industrial researchers and IMEC research teams focused on a specific topic or technology area. The concept is recognized worldwide as one of the most successful international partnership models for joint development of next-generation technologies. Each industrial partner joins the IIAP research program on a bilateral basis, with clearly defined technical scope and deliverables, allowing the partner to tune the bilateral project to some of its industrial needs. An industrial resident can be delegated to IMEC by the partner to join IMEC's research teams, typically for one year. Intellectual Property The intellectual property rights of the deliverables are defined before the project starts and forms part of the agreement: R1: the more generic or methodological type of project results, based on IMEC's strategic knowhow (background information, R0) are co-owned by both IMEC and the industrial partner, without any accounting to each other. R2: company-specific results or confidential information are the exclusive ownership of the industrial partner. R0: results owned exclusively by IMEC are available for licensing, providing full user rights for the industrial partner. This type of IP relates to more fundamental, generic technologies. In addition, the industrial partner gets access to IMEC's background information in the research domain specific to the IIAP, and the R0 and R1 results of the other industrial partners in the same IIAP. Benefits for Partners The industrial partner gets access to strategic IMEC background information at an early stage. The industrial partner gets access to other R0 and R1 (shared) results from other partners in the same IIAP. The industrial researcher (resident) is taken up into the IMEC mixed research team to execute the IIAP program. This intensifies the process of technology transfer and shortens the learning curve. The program induces a flexible interaction between the research team at IMEC (including the industrial researcher) and the industrial headquarters. Each IIAP contract is conducted on a bilateral basis, allowing for tuning and confidential information (exclusive R2) as described in the bilateral agreement. Each IIAP contract is standard as well as the corresponding prices. Leverage effects Joining an IIAP program induces: IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 47 of 77
A pricing leverage, through the cost-sharing principle of R0 and R1 results. An information leverage, as each industrial partner gets access to much more information (project info, IMEC's background information, R0 and R1 of other program partners) than its financial commitment. A cross-fertilization leverage, through the sharing of R0 and R1 results and through a good combination by IMEC of leading-edge partners, also coming from complementary fields (e.g. foundries, equipment or materials suppliers) but interested in the same research topic. A time-to-market leverage, as the industrial partner gets a competitive advantage in both strategic results and rapid time-to-market. For further details regarding the exploitation plans of IMEC, please refer to Annex II. 12.2.3. Approach, timing for use of result D11 IMEC is continuously doing prospective efforts to attract new partners in the Reconfigurable Systems Industrial Affiliationship Program. The generated results within this program are being transferred to the partners on a permanent basis. Efforts will also be undertaken to license the IP library directly to IP vendors and other interested parties.
12.3.
Detailed description of result D14
12.3.1. Description of result D14 The result is the detailed architecture design of a power efficient configurable logic block (CLB), taking into consideration the constraints and limitations of the design supporting tools. Full-custom design using the chosen silicon technology of 0.18 m STM technology, exhaustive design exploration for selecting optimal design parameters, for instance number of look-up table inputs, in terms of power, area, and performance provided the appropriate results regarding with the design of configurable block. The low-energy CLB design of was the first critical step for implementing efficient low-energy fine-grain reconfigurable hardware. 12.3.2. Market size of result D14 DUTH used the design of configurable logic block for teaching purposes, because it is an excellent case study for undergraduate students to understand the concepts of full-custom design of FPGAs, topic which is usually is not well-described in existing textbooks. More specifically, the undergraduate programme of DUTH includes two semester courses, VLSI Systems I & II, where 110 and 25 students take these courses, respectively. Concerning the graduate students, they may design their own configurable logic block using Europractice silicon technologies in context of the MSc and PhD semester courses “Design of Integrated Systems for Low Power” and “Integrated Systems of hardware and software”. During the academic year 2004-2005, 10 MSc and 4 Ph.D. students enrolled to these courses. It is estimated that 15 MSc and 4 Ph.D. students may take these courses for the next academic year 2005-2006. Furthermore, during the academic year 2004-2005 DUTH’s subcontractor (AUTH) provided similar graduate courses with 10 enrolled MSc students. It is estimated that similar number of MSc students will take these graduate courses for the next academic year.
12.3.3. Approach, timing for exploitation of result D14 The implemented IP will be available in by the mid of second year. Various teaching instruments such IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 48 of 77
as class notes handouts and class assignments/projects will be prepared for absorbing the concepts of full custom design of configurable logic building block for undergraduate and graduate students. Similar material can be also used for graduate courses of AIT (INTRACOM’s educational centre). A tutorial lecture on low-power FPGA architecture design and tools took place by personnel of AUTH (DUTH’s subcontractor) at the Silesian University of Technology in Gliwice, Poland, in March 2004. The number of attendees is approximately 27. Similar activities will take place in the near future with other Polish Universities and Toulouse University, France because AUTH is involved into bilateral national projects for human capital mobility. The result of configurable logic block is closely related with the results from D26-D30. Consequently, the same distribution channels can be used.
12.4.
Detailed description of result D15
12.4.1. Description of result D15 This result provides the usage support to allow designers to build and integrate an interconnect network in several applications, using a library of network building blocks (D11). It consists of two major components. The first component comprises the simulation models of the network, which enables the modeling of the complete system that runs on the reconfigurable platforms. It allows to see the impact of different network technologies. The second component consists of the network instance generators, which will allow the designer to create a network according to the structure of the reconfigurable system he/she wants to develop. 12.4.2. Market size of result D15 This result complements the library of networking building blocks (D11) and will most probably be exploited together with that library. IMEC’s business strategy is based upon their ‘Intellectual Property (IP) Portfolio’. The abovementioned result will be an extension of this ‘IP Portfolio’ and will be exploited via several ways: IMEC’s Industrial Affiliation Programs (IIAP) (e.g. IIAP on Reconfigurable Systems); Bilateral contracts with the national and international industry and universities; Technology transfers and licensing to industry or spin-off companies. The targeted customers of this result are fine-grain reconfigurable hardware (FPGA) semiconductor companies, coarse-grain reconfigurable hardware semiconductor and fabless companies, system design houses and micro-electronics companies with an interest in using reconfigurable hardware for optimal implementation of dynamic hardware applications. The extension of the ‘IP Portfolio’ will also be used as ‘Pre-existing knowledge’ for future research and development projects and PhD topics. For a more elaborate description of the IIAP model, the reader is referred to the description of result D11. 12.4.3. Approach, timing for exploitation of result D15 IMEC is continuously doing prospective efforts to attract new partners in the Reconfigurable Systems Industrial Affiliationship Program. The generated results within this program are being transferred to the partners on a permanent basis. Efforts will also be undertaken to license this result together with the IP library (D11) directly to IP IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 49 of 77
vendors and other interested parties.
12.5.
Detailed description of result D18,21
12.5.1. Description of result D18,21 The results are: i) the development of a systematic design methodology towards behavioral-level optimisation,and especially, the development of a novel methodology for energy- and performanceoptimized design of dynamic memory allocators and ii) the development of a prototype design support software for addressing time-consuming task of dynamic memory management of the behavioral optimization approach. More specifically, the methodology is already finalized and the corresponding tool was completed by end of June 2004. Both methodology and tools target to wireless telecom applications. 12.5.2. Market size of result D18,21 As stated in the previous sections since neither RSoCs nor systems using RSoCs are available today, INTRACOM intents to use RSoCs for the development of its future wireless telecom products to improve its competitiveness. INTRACOM has a wide portfolio of solutions, including wireless access network infrastructure and is poised to promote the use of broadband wireless access, in full cooperation to wire-line broadband access networks. INTRACOM’s access network systems upgrade qualitatively the networks of telecommunications organizations by digitalizing their access network systems and by providing new services (video, Internet, multimedia). Furthermore, INTRACOM has already developed a series of wireless systems in order to provide voice, data and video services in rural, suburban and urban areas, in particular in cases that the use of wire-line transmission systems becomes too expensive, and/or time-to-market is critical to the operator. Wireless systems offer an efficient way to connect agricultural, mountainous and other remote or inaccessible areas to the backbone network and provide alternative routes where there is insufficient telecommunication infrastructure. WIBAS • OFDM technology • P-MP architecture
IAS-W iBRAIN
IAS-W
0
1
2
FBWA Outdoor solutions
• PointPoint-to to--Point • Point Point--to to--Multipoint
3
4
IAS-W iBRAIN
5
6
7
8
9
10
11
12
WIBAS
13
14
15
16
…..
25
26
27
Frequency (GHz) Point-to-Multipoint systems Point-to-Point systems
Figure 11: INTRACOM wireless systems For wireless access the company offers Point-to-Point and Point-to-Multipoint systems. In terms of the latter, the IAS-W product line, which has been available for a number of years, provides narrow band telecommunication services (PSTN, ISDN/BRA&PRA and leased line) and has been proven very efficient and successful for applications in rural, remote and hard to reach areas. This line was enriched with the addition of new WIBAS systems providing broadband services (through 1/FE1, Ethernet, xDSL and / interfaces) to demanding business and residential subscribers in urban areas. These broadband access systems offer a highly flexible and reliable solution for 3G networks IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 50 of 77
and areas with high telecommunication traffic and subscriber densities. Point-to-Point systems include low- and medium-capacity Microlink and Intralink systems (nx64kbit/sec up to 16x2Mbit/sec) operating in the 2 GHz to 38 GHz frequency ranges. These systems are used in providing businesses or remote subscribers access to fixed-line service networks, but are also widely utilized in connecting mobile service base stations with control and transfer centres, as well as in transmission systems linking network nodes. In 2003, the company sustained its strong position in both the domestic market and in Southeastern Europe, despite the unfavorable conditions that prevailed in the telecommunications and IT sectors. The persistently weak demand for telecommunications and IT products and services worldwide had a negative impact on INTRACOM’s main markets, which resulted in a decline in sales. Another contributing factor to this development was the protracted inactivity in the domestic IT market due to the slow release rate of 3rd CSF funds designated for IT and public sector modernization projects. As a result of the above, parent company sales in 2003 amounted to €494 million from €687.1 million in 2002, posting an annual decrease of 28.1%. Meanwhile, the significant geographic expansion of exports continued in 2003 with exports to 50 countries and an established strong presence in Western and Eastern Europe, the Americas, Asia and the Middle East. Total exports in 2003 reached €218.8 million or 44.3% of turnover compared to 40.6% in 2002. For the year 2004, the total revenues are estimated to reach 460 million €, with its wireless systems reaching the 15 million €.
* Consolidated results after the merger with INTRASOFT
Figure 12: INTRACOM’s turnover 1999-2003 Source: INTRACOM 2003 annual report INTRACOM has already begun the development of a BFWA system operating at the 3,5 GHz frequency band and plan to go-to-market within the next 1-2 years. Furthermore, there are plans to enhance its presence in the market by exploiting the 5-6 GHz frequency band, given the advantage that this area is license exempt (5,725–5,850 GHz ISM band), aiming at medium and large enterprises. PERLA will provide the stepping-stone for prototype systems and interoperability tests for unlicensed BFWA equipment Annex I contains an update on the “Business Case for a 5GHz Wireless Bridge Product”, that describes the forecast of sales, cost, revenue and profit issues concerning the 5 GHz point-to-point wireless bridge product that is planned to be offered by INTRACOM. It is presented as an example of how INTRACOM plans to utilize the results of the project. IST-2001-34379/WP7/D39/ICOM/R AMDREL Consortium
Deliverable D39
Page 51 of 77
According to project’s objective, an improvement of the implementation efficiency by 20% will be achieved. INTRACOM plans to utilize the results of AMDREL for upgrating its outdoor systems (both point-to-point and point-to-multipoint) as well as for the development of new ones (e.g BFWA system operating at the 3,5GHz frequency band). The utilization of AMDREL’s results will depent of the development roadmap of each individual product, the company’s policy and the market evolution. The academic partner (DUTH) used and will use the results for teaching purposes of graduate students in the course “Integrated Systems of Hardware and Software”, where 10 MSc and 4 Ph.D. students were enrolled, during the academic year 2004-2005. It is estimated that 15 MSc and 4 Ph.D. students may take these courses for the next academic year 2005-2006. Also, one MSc thesis and two Diploma Theses were completed during year and one additional MSc thesis and two Ph.D. dissertations are under progress with topics related with dynamic memory management optimization methodology and tools. 12.5.3.
Approach, timing for exploitation of result D18, 21
The system-level methodology and the accompanying design tool delivered by M24 and M28, respectively. INTRACOM has identified the need for RSoCs and expects to exploit the RSoC opportunities provided by AMDREL basically for the development of competitive wireless communication products where more flexibility is needed. INTRACOM will be able to provide several solutions for WLAN deployments, depending on the customer’s budget or his technical demands. There will be a direct channel-to-market or a channel-to-market through VARs (Value Added Resellers). One of the targets for such products is the SOHO market (Small Office-Home Office) for that is not clearly developed in Greece, or in Europe. However, this market is already starting to be addressed and will continue to receive more attention as time passes by. Wireless LAN technologies are effectively contributing to SOHO development and INTRACOM, as a system’s company expects to commercially exploit the results of AMDREL project, mainly for outdoor wireless communication applications: INTRACOM plans to exploit the results through its strategic partnerships with other end-product vendors and through its strong point of presence in the East Europe region (INTRACOM has many subsidiaries in that region). Concerning the system level design methodology, the corresponding results are exploited by DUTH through teaching activities include hand notes material, class projects and half-day seminars sponsored by IEEE CAS & SSC Greek Chapter. Furthermore, one MSc thesis and one Ph.D. were completed and it is estimated that one additional M.Sc. thesis will be completed by mid of 2005 and one by mid of 2006, while the two Ph.D. dissertations by end of 2005 and 2006. The main research results of all theses are related with the topic of “Memory Management”. From “planned activities” of D33, DUTH people provided the three planned lectures in University of Patras, Dept. Of Electrical & Computer Engineering, Aristotle University of Thessaloniki, Dept. of Physics, Division Electronics and Informatics and National Technical University of Athens Dept. Of Electrical & Computer Engineering with 14, 11 and 32 attendees in each lecture, respectively. The main theme was the “Behavioural Optimization of Wireless Applications with emphasis on Memory Management”. An additional tutorial lecture about the topic of “Behavioral level Optimization Methodology”, planned activity described in Section 11.5 “Other activities” was took place during MARLOW Workshop Network of Excellence IST project in 14th September 2005, Santorini, Greece with 35 participants. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 52 of 77
A new activity for the year 2005 will take place in Technical University of Delft, after the ivitation of Prof. Stamatis Vassiliadis, where Prof. Dimitrios Soudris will give a tutorial about “Dynamic Memory Management”.
12.6.
Detailed description of result D23
12.6.1. Description of result D23 The result is an IP library of reusable VHDL-described components, which can perform critical tasks of systems in the targeted wireless communications domain. The main focus is on IPs for FFT, FIR filtering, taking into consideration plethora of design parameters will be delivered. These descriptions can be either directly mapped on the available reconfigurable hardware or used as input for the development of optimised lower level descriptions that can be directly on the available reconfigurable hardware. 12.6.2. Market size of result D23 The design teams of INTRACOM will use the relevant IP library for RSoC development, while the academic partner (DUTH) will use some IPs in graduate courses as case studies and or class projects for absorbing the concepts of Design for Reuse. Additional market sector will be customers from SMEs, system design houses, fabless companies, spin-off companies with an interest in wireless or multimedia applications. Reconfigurable hardware solutions are very crucial in the domain of telecom application where standards are emerging and high degree of flexibility is needed. A multimode model ensures that the strengths of all of the modes of operation will persist in the market place. On the other hand, the various market segments have a distinct set of demands and requirements that differ from each other. Again, a multimode model of operation is best suited to meeting all of these needs across the broad spectrum of a diverse WLAN marketplace. A more detailed description regarding the market size for INTRACOM can be found in section 12.5.2. The academic partner (DUTH) will use the results for teaching purposes of graduate students in the course “Low Power Design of Integrated Systems” and in the course “Designing Embedded Systems”, where it is estimated that 15 M.Sc. and 2 Ph.D. student are enrolled. Also, one MSc thesis and two Ph.D. dissertations are under progress with topics related with static and dynamic memory management optimization methodology and tools. 12.6.3. Approach, timing for exploitation of result D23 The implemented IPs will be available in by the mid of third project year (i.e 2004). Various teaching instruments such as class notes handouts, case studies and class assignments/projects will be prepared for absorbing the concepts of Design for Reuse in MSc. and Ph.D. programmes of DUTH. In particular, the IP design of FFT and reconfigurable FIR will be used as a case studies of semester course “Low Power Design of Integrated Systems”. In addition, these two IP modules will be included in an IP library for implementing component-based embedded systems in lab experiments of the graduate semester course “Designing Embedded Systems”. The number of the enrolled students for last winter semester was 19 students. It is expected that similar number of graduate students will choose the same lesson for the next year. Futhermore, two M.Sc. theses will be completed by end of 2004 and 2005, where a part of presented results will be related with the design of IP modules. In addition, efforts will also be undertaken to license the IP library directly to IP vendors and other interested parties. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 53 of 77
A more detailed use plan for INTRACOM can be found in section 12.5.3.
12.7.
Detailed description of result D25
12.7.1. Description of result D25 Deliverable D25 is described as a “Systematic methodology form implementation of functional reconfigurable hardware blocks”. Here, the term “methodology” is taken to be the set of design tools, working methods and protocols that form a professional design flow capable of delivering high-quality and maintainable results. In this case, a methodology as a subset of a complete digital ASIC (or ASSP) design flow is taken, which specifically addresses the complex requirements of designs using (digital) blocks that do not have a unique function (reconfigurable). The target application for this design flow is for the specific development of baseband processor devices for wireless LAN applications. The development of a device for the IEE802.11 set of standards is taken as a driving application for proof of the methodology. In this application field, the use of coarse-grained reconfigurability concepts has been identified as a potentially powerful technique for optimization of the design towards critical design parameters on the one hand, and stringent economic considerations on the other. Therefore, the methodology developed in AMDREL, and the resulting application device, will focus uniquely on this specific class of reconfigurable entities. (Fine-grain and therefore mixed-grain reconfigurable architectures will not be addressed specifically by STM. The complementary work of the other partners in the project will describe the specific additions to the methodology required for these classes of reconfigurable structures). The methodology presented in deliverable D25 will be derived from an existing design flow based on the use of SystemC and UML for high-level modeling, and will describe the specific interfaces and techniques for the use of specifically identified, commercially available tools for the support of reconfigurable structures. 12.7.2. Market size of result D25 The design methodology, as described in D25 will not per se generate specific revenue for STM – the sale of EDA tools is not a core business activity of the group. However, the commercial value of the resulting methodology may be described by analysing the available market to be addressed by STM in the chosen WLAN segment. This will give in fact a conservative estimate of the ‘market size’, as the methodology developed for the specific WLAN application will also be applicable to other application domains to be addressed by the company’s design groups in the future (e.g. mobile terminals, Bluetooth™ devices and many others). However, for simplification, only the WLAN market will be looked at here. This evaluation is based on market analysis results available at the end of 2002. In their position as number 3 in the world-wide semiconductor market, STM is well placed to realise a siginificant market share in this domain, both through the sale of devices to the open market, and particlarly also through sales to their key strategic partners, who are amongst the leading companies in the world for wireless communications. The analysis of a number of market analysts’ reports allows the following conclusions to be drawn: IEE802.11-based standards will prevail, despite present perceived technical weaknesses compared to e.g. Hiperlan2 (QoS management, mainly). The market will be dominated by data applications, at least until 2005. This renders the technical weakness to be less significant. Accurate estimation of the actual market size is difficult, due to the very high price elasticity causing a wide range of estimates for the market near-term. (From 2005, the predictions seem to converge). However, all analysts agree that the WLAN world-wide market will be a key business generator in the coming 3 to 5 years. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 54 of 77
The move from 2.5GHz to 5GHz standards will be gradual, due to support needs of an already significant installed base. (Scares about legislation possibly leading to licensing of the 5GHz may or may not be founded). The WLAN boom starts now. From this, any companies not presently having a well-defined product roadmap and design know-how in place are likely to miss the train. The following graphs summarise an averaging of the various market analysts’ views to give an indication of the expected business to be gained through timely availability of ‘industrial strength’ and competitive designs.
2 .4 G H z (b o r g )
5 GH z
Millions of $
1000 800 600 400 200 0 5 GHz 2 .4 G H z (b o r g )
2000 2001
2002 2003
2004 2005
2006
0
0
29
163
316
423
677
262
217
300
277
259
282
226
Figure 13: WLAN Silicon Market Evolution, 802.11Summary (Shipments by Technology)
From this, it can be seen that the market size for the addressed WLAN application is expected to more than double in the period 2003 to 2006. The baseband function is a core requirement for EACH terminal and network access-point. The efficiency of the design of this key function therefore has a significant impact on the performance of the devices in marketing terms. The methodology described as deliverable D25 therefore has a direct impact on the performance of STM’s silicon solution in the marketplace: the methodology can therefore be viewed as the entry-ticket to this fast growing and lucrative market.
12.7.3. Approach, timing for exploitation of result D25 The approach to the development and valorization of the methodology (deliverable D25) by STM can be viewed as a five step process: 1) 2) 3) 4) 5)
Pre-existing methodology backbone based on SystemC Methodology extensions supporting coarse-grained reconfigurability (AMDREL) Implementation of blocks (AMDREL) Integration of blocks into productised SoC solutions, generating revenue (post-AMDREL) Methodology refinement and maintenance to the state-of-the-art.
Step 1 represents the use of pre-existing know-how and experience with SystemC and it’s incorporation into the design group’s daily working methods. Steps 2 and 3 occur during the course of the AMDREL project, and are strongly interactive (the IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 55 of 77
methodology is ‘tested’ on-line, though the architectural decomposition, modeling, and development of chosen blocks in the target solution). Steps 4 and 5 represent the actual valorization/exploitation of the AMDREL project results, as well as the necessary maintenance of the methodology to keep track of the continuous improvements both in internal design flows as well as in the externally available EDA tool offering. Though the various blocks developed in the AMDREL project will be highly useful for STM in the short term, they are not the most valuable contribution. This lies in the setting up of a workable design flow using top-down methodologies for building safe designs of very complex IC’s (SoC). The design methodology of D25 will be a key element in establishing this design flow, specifically for the WLAN design activity. STM’s business unit responsible for WLAN activities develops new IC’s through design centers in Belgium (STMB, where the headquarters of the Telecom Group, in which the wireless activity is sited, is located), in Turkey and in Italy. The design group in Belgium – the partners in this project – are primarily responsible for the development of implementation architectures for the wireless group, specifically for the baseband function, as this calls upon the existing signal-processing expertise. This activity includes the optimization of process algorithms along with the platforms upon which they will run. The design team also pioneered the use of a top-down methodology based on SystemC specifically for the development of complex WLAN functions. Today, the activity is focused firmly on the WLAN signal processing path, while design groups in Italy are responsible for other complex parts (e.g. the Layer-2 MAC functions). The design group in Turkey is called upon to assist in the implementation aspects of the structures defined in Belgium and Italy, and they make valuable contributions by feeding back intermediate results to the architecture specialists on the performance of specific implementations and algorithms. All groups make use of the pre-existing SystmeC backbone methodology, and in all at the time of writing, some 38 engineers are dedicated to the WLAN field who will call upon the AMDREL results, specifically D25, in the future. STM’s use of the D25 result will therefore not be limited to the immediate vicinity of the specific engineers working on the AMDREL project, but will also be adopted by the other parts of the WLAN design group in the different geographic locations. It is intended to be a primary tool for all future developments, as it is felt that such a top-down approach is the only realistic answer to the extreme complexity of modern IC design tasks, especially when distributed over remote locations. It is so that the SystemC backbone methodology is also used by other design groups in other application areas. For example, almost all new STM IC’s for wired broadband connectivity are designed using it, though these do not today benefit from the D25 extensions which specifically address the use of reconfigurability techniques for optimizing designs. Once the maturity of the approach has been proven by the completion of the AMDREL project, these groups also will be encourage to make full use of the approach. With this approach, a high return on the development investment by STM, together with the other AMDREL partners, can be secured: there is a real product in sight, albeit some time after the AMDREL project has completed. Excluding any revenue from the WLAN market that may be generated through punctual actions based on devices derived from marketing activities of a tactical nature, the marketing of optimized devices generated specifically from the AMDREL results may be expected to start in 2005. As a quantified indication of the return, specifically for the Zaventem site of STM, the following assumptions can be made. Out of the system designers, HW ans SW development engineers, we estimate that about 12 individuals may be exposed to the benefits of using the AMDREL methodology in the coming few years. This does not entail a guarantee, as the suitability of the approach will be evaluated on a case-by-case basis as projects arrive. However, interest already exists for use by projects in the domains of advanced DSL processing and in future wireless technologies such as UWB. Taking the assumption that 50% design-time may be saved when the methodology is used, then IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 56 of 77
an equivalent of 6 persons can be taken as an equivalent economic benefit. Using a standard rate of 150.000 euro per year for an engineer, the total equivalent value can therefore be estimated to be 900.000 euro per year. In addition, the possibility of generating revenue through licensing of the blocks, processes or other know-how generated in the course of the AMDREL project may also be considered. However, this is not a core business activity for STM, and would only serve as a tactical activity in the context of longer-term strategic agreements. As such they cannot be quantified nor committed to.
12.8.
Detailed description of result D26,27,28,29,30
12.8.1. Description of result D26,27,28,29,30 The results are: (i) the circuit-level design of a fine-grain reconfigurable IP block and (ii) accompanying toolkit for supporting the design procedure. More specifically, the detailed design of the building blocks (CLB, switches, interconnections) including power optimization techniques, provide the fine-grain architecture. Using 0.18 m STM technology, a full-custom 8×8 fine-grain IC was designed. To support alternative fine-grain reconfigurable architectures, i.e. design space exploration, function mapping, placement, routing, and reconfiguration bit-stream generation, a design environment based on public-domain and new tools as well as an appropriate user interface was developed. 12.8.2. Market size of result D26,27,28,29,30 The industrial partner (INTRACOM) will integrate the relevant results for RSoC development, while the academic partner (DUTH) will use this result for teaching purposes of undergraduate and graduate students. Since May 2004, the developed design environment is available to users though AMDREL’s website http://vlsi.ee.duth.gr/amdrel, and therefore, people at least from academia may use the derived design flow or individual tools for teaching purposes (laboratory project, graduate projects etc). Here, it should be mentioned that DUTH and University of Toronto, Canada have reached an agreement for updating Toronto’s existing tools and use new tools from DUTH to fill some gaps in its design flow. Toronto’s tools are the most mature public domain tools all over the world and therefore, there is a great potential for further use of the developed tools. Up to now, the whole design has been distributed officially (with signed license) to two academic institutes: 1) CSEM: Centre Suisse d'Electronique et de Microtechnique SA Prof. Christian Piguet and 2) Dr. Wim Vanderbauwhede, EPSRC Advanced Research Fellow, Department of Computing Science, University of Glasgow and three companies: 1) ALMA Technologies, Greece (http://www.alma-tech.com), 2) Evatronix, Poland (http://www.evatronix.pl), 3) CAST (http://www.cast-inc.com), USA. A more detailed description regarding the market size for INTRACOM can be found in section 12.5.2. 12.8.3.
Approach, timing for exploitation of result D26,27,28,29,30
The hardware design and software development of the fine-grain platform was finished by end second year (i.e. February 2004). Since May 2004 all tools can be accessed through AMDREL website. Also DUTH used the developed design flow for its students in the context of the 9th semester course VLSI Systems II (the average number of enrolled students is around 35) and in one Master’s Thesis about reconfigurable architectures. DUTH’s subcontractor also used various forms teaching activities the developed design flow, since it is directly-related with the result of D14. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 57 of 77
Taking into consideration the planned activities from D33 the current situation is as follows: DUTH provided one tutorial lecture in the Dept. of Electrical and Computer Engineering, University of Patras, Greece with the context MSc. Graduate studies “Integrated Systems of Hardware and Software”. The number of attendees was twenty-five (21) students. The lecture’s topic was about “Architecture of Fine-Grain Reconfigurable Hardware and Tools”. From the planned activities described in D33, we accomplished two of them, while the last postpone for some months due to the schedule re-organization of the initiative where the last lecture belongs to.In particular, one lecture on low-power FPGA architecture and design took place in given by personnel of AUTH (DUTH’s subcontractor) at the Silesian University of Technology in Gliwice, Poland, in March 2004 with 27 attendees. An additional tutorial lecture about the “Low-Energy FPGA Architecture”, planned activity described in Section 11.5 “Other activities” was took place during MARLOW Workshop Network of Excellence IST project in 14th September 2005, Santorini, Greece with 35 participants. Finally, one more lecture will be carried out in Toulouze CNRS by first half of 2005. Concerning the graduate students, they can use the design flow to develop their own fine grain block having as input silicon technologies through EUROPRACTICE. Also, in context of graduate course “Design of Integrated Systems for Low Power Design”, where 10 MSc students and 4 Ph.D. students are enrolled for the spring semester of 2005, the results about the low power techniques and their impact on FPGA architectures, will be included in class handouts. Furthermore, one MSc thesis entitled “FPGA mapping tools” and one PhD dissertation entitled “Design and implementation of low power VLSI Systems” were completed by DUTH graduate students during the third year of project. In addition, the collaboration among the academic partner and Univ. of Toronto we allow distributing the developed tools into a large number of users including research institutes, and SMEs. Also, this strategic collaboration will make more probably the tools update from other academic users. DUTH provides the necessary personnel for supporting the developed design flow.. In addition, after a specific request we distributed a specific tool (i.e. DRUID) from the design flow to Prof. Tsutomu Sasao,
[email protected], Kyushu Institute of Technology, Japan. Finally, the complete design flow is available through the mirrored hyperlink http://microsys6.engr.utk.edu/ece/msn, which has hundreds of hits every day. The responsible person this website is Prof. Don Bouldin, Electrical & Computer Engineering, University of Tennessee. The academic partners DUTH/AUTH follow a three step approach for possible commercialization of the developed design flow tools. a. Determination the target groups (e.g. universities, institutes, SMEs), which can use and/or evaluate the developed tools. b. Determination the type of cooperation/communication (e.g. bilateral contacts, contracts, licenses, national innovation centers) with the different parties. c. Exploiting the comments, the suggestions and the responses from the various parties, we will proceed with the development of the second version of the design flow. Up to now, the whole design has been distributed officially (with signed license) to two academic institutes: 1) CSEM: Centre Suisse d'Electronique et de Microtechnique SA Prof. Christian Piguet and 2) Dr. Wim Vanderbauwhede, EPSRC Advanced Research Fellow, Department of Computing Science, University of Glasgow and three companies: 1) ALMA Technologies, Greece (http://www.alma-tech.com), 2) Evatronix, Poland (http://www.evatronix.pl), 3) CAST (http://www.cast-inc.com), USA. Due to the small time period between the time point where the design flow was available through internet and the scheduled deadline for preparing the D39 DUP report, responses from the academia and industry will be available during the next review meeting. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 58 of 77
ANNEX I
BUSINESS CASE FOR A 5 GHZ OUTDOOR WIRELESS BRIDGE PRODUCT - Version 5 -
(Update version)
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 59 of 77
ABSTRACT This document contains an analytical business case that describes the forecast of sales, as well as cost, revenue and profit issues concerning the 5 GHz point-to-point outdoor wireless bridge product that is planned to be offered by INTRACOM. In addition, a market overview and a system overview describing the architecture/topology of the wireless bridge product are provided. This document is strongly related to the IST EASY project due to the fact that the main exploitation path of INTRACOM within the EASY project concerns the enhancement of its wireless portfolio with the development of a high-speed point-to-point outdoor wireless bridge system operating in the 5 GHz frequency band aiming mainly at medium and large enterprises. This wireless system is based on the dual-standard SoC that has been developed within the EASY project.
1.
INTRODUCTION
INTRACOM’s access network systems upgrade qualitatively the networks of telecommunications organizations by digitalizing their access network systems and by providing new services (video, Internet, multimedia). Furthermore, INTRACOM has already developed a series of wireless systems in order to provide voice, data and video services in rural, suburban and urban areas, in particular in cases that the use of wire-line transmission systems becomes too expensive, and/or time-to-market is critical to the operator. Wireless systems offer an efficient way to connect agricultural, mountainous and other remote or inaccessible areas to the backbone network and provide alternative routes where there is insufficient telecommunication infrastructure. INTRACOM’s outdoor wireless systems are distinguished in Point-to-Point and Point-to-Multipoint systems (Figure 14). Point-to-Point products are divided into four main series: The low capacity radio products (FQUAD 450 and DIGILINK 450) provide services of one-channel (64 Kbps) up to fourchannels (4x32 Mbps) with the use of ADPCM in the low UHF band of 400-470 MHz. They can be deployed to offer telephony, basic-rate ISDN and data services to remote subscribers. MICROLINK and INTRA-LINK series comprise digital microwave radio relay systems designed to offer costeffective solutions in rural/suburban/urban areas. They cover a wide range of frequencies and can satisfy various capacity requirements depending on the application. They can be deployed in mobile telephony networks, public fixed networks, corporate networks and subscriber access networks.
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 60 of 77 FQUAD 450 DIGILINK 450
POINT-TO-POINT Low / Medium Capacity Radio Systems
MICROLINK FAMILY INTRALINK FAMILY
IAS-W POINT-TO-MULTIPOINT Wireless Access Systems
i-BRAIN
WIBAS Figure 14: INTRACOM’s wireless access network systems
Point-to-Multipoint products include the IAS-W, a digital wireless access system based on TDMA architecture, and the i-Brain a broadband system based on IP. IAS-W network solutions are composed of a central node and a number of remote nodes (up to 128) including terminal and repeater notes. The central node is connected to the telephone exchange and communicates with the remote nodes through radio transmission in the 1.5, 2.6, 3.5 or 10.5 GHz frequency bands. The subscribers can be connected to the remote nodes through copper pairs or DECT technology wireless links and can have access to telephony, ISDN and data services. i-Brain is basically a wireless IP radio system which is designed to meet the increasing traffic demands for voice/data/video. i-Brain, based on IP technology, enables operators and service providers to offer multiple services with diverse requirements to the subscribers. In addition, ICOM is developing the WIBAS (Wireless INTRACOM Broadband Access System), which is a point-to-multipoint system targeted for medium to high population density areas. It is a second generation LMDS system operating at 26 and 3.5 GHz frequency bands that will offer broadband services through a standard 120 Mbps wireless link, supporting ATM or IP-based voice and data services with a maximum of 5 Km access radius. One of the objectives of INTRACOM in the area of wireless links is the enhancement of its wireless portfolio by filling the frequency gap (Figure 15) with the development of a 5 GHz point-to-point outdoor wireless Ethernet bridge offering high data rates and aiming mainly at medium and large enterprises. The new bridge will be based on the dual-mode SoC developed within the EASY project. INTRALINK
IAS-W
FQUAD 450 DIGILINK 450
0
1
IAS-W iBRAIN
WIBAS MICROLINK IAS-W iBRAIN
MICROLINK INTRALINK
INTRALINK INTRALINK
WIBAS
New wireless bridge
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
...
25
26
Frequency (GHz)
Figure 15: INTRACOM’s plans to fill the frequency gap
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 61 of 77
In the following sections of this document, a market overview describing the outdoor bridges market and the existing similar products as well as a system overview describing the architecture/topology of the INTRACOM’s new wireless bridge product are provided. In addition, a system cost analysis as well as the forecast of unit shipments, revenue and profit concerning the new 5 GHz wireless bridge product are presented.
2.
MARKET OVERVIEW
According to Maravedis Inc. (“WiMAX, NLOS and Broadband Wireless Access (sub-11GHz) Worldwide Market Analysis”, February 2004) as well as to internal sources, the worldwide BWA (Broadband Wireless Access) unit shipments forecast for Backhaul applications and for the period 2005 to 2009 are summarized in Table 4. Year
2005
2006
2007
2008
2009
Worldwide BWA unit shipments forecast for Backhaul applications
210,963
478,256
903,468
1,380,120
1,850,550
Table 12 Worldwide BWA unit shipments forecast for Backhaul applications Also, according to the same market report the BWA (sub-11GHz) market percentage concerning the unlicensed bands is given in Table 5, for each year of the aforementioned period. Year
2005
2006
2007
2008
2009
Percentage of the unlicensed bands
30 %
29 %
25 %
19 %
15 %
Table 13 Percentage of the unlicensed bands Under the assumption that the unlicensed part of the total unit shipments for Backhaul applications concerns the outdoor bridges market, the worldwide outdoor bridge unit shipments for the period 2005 to 2009 are summarized in Table 6 (see also in Figure 16). Year
2005
2006
2007
2008
2009
Worldwide outdoor bridge unit shipments forecast
63,289
138,694
225,867
262,223
277,583
Worldwide bridge unit shipments
Table 14 Worldwide outdoor bridge unit shipments forecast
250,000 200,000 150,000 100,000 50,000 0
2005
2006
2007
2008
2009
Figure 16: Worldwide outdoor bridge unit shipments forecast
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 62 of 77
The bridge market is a small portion of the enterprise wireless market (in terms of unit shipments and competition) compared to the access point and mobile terminal WLAN market (indoor market). The bridge market focuses on those end-users looking for an alternative to installing expensive cabling in a campus environment or leasing a line from a local service provider in order to connect buildings or locations that are often far from each other on a campus environment, educational setting or manufacturing facility. In the following, a survey of the major existing solutions concerning point-to-point outdoor wireless bridges is presented. 3Com’s 11 Mbps wireless LAN outdoor Bridge solution is a building-to-building bridge with integrated antenna and power-over-Ethernet cable in a durable, weatherproof enclosure. The wireless bridge can connect cross-campus buildings, or portable or temporary classrooms, at distances up to 16 Km (10 miles). It interoperates seamlessly with other Wi-Fi (IEEE 802.11b) certified access points in large multi-vendor environments. AIRAYA offers the AI108; a new high-speed wireless bridge family aimed at last-mile broadband wireless access (BWA) links and campus data networks that need to send large amounts of data over the air. AI108 takes advantage of the latest 5 GHz technology providing wireless bandwidth between E1/T1, E3/T3, and Fast Ethernet rates. The AI108 wireless bridge employs OFDM modulation technique, operating in the 5.2 GHz band at a range of up to 5 miles. Data is transmitted over a halfduplex radio channel offering scalable data rates from 12 Mbps to 108 Mbps. Each AI108 system consists of an outdoor unit and an indoor unit, interconnected by a special category weatherised cable. Radio link level security is provided by the use of 152-bit SecureRF encryption and MAC address authentication, ensuring the prevention of unauthorized intrusions and data theft. An integrated web server greatly simplifies the configuration process by providing access to all parameters and settings through a single, consistent user interface. Alvarion’s BreezeNET DS.11 and DS.5800 bridges operate in the 2.4 and 5.8 GHz band, respectively. The DS.11 model can bridge distances of up to 15 miles at 11 Mbps, while the DS.5800 model can bridge distances of up to 30 miles also at 11 Mbps, making them ideal solutions for Internet backhauls and campus interconnectivity. Providing an indoor-outdoor architecture wireless infrastructure for optimal range and capacity, BreezeNET bridges leverage DSSS technology, which is ideally suited for high-speed building-to-building connectivity, providing optimal service to broadband applications. Alvarion also offers the BreezeACCESS LB family of bridges that is a good solution for ISPs. Operating in the unlicensed 5.8 GHz band, BreezeACCESS LB leverages OFDM technology to deliver high data rates, high spectral efficiency and immunity to interference and multi-path conflicts. Delivering 72 Mbps, BreezeACCESS LB ensures reliable, high-bandwidth connectivity (up to 30 miles) to Ethernet-based services. Avaya’s ROR-II (Remote Outdoor Router) is a point-to-point solution operating in the 2.4 GHz frequency band. It can bridge distances of up to 10 miles at 11 Mbps, using the DSSS technology. By using ROR-II, ISPs can create a wireless network providing Internet access to residential customers. The 10/100Base-T Ethernet interface allows integration in both 10 and 100 Mbps Ethernet environments. High-level security is provided by using data encryption levels of 64-bit WEP and 128bit RC4. CIRRONET offers the SEM2410/2411/2420 wireless bridges that enable high-speed links (up to 1.5 mile) between two Ethernet networks. The SEM2410 offers 230 Kbps of real data throughput, SEM2420 doubles that to a total of 460 Kbps, while SEM2411 offers 1 Mbps data throughput. All models operate in the 2.4 GHz frequency band, use FH technology and include a standard Ethernet 10/100 Base-T interface. Cisco offers the Aironet 350 wireless bridge that enables high-speed long-range outdoor links between buildings and is ideal for installations subject to plenum rating and harsh environments. Its basic IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 63 of 77
features are: high-speed (11 Mbps) and high-power (100 mW) radios delivering building-to-building links of up to 25 miles, DSSS (Direct Sequence Spread Spectrum) modulation technology, frequency band 2.4 to 2.497 GHz, security scheme 128-bit WEP. Enterasys RoamAbout 11 Mbps outdoor solution allows customers to quickly establish high-speed connectivity between buildings without the inconvenience of installing cable or the recurring expense of leased T1 lines, providing an ideal solution for extending wired LANs or building entirely wireless LANs. Enterasys is offering this outdoor solution in a wide variety of antennas and accessories, enabling customers to customize a solution for their particular environment. The High-Rate Outdoor RoamAbout solution offers a full set of wireless features, including: support for Ethernet speeds (by embracing the IEEE 802.11 High Rate draft standard), and enhanced security (by offering 40 and 128bit encryption that supports the 802.11 Wired Equivalent Privacy (WEP) standard). The RoamAbout outdoor solution is compliant with the IEEE 802.11 standard. When 14 dB antennas are added, the outdoor wireless configuration is extended to 3.5 miles at an impressive 11 Mbps throughput. When combined with any third party 24dB antenna, distances of 25 miles at 11Mbps can be achieved. HARRIS offers the Aurora point-to-point bridges that use DSSS technology. The Aurora 2400 device operates in the 2.4 GHz band, and offers deployment of 1xE1/T1 to 2xE1/T1 wireless service as well as remote bridging (10Base-T) with a typical distance of 30 miles. The Aurora 5800 device operates in the 5.8 GHz band, and offers deployment of 1xE1/T1 to 2xE1/T1 wireless service as well as remote bridging (10Base-T) with a typical distance of 30 miles. Intermec’s MobileLAN access 2100 is an 11 Mbps wireless access point available for high-speed, high-throughput, demanding environments (such as outdoor or industrial environments). Compliant with IEEE 802.11b standard, MobileLAN access 2100 sets a new standard in access points with advanced features and better performance. Housed in a NEMA4/IP54 case with heater options, MobileLAN access 2100 is the ideal access point for harsh environments where cold temperatures, small airborne particles and moisture are prevalent. Intermec is offering this solution in a wide variety of antennas and accessories, enabling customers to customize a solution for their particular environment. The maximum achieved range is 533 m. Proxim developed Tsunami family of wireless Ethernet bridges provide a variety of plug-and-play solutions to the growing demand for transparent, reliable, and economical high-speed network interconnectivity. The Tsunami family of wireless Ethernet bridges provides a variety of plug-andplay solutions to the growing demand for transparent, reliable, and economical high-speed network interconnectivity. The first solution is the Tsunami 10BaseT is a wireless Ethernet bridge providing 10 Mbps full duplex (greater than multiple dedicated T1/E1 leased lines) at distances of over 40 miles. It operates at the 5.8 GHz frequency band and allows bridging Ethernet LANs between office buildings, factories, warehouses, and remote locations in a point-to-point scenario. Also, provides a separate T1/E1 connection in addition to the Ethernet connection, allowing the extension of PBX connectivity between buildings without the need for additional leased lines. The second solution is the Tsunami 100BaseT/F is a wireless Ethernet bridge providing multiple capacities of 93, 206 or 208 Mbps aggregate throughput (greater than using dedicated DS-3 leased lines). It operates at the 5.8 GHz ISM band and in addition to the Fast Ethernet connection also provides a separate T1 connection, allowing you to extend PBX connectivity between buildings without additional leased-line costs. The third solution is the Tsunami 1000BaseSX wireless gigabit Ethernet bridge providing data capacity of 430 Mbps. It operates at the 5.2 and 5.8 frequency bands and allows wireless Gigabit point-to-point connectivity at distances up to 7 miles. Furthermore, Proxim developed the Tsunami QuickBridge outdoor wireless bridge family providing the easiest to install, high-capacity alternative to leased lines, T1/E1 connections or IEEE 802.11b bridges offering enterprises a cost-effective, quickly deployable solution for connecting two buildings up to six miles apart. Tsunami QuickBridge comes in four varieties: a) Tsunami QuickBridge 60, which operates in the 5.8 GHz band and provides data connectivity up to 60 Mbps between buildings up to 3 miles apart, b) Tsunami QuickBridge 20, which also operates in the 5.8 GHz band and offers up to 20 Mbps connectivity at a range of up to 6 miles, c) Tsunami QuickBridge 20 with T1/E1 connection, which enables businesses to establish both voice and IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 64 of 77
data connectivity, and offers up to 12 Mbps connectivity for up to 6 miles, and d) Tsunami QuickBridge 11, which operates in the 2.4 GHz band (IEEE 802.11b compliant), and provides data connectivity up to 11 Mbps. The Tsunami family of Ethernet bridges provides wireless solutions that meet the growing demand for transparent and reliable high-speed network interconnectivity. After the acquisition of ORiNOCO product line (from Agere), Proxim also offers the ORiNOCO Wireless point-to-point radio backbone kit that is an easy to install, highly reliable 11 Mbps building-tobuilding wireless solution exhibiting similar capabilities with Tsunami QuickBridge 11. The kit includes all the necessary hardware, software and management components needed to establish a licence free 2.4 GHz wireless LAN bridge that spans up to 6 miles under clear line of sight conditions. The basic kit component is the OR-500 outdoor router, which is IEEE 802.11b compliant and supports 128-bit key security using RC4 encryption. RAD Data Communications will unveil at ITU Telecom World 2003 (Geneva), a solution specifically designed for western European applications for extending the range of services that may be provided over a given wireless link over point-to-point topologies. The AirMux-106, which operates on the 5.47 to 5.725 GHz band, is a hybrid multiplexer that aggregates fractional E1 and Ethernet/IP traffic over a 2.6 Mbps full-duplex wireless link, extending data/voice transmission up to 30 Km. The product uses direct sequence spread spectrum modulation technique. The AirMux-106 conforms to the ETSI standard (EN 301 893) and supports Dynamic Frequency Selection (DFS) and Transmit Power Control (TPC). Raylink’s WISP family offers wireless solutions for outdoor applications (up to 5 miles), providing high performance wireless point-to-point link. They also can be used as simple repeater. The family of products includes a single bridge, the CPE Station which has better enclosure and design for use in strong environments, the 12dBi CPE unit with a built-in 12dBi flat panel antenna, which can receive and transmit data up to a 30-degree arc, and the 18dBi CPE unit with a built-in 18dBi flat panel antenna, which can receive and transmit data up to a 15-degree arc. The WISP solutions operate in the frequency range 2.4 to 2.4835 GHz and are compliant with the IEEE 802.11 standard (up to 2 Mbps data rate with FHSS modulation). SoftHill’s BriLAN VOX performs as a wireless Bridge, Router, Switch, HUB, and active Repeater with the following standard functions, such as transparent bridging, standard IP routing, advanced traffic shaping, packet filtering, wireless point-to-point connections and complete collection of traffic statistics. It supports seamless data connection using the 2.4 GHz ISM band and 5.8 GHz ISM band, enabling the bypassing of fixed line infrastructure. BriLAN VOX can be configured as a simple two ports or powerful multiport device depending on customer's needs. Any combination of maximum six interfaces per device is permitted. WiLAN offers the Ultima3 point-to-point solution in two versions. The first version (Rapid Deployment - RD) is a one-piece device providing data rate up to 12 Mbps for links up to 16 miles. The second version (Extended Range - ER) extends the point-to-point networks up to 47 miles providing the same data rate. Both RD and ER operate in the 5.8 GHz frequency band. WiLAN also offers the LIBRA 3000 and 5800 solutions operating in the 3.5 and 5.8 GHz bands, respectively. The 3000 model bridge distances up to 24 miles, and the 5800 model bridges distances up to 40 miles, providing up to 16 and 32 Mbps data rates, respectively. The LIBRA family is based on an indoor/ outdoor architecture. Finally, WiLAN offers the VIP 110-24 wireless Ethernet bridge operating in the 2.4 GHz frequency band. It uses DSSS technology, providing data rates up to 11Mbps and linking distances up to 34 miles. YDI Wireless offers a set of wireless bridge solutions for multiple frequency bands. The Link CX is a point-to-point, all outdoor radio optimized for backhaul of Ethernet or traditional telecommunications converged voice and data networks. It features license-free radio operation in the UNII (for shortmedium range links) or ISM (for links up to 40 miles) 5 GHz bands using either DS3 or 10/100 BaseT digital interface options. The actual achieved payload throughput is 45 Mbps per way in a Frequency Division Duplexing (FDD) operation. The EX-1 wireless Ethernet bridge is a license-free IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 65 of 77
digital radio that provides wireless point-to-point Ethernet connection. It operates on the UNII frequency spectrum and offers 8 Mbps full duplex throughput on 8 different channels. It uses 1 foot or 2 foot antennas, and a range up to 30 Km can be achieved. The Link 4X is a point-to-point link that transports four E-1 lines on the license-free 5 GHz frequency band. Line-of-sight ranges up to 7 miles are possible. The Backhaul in a Box (BAiB) point-to-point wireless bridge is a complete 5.8 GHz wireless point-to-point system that links two Ethernet LANs together. It consists of two high-gain directional antennas and a pair of 11 Mbps DSSS 5.8 GHz radios in a rugged outdoor enclosure. The 128-bit WEP-plus encryption provides extra security. BAiB is available in two versions. The first has an integrated high-gain one-foot flat panel antenna (with over 15W of transmit power), while the second version features an N-type jack for connecting to higher-gain external antennas. Using twofoot antennas, line-of sight ranges up to 30 miles are possible. The Bridge in a Box (BRiB) point-topoint wireless bridge is a complete 2.4 GHz wireless system that also links two Ethernet LANs. It consists of two high-gain flat panel antennas with built-in IEEE 802.11b wireless LAN devices. BRiB also uses 128-bit WEP-plus encryption. It is available in two versions. The first one is the standard version and provides a transmit power of 2W EIRP, while the second one (Long Range) provides a transmit power of 16W EIRP having a built-in bi-directional amplifier. Line-of sight ranges up to 3 miles (for the standard version) and up to 10 miles (for the Long Range version) are possible. Finally, YDI offers short-range point-to-point wireless links for the 24 GHz (EtherLeap) and 60 GHz (FiberLeap) frequency bands. They can achieve ranges up to 4 miles and 1 mile, respectively.
3.
SYSTEM OVERVIEW AND ARCHITECTURES
Three basic architectures exist in the market for bridge point-to-point wireless systems. The first one concerns an indoor-only solution, the second an outdoor-only solution, while the third is built by an indoor and an outdoor unit. The wireless Ethernet bridge that we have adopted includes two units (indoor and outdoor, see Figure 17). The indoor unit includes the MAC/baseband and IF boards, while the outdoor unit includes the RF board (Figure 18). The adopted architecture has several advantages: Since the whole MAC/baseband and IF processing units are located indoor, no extra effort for wea-ther conditions protection is needed. Note, that in outdoor-only architectures a high-cost waterproof enclosure of large size is required. Flexible architecture allowing easy upgrades (mainly in terms of software), since the MAC/baseband sub-system is located in indoor environment, while the outdoor unit will be remained unchanged. The adopted architecture avoids the losses occurred when the signal is transmitted through a long antenna cable (as in indoor-only architectures), reducing the target bit rate and range of the system. This can also happen in indoor/outdoor architectures when the IF part is located outdoor.
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 66 of 77 ANTENNA
ANTENNA
OUTDOOR UNIT
OUTDOOR UNIT
INDOOR UNIT
INDOOR UNIT
ETHERNET
ETHERNET
Figure 17: Point-to-point wireless link through Ethernet bridges with indoor/outdoor architecture Analog 415 MHz and digital control Analog FLASH
BASEBAND / MAC SoC
ADC / DAC
10 /100 BaseT
5 GHz
SDRAM
BASEBAND BOARD ETHERNET CONTROLLER
80 MHz
IF BOARD
INDOOR UNIT
RF BOARD
OUTDOOR UNIT
Figure 18: Block diagram of the wireless Ethernet bridge product
Since most of the existing wireless systems of INTRACOM are based on indoor-outdoor architectures, the company has significant experience in developing such systems. This will lead to a robust and competitive new product, since most of the design difficulties have already been encountered during the development of the existing products based on similar architecture.
4.
SYSTEM COSTS
Like most systems, the cost of the outdoor bridge product can be divided in two parts: fixed cost and variable cost. The fixed cost that includes the prototype development cost (company’s contribution to the IST EASY project for the development of a baseband/MAC SoC for use in 5 GHz wireless LAN devices), the bridge product development cost (before the production), the non-recurring expenses (NRE) for the baseband/MAC SoC fabrication, as well as fixed marketing and sales costs, is analyzed in Table 7. Description Prototype development cost: company’s contribution to the IST EASY project Development cost: System design, RF and IF hardware development, Baseband/ MAC SoC re-design, Baseband board design and boards integration, System testing, Software development for bridging extensions. NRE (Non-Recurring Expenses) for baseband/MAC SoC fabrication Fixed (initial) cost for marketing Fixed (initial) cost for sales (support, service) Total Fixed Cost
Cost (€) 770.000 750.000 250.000 70.000 30.000 1.870.000
Table 15 Fixed cost of the bridge product IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 67 of 77
AMDREL targets to an improvement of the implementation efficiency by 20% according to project’s objectives. According to internal estimations, the aforementioned improvement will result in a 10% reduction of system’s design. As a consequence, the total fixed cost of the outdoor bridge will be about 1,500,000 €. In order to determine the variable cost of the product, the Bill of Materials (BOM) has to be determined first. The required materials along with their cost are summarized in Table 8. Note, that the cost of the baseband/MAC SoC fabrication includes the production cost of each chip (variable) as well as the NRE (fixed - see Table 7). Description of material INDOOR UNIT Aluminum enclosure (45 x 30 x 10 cm) PCB (Printed Circuit Board) for the baseband/MAC board Baseband/MAC SoC production Rest ICs of baseband/MAC board: Ethernet controller, memory modules, D/A & A/D converters PCB for the IF board ICs of the IF board: Saw filters, PLL, VCO Connectors (Ethernet, D-type baseband/IF, N-type IF/RF and power connector) and push button Power supply unit OUTDOOR UNIT Waterproof enclosure (mixed plastic and aluminum – 30 x 13 x 11 cm) PCB for the RF board ICs of the RF board: Power amplifier, PLL, VCO, differential A/D and D/A converters (RSSI, AGC, power control) Connectors (N-type RF/IF and antenna connector) OTHER MATERIALS Antenna (19dBi flat panel, 5.15 - 5.35 GHz) Cables (1m Ethernet cable, 1m power cable, 15m IF cable, 1m antenna cable) Mounting kits for outdoor unit and antenna Capacitors, Inductors, Resistors, Led diodes and consumables Total BOM
Cost (€) 60 25 11,3 43,5 11 9,5 6,3 30 50 11 26,2 17,5 110 37,2 47 15 510,5
Table 16 BOM of the bridge product The variable costs per bridge are summarized in Table 9. Description
Cost (€) 510,5 76,58 587,08 17,61 41,10 58,71
(Bill of Materials) Production cost (15% BOM) Total Variable Manufacturing Cost - VMC (BOM plus production cost) Sales cost (3% VMC) Marketing cost (7% VMC) Administration (10% VMC) Total variable cost per bridge
704,49
Table 17 Summary of the variable costs per bridge
5.
INTRACOM BUSINESS CASE
In this section an analysis in order to present forecasts of INTRACOM’s bridge unit shipments, revenue, cost and profit concerning the new 5 GHz wireless Ethernet bridge product is provided. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 68 of 77
According to the Gartner Inc. (September 2003) as well as to internal sources, the percentage of the wireless outdoor market (sub-11 GHz fixed wireless access systems) that will be covered by the EEMEA (East Europe Middle East and Africa) area is given in Table 10. For the present analysis, we can assume that the same percentage is valid for the bridges market. 2005 Percentage of total wireless outdoor unit shipments in EEMEA area
2006
24.3 %
23.8 %
2007
2008
21.9 %
2009
20.3 %
18.7 %
Table 18 Percentage of the wireless outdoor market covered by the EEMEA area By combining the figures of Table 7 with those of Table 6 (worldwide outdoor bridges unit shipments forecast) we conclude in the following Table 11 that contains the forecast of the bridges unit shipments in the EEMEA area (see also in Figure 19). Shipments (thousand of units)
2005
Bridges unit shipments forecast in EEMEA area
15,379
2006 33,009
2007
2008
49,465
2009
53,231
51,908
EEMEA bridge unit shipments
Table 19 Bridge unit shipments forecast in the EEMEA area 50,000 40,000 30,000 20,000 10,000 0
2005
2006
2007
2008
2009
Figure 19: Bridge unit shipments forecast in the EEMEA area
The growth of the WiMAX-based point-to-multipoint system installations as well as the evolution of the Mesh-type architectures are the main reasons of the reduction of the wireless bridge (point-topoint) unit shipments in the EEMEA area, after the year 2008. Taking into account the average of the current selling prices of ten similar wireless bridge products that are based on an indoor/outdoor architecture (including flat panel antennas), as well as a reasonable yearly reduction rate of the selling price (based on internal sources and on the analysis of iSuppli Corp., September 2002), we conclude in the figures of Table 12 (see also in Figure 20).
Bridge’s ASP forecast (€)
2003
2004
2005
2006
2007
2008
2009
2885
2718
2637
2584
2545
2520
2507
Table 20 Bridge’s ASP (Average Selling Price in €) forecast for indoor/outdoor architecture
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 69 of 77
Bridge’s ASP (€)
2900 2800 2700 2600 2500 2400 2300
2003
2004
2005
2006
2007
2008
2009
Figure 20: Bridge’s ASP (Average Selling Price) forecast for
indoor/outdoor architecture
INTRACOM has a quite good position in the EEMEA area’s market, which is proved by the existing point-to-point and point-to-multipoint systems installations in this area. Total point-to-point system sales in 2001 reached 14.2 million €, of which 10 million € derived mainly the sales of PDH systems from the INTRALINK family, with the remaining 4.2 million € coming from the sales of low capacity FQUAD 450 systems. Mobile phone service providers (Cosmote, Vodafone, AMC, Cosmorom, CBM) accounted for the majority of sales. In 2002, total point-to-point systems’ sales reached 4.2 million €, derived from sales of PHD systems from the INTRALINK family, and low capacity FQUAD 450 radio systems. Deliveries to mobile telephony service providers in Greece, Albania, Bulgaria and FYROM continued in 2003 and are expected to grow, while marketing activities targeting mobile providers in Russia and China are expanded. Potential clients also include Sweden’s Telia, Czech Telecom, and Norway’s Telenor. Total deliveries of point-to-multipoint systems in 2001 reached 8.5 million €, of which 40% were exports to new markets such as Russia, Yemen, Hungary, Armenia and Africa. In 2002, total deliveries of point-to-multipoint systems reached 15.2 million €, of which 75% were exports to markets such as Portugal, Albania, Romania, Pakistan, Kazakhstan, Russia, Yemen and Africa. 2003 domestic market deliveries reached 3 million €, with exports amounting to 13 million €. Also, the introduction of the new point-to-multipoint system (WIBAS) featuring broadband services will enhance the company’s ability to penetrate new markets. In 2003, the deliveries of wireless access systems concerned mainly the following customers: OTE, Cosmote (Greece), Moldtelecom (Moldova), Center Telecom (Russia), STE (Syria), Portugal Telecom, Digitel (Indonesia), Cosmofone (FYROM) and H-Communications (Albania). Based on existing point-to-point and point-to-multipoint system installations and on the current position of INTRACOM in the EEMEA area, two scenarios (aggressive and moderate) concerning the INTRACOM’s percentage of the wireless bridges’ market in this area are investigated (Table 13). In our analysis, general availability of the product is considered to occur in January 2006. As general product availability we define the stage not only after the development period, but also after the field trials, verification and certification, pilot production and possible adjustments have been completed successfully. INTRACOM’s bridge unit shipments percentage
2006
2007
2008
2009
Aggressive scenario
4.0%
5.0%
6.0%
6.5%
Moderate scenario
1.0%
2.0%
3.0%
3.5%
Table 21 Scenarios for INTRACOM’s percentage of the bridges market in the EEMEA area IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 70 of 77
According to the above scenarios the yearly INTRACOM’s bridge unit (half-link) shipments forecast for the period 2006-2009 is given in Table 14 (also in Figure 21). INTRACOM’s bridge unit shipments forecast in EEMEA area
2006
2007
2008
2009
TOTAL
Aggressive scenario
1,320
2,473
3,194
3,374
10,361
Moderate scenario
330
989
1,597
1,817
4,733
INTRACOM' s bridge unit shipments (units)
Table 22 INTRACOM’s bridge unit shipments forecasts (aggressive and moderate scenarios)
3,500 3,000 2,500 2,000 1,500 1,000 500 0
INTRACOM' s bridge unit shipments (units)
Aggressive scenario
1,800
2006
2007
2008
2009
2007
2008
2009
Moderate scenario
1,500 1,200 900 600 300 0
2006
Figure 21: INTRACOM’s bridge unit shipments forecast per year (aggressive
& moderate scenarios)
In the following tables (Tables 15 and 16), the INTRACOM’s total unit shipments, cost, profit and revenue forecasts at the end of each year of the entire period (2006-2009) are given, for both aggressive and moderate scenarios (see Table 13 and Figure 21). The given amounts are in million €. Note, that the revenue forecasts at the end of each year of the entire period are calculated by combining the bridge’s ASPs of Table 12 with the expected total bridge unit shipments. The cost figures are calculated by using the data from Table 7 (fixed cost) and Table 9 (variable cost per unit) in combination with the expected total bridge unit shipments. The total profit figures are calculated as the difference between the total revenue and the total cost.
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 71 of 77
TIME
TOTAL UNITS
Dec-05 Dec-06 Dec-07 Dec-08 Dec-09
0 1,320 3,793 6,987 10,361
TOTAL PROFIT TOTAL REVENUE TOTAL COST -1,496 0,985 5,537 11,335 17,417
0 3,411 9,705 17,754 26,212
1,496 2,426 4,168 6,418 8,795
Table 23 INTRACOM’s total unit shipments, cost, profit and revenue forecasts at the end of each year (aggressive scenario) TIME
TOTAL UNITS
Dec-05 Dec-06 Dec-07 Dec-08 Dec-09
0 330 1,319 2,916 4,733
TOTAL PROFIT TOTAL REVENUE TOTAL COST -1,496 -0,876 0,945 3,844 7,119
0 0,853 3,370 7,395 11,949
1,496 1,728 2,425 3,550 4,830
Table 24 INTRACOM’s total unit shipments, cost, profit and revenue forecasts at the end of each year (moderate scenario) According to the aggressive scenario the total bridge unit shipments of INTRACOM (for the period 2006-2009) will be 10,361 units with a revenue of about 26,2 million €, while for the moderate scenario the total bridge unit shipments of INTRACOM will be about 4,733 units with a revenue of about 11,9 million €. In addition, according to the aggressive scenario the total profit of INTRACOM (for the period 20062009) will be about 17,4 million €, while for the moderate scenario the total profit will be about 7,1 million €. In the following figures (Figures 22,23), the INTRACOM’s total cost, profit and revenue forecasts as functions of time are given, for both aggressive and moderate scenarios. 28
Aggressive scenario 24 20
Million €
16 12 8 4 0 -4 ∆ -05
∆
-06
TOTAL PROFIT
∆
-07
∆
-08
∆
TOTAL REVENUE
-09
∆
-10
TOTAL COST
Figure 22: INTRACOM’s total cost, profit and revenue forecasts as functions
of time (aggressive scenario)
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 72 of 77 14 12
Moderate scenario
10
Million €
8 6 4 2 0 -2 -4 ∆ -05
∆
-06
TOTAL PROFIT
∆
-07
∆
-08
∆
TOTAL REVENUE
-09
∆
-10
TOTAL COST
Figure 23: INTRACOM’s total cost, profit and revenue forecasts as functions
of time (moderate scenario)
From the above figures, the following details can be determined and concluded: According to the aggressive scenario, the break-even point occurs close to the end of the first year (2006) and after selling of 796 units. According to the moderate scenario, the break-even point occurs within the second year (2007) and after selling of about 806 units. The above details concerning the break-even point are summarized in Table 14, along with the return of investment percentage (ROI) for each scenario. As we can conclude, both scenarios offer a very effective ROI percentage. BREAK-EVEN POINT YEAR
UNITS
ROI (RETURN OF INVESTMENT)
Aggressive scenario
2006
796
1164 %
Moderate scenario
2007
806
476 %
SCENARIOS
Table 25 Break-even point details and ROI percentage for both aggressive and moderate scenarios
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 73 of 77
ANNEX II
News Release 1:
Organizations work together to make seamless mobility a reality
Freescale joins IMEC to enhance reconfigurable technology LEUVEN, Belgium and AUSTIN, Texas – October 5, 2004 – Imagine seamless continuity of your favorite video between your home theater DVR and your car’s backseat entertainment system. Imagine pausing a song as your car arrives at home and, as you walk into the house, your home stereo picks up the song at the same spot. Freescale Semiconductor, Inc. (NYSE:FSL) and IMEC are currently in the process of helping you realize this vision of seamless mobility. IMEC and Freescale are working together on reconfigurable multiprocessor systems. By joining IMEC’s Industrial Affiliation Program (IIAP), Freescale plans to deliver leading edge mobile multimedia solutions by utilizing IMEC’s existing and future reconfigurable technology, capitalizing on IMEC’s total system approach and its focus on low power, as well as leveraging IMEC’s system design tools and methodologies. This cooperation promises to enable Freescale to establish its own proprietary seamless mobility platform. Reconfigurable data flow is needed to provide the performance and flexibility required in future seamless mobility products. IMEC’s solution is characterized by a complete system, low-power approach. “The combination of Freescale’s microprocessor know-how and insight into requirements of embedded systems applications, combined with IMEC’s expertise in reconfigurable architectures and system design, makes this collaboration a win-win endeavor,” said Rudy Lauwereins, vice-president of Design Technology for Integrated Information and Communication Systems at IMEC. “IMEC’s technology will complement Freescale’s long-standing technology position in wireless SoC design and provide our customers with innovative and disruptive semiconductor solutions,” said Ken Hansen, senior technical fellow and director of advanced technology for Freescale’s wireless group. “By working together, this vision of seamless mobility may be a reality earlier than originally anticipated.” The architecture is based on IMEC’s novel processor architecture template, which combines VLIW (very-long instruction word) processors and coarse-grain reconfigurable hardware. The combination of these two highly parallel processor architectures complemented with adequate memory architecture, provides an ultra-low-power ASIP (application-specific instruction set processor) with increased flexibility and performance. Together with the architecture template, a C compiler is developed which provides efficient mapping of applications allowing a fast design cycle while keeping the performance breakthrough delivered by the new architecture. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 74 of 77
---ends--Notes to editors About IMEC Industrial Affiliation Programs The IMEC Industrial Affiliation Program (IIAP) is IMEC’s premier R&D collaboration formula for joint R&D between industrial researchers and IMEC research teams. IIAPs focus on a specific topic or technology area. The concept is recognized worldwide as one of the most successful international partnership models for joint development of next-generation technologies. About IMEC IMEC is a world leading independent research center in nanoelectronics and nanotechnology. Its research focuses on the next generations of chips and systems, and on the enabling technologies for ambient intelligence. IMEC’s research bridges the gap between fundamental research at universities and technology development in industry. Its unique balance of processing and system know-how, intellectual property portfolio, state-of-the-art infrastructure and a strong network of companies, universities and research institutes worldwide, positions IMEC as a key partner with which to develop and improve technologies for future systems. IMEC is headquartered in Leuven, Belgium and has representatives in the US, China and Japan. Its staff of more than 1300 people includes over 380 industrial residents and guest researchers. In 2003, its revenues were EUR 145 million. Further information on IMEC can be found at www.imec.be. About Freescale Semiconductor Freescale Semiconductor, Inc. (NYSE:FSL) is a global leader in the design and manufacture of embedded semiconductors for the automotive, consumer, industrial, networking and wireless markets. Freescale became a publicly traded company in July 2004 after more than 50 years as part of Motorola, Inc. (NYSE:MOT). The company is based in Austin, Texas, and has design, research and development, manufacturing or sales operations in more than 30 countries. Freescale Semiconductor's 2003 sales were $4.9 billion (US). For more information: www.freescale.com. For more information: IMEC Media Contact: Katrien Marent Corporate Communication Manager IMEC, Kapeldreef 75 B- 3001 Leuven, Belgium Tel +32 16 28 18 80 Fax +32 16 28 16 37 Email:
[email protected] Freescale Media Contacts: North America: Stephanie Sobotik Freescale Semiconductor IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 75 of 77
+1 (512) 895-3836
[email protected] Europe, Middle East and Africa: Regina Cirmonova Freescale Semiconductor +41 22 799 1258
[email protected] Asia Pacific: Gloria Shiu (Hong Kong) Freescale Semiconductor +852-2666-8237
[email protected] Koichi Yoshimura (Japan) Freescale Semiconductor +81-3-3280-8672
[email protected] Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004.
News Release 2:
Samsung secures the first strategic research partnership with IMEC on future mobile terminals
Leuven, Belgium --- January 26, 2005 --- IMEC, Europe's leading independent nanoelectronics and nanotechnology research institute, has announced that Samsung Electronics Co. LTD., the world's leading information and communications technologies (ICT) company, has become the first long-term strategic partner within IMEC's M4 (MultiMode Multi-Media) research program, which focuses on the mobile terminal for the future ubiquitous network era. Under this agreement, Samsung and IMEC intend to develop key technologies for its future portable communication products. Future generation mobile terminals will start to incorporate ubiquitous network functionality, by efficiently dealing with a multitude of communication modes and various multimedia applications. Further down the road, these terminals will also need adaptive behavior to intelligently manage the computational resources that will be distributed and shared across the environing systems. IMEC's M4 integrated research platform aims to resolve the fundamental technological issues for future mobile terminals, allowing the true ubiquitous network environment to become a reality. Complexity, cost, power consumption, high throughput at low latency, and flexibility are the five primary hurdles in developing a mobile terminal. To overcome these hurdles, IMEC and Samsung have outlined a number of domains of innovation, which are targeted by the M4 IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 76 of 77
technology programs. M4 strategic program partners join the full frame of technology programs and closely collaborate with IMEC's cross-disciplinary team of more than 100 researchers. The M4 roadmap is fine-tuned with the strategic partners, ensuring that research targets are strongly tuned to industrial applications, which is a major advantage for the strategic partners. In addition, the integrated approach guarantees the compatibility of the different technology solutions, and enables efficient transfer of the research results into industrial applications. In addition to Samsung's strategic partnership with IMEC, IMEC also has a running relationship with several technology partners including Freescale, Infineon and Xilinx, collaborating within one of the M4 technology programs. The highest level of collaboration is at the M4 program level, followed by collaboration on technology level (collaboration on one or more of the subordinate technologies of M4). Both the strategic and the technology partners gain benefits from IMEC's business model, which allows companies to reduce research costs and risks while sharing intellectual property. By working cross-industry with a wide range of partners within the M4 program context, IMEC will ensure creation and continuity of a challenging M4 program research roadmap to address the key challenges within the mobile multimedia area. “We believe IMEC's outstanding research capability would match Samsung's need well. Through this strategic partnership, both Samsung and IMEC can achieve mutual benefit in preparing for the future,” said Dr. Joonki Kim, Head of Digital Research Center of Samsung Advanced Institute of Technology. “We are very pleased that our successful relationship with Samsung, which started in 2003 with Samsung joining our core sub-45nm CMOS research platform, has now resulted in this M4 strategic partnership,” said Prof. Gilbert Declerck, President and CEO of IMEC. “Such long-term collaborations with industry leaders prove the industrial relevance of our research programs.” ---ends--Note to editors: About IMEC IMEC is a world-leading independent research center in nanoelectronics and nanotechnology. Its research focuses on the next generations of chips and systems, and on the enabling technologies for ambient intelligence. IMEC’s research bridges the gap between fundamental research at universities and technology development in industry. Its unique balance of processing and system know-how, intellectual property portfolio, state-of-the-art infrastructure and its strong network of companies, universities and research institutes worldwide, position IMEC as a key partner with which to develop and improve technologies for future systems. IMEC is headquartered in Leuven, Belgium and has representatives in the US, China and Japan. Its staff of more than 1300 people includes over 380 industrial residents and guest researchers. In 2003, its revenues were EUR 145 million. Further information on IMEC can be found at www.imec.be. IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
Deliverable D39
Page 77 of 77
About Samsung Electronics SAMSUNG ELECTRONICS Co. LTD. is a global leader in semiconductor, telecommunication, and digital convergence technology. SAMSUNG ELECTRONICS employs approximately 64,000 people in 89 offices in 47 countries. Being the largest producer of memory chips, smart card chips, disdplay driver ICs, TFT-LCDs, CDMA mobile phones, monitor and VCR’s, SAMSUNG ELECTRONICS consists of four main business units: Digital Media Network, Device Solution Network, Telecommunications Network, and Digital Appliance Network Businesses. For more information, please visit the web site, http://samsungelectronics.com For more information: IMEC Katrien Marent Tel +32 16 28 18 80 Email:
[email protected] Samsung Advanced Institute of Technology Manjo Han Tel: 82-31-280-9082 Email:
[email protected] Eunie Dong Tel: 82-31-280-9035 Email:
[email protected]
IST-2001-34379/WP7/D39/ICOM/R
AMDREL Consortium
