Transcript
7D-4s
A 10Gb/s Transmitter with Multi-Tap FIR Pre-Emphasis in 0.18µm CMOS Technology Shoujun Wang, Yuming Tao
Miao Li, Tad Kwasniewski
Ottawa IC Development ALTERA CO. Ottawa, ON., Canada K2K3C9 Tel : 613-591-6767 Fax : 613-591-6701 E-mail : {sjwang, ytao}@altera.com
Department of Electronics Carleton University Ottawa, ON., Canada K1S5B6 Tel: 613-520-2600 ext. 1825 Fax: 613-520-5708 E-mail : {mili, tak}@doe.carleton.ca
Abstract－ A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.18µm CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. HSPICE simulation results of a 5-tap FIR transmitter show that the closed eye over a 34” FR4 backplane can be opened to 0.72UI at 10Gb/s. The power dissipation of the transmitter is 50mW at a 1.8V supply.
Fig. 1 Configuration of a transceiver interface and backplane channel This paper deals with the FIR pre-emphasis design. The mathematical expression for the symbol-spaced FIR filter is:
y(n) =
I. INTRODUCTION
M
∑c x(n − i)
i =−N
High-speed serial interfaces, which significantly reduce I/O pin count and increase maximum bandwidth per pin, are replacing conventional low-speed parallel buses for backplane communications. ISI is the major factor limiting the maximum distance and data rate of backplane data transmission. Using a symbol-spaced FIR filter for preemphasis at transmit side is a popular technique for counteracting ISI [1,2,3]. Traditionally, the symbol-spaced data for a multi-tap FIR filter is generated by employing a single-edge-triggered D flip-flop (DFF) with full-rate clock retiming. The full-rate clock, which is two times the data fundamental frequency, could reach the speed limitation of a given technology. In this paper, a half-rate clock retiming circuit for generating the symbol-space data is proposed. A 10Gb/s CML transmitter with 5-tap FIR pre-emphasis has been implemented in 0.18µm CMOS technology. The design of symbol-spaced FIR pre-emphasis is presented in Section 2. The design of half-rate retiming circuit is given in Section 3. HSPICE simulation results in Section 4 verify the circuit function and Section 5 provides conclusions.
(1)
where ci are tap coefficients, N is the number of pre-taps, M is the number of post-taps, and c0 is the main or reference tap. The FIR pre-emphasis design usually involves the determination of the required number of taps and the optimization of tap coefficients. A MATLAB program has been developed to automate the FIR pre-emphasis design [4]. For a given backplane channel, (e.g., simulated or measured S-parameters), the MATLAB program gives the optimized tap coefficients, including the sign and absolute value.
Fig. 2 Transmitter architecture Figure 2 shows the proposed transmitter architecture, which consists of multi-tap FIR pre-emphasis driver, predriver with XOR gate for sign control and half-rate retiming circuit (detailed in next section). Multi-tap FIR pre-emphasis can be implemented in a CML driver, as shown in Figure 3(a). Here a 5-tap FIR implementation is given, the tap coefficients are controlled by current sources. The sign of the tap coefficients is controlled by CML XOR gate, as shown in Figure 3(b), by exchanging the polarity of data outputs. The pre-driver is also based on CML structure to achieve the highest speed.
II. FIR PRE-EMPHASIS DESIGN Figure 1 shows the transceiver interface, where a transmitter at near-end transmits a signal through a backplane channel and a receiver at far-end receives the signal. The transmitter consists of the data retiming and preemphasis circuits, while the receiver consists of the equalizer and clock and data recovery circuits. Typically, the backplane channel consists of a transmit daughter card, a backplane, a receive daughter card and connectors. 0-7803-8736-8/05/$20.00 ©2005 IEEE.
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(b) (a)
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Fig. 4 (a) Half-rate retiming circuit, (b) structure of DETFF, (c) D-latch, (d) MUX (b)
The half-rate retiming circuit is realized by breaking the DETFF structure as presented in [5] and by properly interleaving the clock phases. The output of the DFF of the first DETFF directly goes to the input of the DFF of the next DETFF. The clock phases for cascaded DFFs and MUXs are interleaved in such a way to generate symbol-spaced data sequences. Figure 5(a) shows the five symbol-spaced pseudorandom bit sequence (PRBS) of 215 at 10Gb/s generated using a 5GHz clock, where the signal rising/falling time is about 0.4UI (1UI =1 unit interval= 1 symbol period).
Fig. 3 (a) 5-tap FIR pre-emphasis driver, (b) XOR gate for sign control The tap coefficients are the normalized currents with respect to the main tap current. The expression is:
| Ci |=
I tapi
(2)
I tap0
A digital-to-analog converter (DAC) can be used to control the current sources. For example, with an 8-bit DAC, the resolution can be as high as 1/0.004.
Symbol-spaced data sequences D0
1 0
III. HALF-RATE RETIMING CIRCUIT DESIGN
D1
The traditional data retiming circuit requires a full-rate clock with single-edge-triggered DFF to generate symbolspaced data sequences for the FIR filter. To alleviate the speed requirement of the full-rate clock, a half-rate retiming circuit is proposed. The structure of the proposed half-rate retiming circuit is shown in Figure 4(a). It is based on the double-edgetriggered flip-flops (DETFF) [5]. Two DFFs operating on opposite clock phases along with a multiplexer (MUX) form a DETFF, as shown in Figure 4(b). Each DFF consists of two D-latches in a master-slave configuration. The structure of the CML based D-latch and MUX are shown in Figure 4(c) and 4(d), respectively.
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(a) Superimposed eye diagrams
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(b) Fig. 5 (a) Five symbol-spaced data sequences at 10Gb/s, and (b) superimposed eye diagrams 680
The potential jitter contribution in FIR circuit design comes from the jitter of the retiming clock and the timing skew of symbol-spaced data. Superimposing the eye diagrams of the five symbol-spaced PRBS of 215 shows that the total jitter is about 7ps, as shown in Figure 5(b). With half-rate clock retiming, another jitter contribution comes from the duty cycle distortion of the clock. Duty cycle control circuits may be necessary for high-speed serial communications [6, 7]. Compared with full-rate clock retiming circuit, the half-rate retiming circuit achieves higher speed for a given technology.
Eye diagram at near end of channel 0.5 0.4 0.3
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IV. HSPICE SIMULATION RESULTS
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(a) A CML transmitter with 5-tap FIR pre-emphasis described above has been designed in 0.18µm CMOS technology. The near-end eye diagram without pre-emphasis is shown in Figure 6(a), at a data rate of 10Gb/s. The far-end eye diagram of the 34” FR4 backplane is shown in Figure 6(b). It can be seen that the eye is totally closed both horizontally and vertically.
Eye diagram at far end of channel 0.08 0.06
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Fig. 7 Eye diagram at (a) near-end, and (b) far-end of a 34” FR4 backplane channel with pre-emphasis at 10Gb/s
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Another example is given at a data rate of 6.25Gb/s. Without pre-emphasis, the eye diagram at far-end of channel is also totally closed. With the 5-tap FIR filter pre-emphasis employed, the eye diagrams at near-end and far-end of a 34” FR4 backplane are shown in Figure 8(a) and 8(b) respectively. The horizontal eye opening is approximately 0.88UI.
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Fig. 6 Eye diagrams at (a) near-end, and (b) far-end of a 34” FR4 backplane channel without pre-emphasis at 10Gb/s
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The near-end eye diagram with pre-emphasis is shown in Figure 7(a). The corresponding far-end eye diagram is shown in Figure 7(b). The horizontal eye opening at the farend of the channel is measured at 0.72UI.
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and M. Yotsuyanagi, “A CMOS 50% duty cycle repeater using complementary phase blending”, VLSI Circuits Symp., pp. 48-49, June 2000.
Eye diagram at far-end of channel 0.15
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[7] T. Gawa and K. Taniguchi, “A 50% duty-cycle correction circuit for PLL output”, Proc. ISCAS 2002, pp. IV-21-IV-24, May 2002.
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(b) Fig. 8 Eye diagram at (a) near-end, and (b) far-end of a 34” FR4 backplane channel with pre-emphasis at 6.25Gb/s
V. CONCLUSIONS A CML transmitter with 5-tap FIR pre-emphasis has been implemented in 0.18µm CMOS technology. The tap coefficients, including the sign, are implemented with full programmability. With the proposed half-rate clock retiming circuit, 10Gb/s operation has been demonstrated over a 34” FR4 backplane, performance exceeding that reported previously in the literature. The power dissipation of the transmitter is 50mW at a 1.8V supply.
ACKNOWLEDGEMENTS Authors would like to thank Peter Noel and Jing Chen for their editorial and technical contributions.
REFERENCES [1] J. Zerbe, et al., “Equalization and clock recovery for a 2.5-10Gbs 2-PAM/4-PAM backplane transceiver cell,” J. Solid-State Circuits, vol. 38, pp. 2121-2130, Dec. 2003. [2] C-H Lin, C-H Wang, and S-J Jou, “5 Gb/s serial link transmitter with pre-emphasis”, Proc. ASP-DAC 2003, pp. 795-800, Jan. 2003. [3] R. Farjad-Rad, C.-K.K. Yang, M.A. Horowitz, and T.H. Lee, “A 0.4-µm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter”, J. Solid-State Circuits, vol. 34, pp. 580-585, May 1999. [4] M. Li, S. Wang, Y. Tao, and T. Kwasniewski, “FIR Filter Optimization as Pre-Emphasis of High-Speed Backplane Data Transmission”, Electronics Letters, vol. 40, pp. 912-913, July 2004. [5] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector”, J. Solid-state Circuits, vol. 38, pp. 13-21, Jan. 2003. [6] K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, 682
