Transcript
Data Sheet
100 MHz to 4000 MHz RF/IF Digitally Controlled VGA ADL5243
FEATURES
GENERAL DESCRIPTION
Operating frequency from 100 MHz to 4000 MHz Digitally controlled VGA with serial and parallel interfaces 6-bit, 0.5 dB digital step attenuator 31.5 dB gain control range with ±0.25 dB step accuracy Gain Block Amplifier 1 Gain: 19.2 dB at 2140 MHz OIP3: 40.2 dBm at 2140 MHz P1dB: 19.8 dBm at 2140 MHz Noise figure: 2.9 dB at 2140 MHz ¼ W Driver Amplifier 2 Gain: 14.2 dB at 2140 MHz OIP3: 41.1 dBm at 2140 MHz P1dB: 26.0 dBm at 2140 MHz Noise figure: 3.7 dB at 2140 MHz Gain block, DSA, or ¼ W driver amplifier can be first Low quiescent current of 175 mA The companion ADL5240 integrates a gain block with DSA
The ADL5243 is a high performance, digitally controlled variable gain amplifier operating from 100 MHz to 4000 MHz. The VGA integrates two high performance amplifiers and a digital step attenuator (DSA). Amplifier 1 (AMP1) is an internally matched gain block amplifier with 20 dB gain, and Amplifier 2 (AMP2) is a broadband ¼ W driver amplifier that requires very few external tuning components. The DSA is 6-bit with a 31.5 dB gain control range, 0.5 dB steps, and ±0.25 dB step accuracy. The attenuation of the DSA can be controlled using a serial or parallel interface. The gain block and DSA are internally matched to 50 Ω at their inputs and outputs, and all three internal devices are separately biased. The separate bias allows all or part of the ADL5243 to be used, which allows for easy reuse throughout a design. The pinout of the ADL5243 also enables the gain block, DSA, or ¼ W driver amplifier to be first, giving the VGA maximum flexibility in a signal chain.
APPLICATIONS
The ADL5243 consumes 175 mA and operates off a single supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP and is fully specified for operation from −40°C to +85°C. A fully populated evaluation board is available.
Wireless infrastructure Automated test equipment RF/IF gain control
SEL
D0/CLK
D1/DATA
D2/LE
D3
D4
D5
D6
FUNCTIONAL BLOCK DIAGRAM
32
31
30
29
28
27
26
25
VDD 1
24
VDD
NC 2
23
NC
NC 3
22
NC
21
DSAOUT
20
NC
19
AMP2IN
18
NC
17
NC
SERIAL/PARALLEL INTERFACE
DSAIN 4 0.5dB
1dB
2dB
4dB
8dB
16dB
NC 5
AMP1OUT/VCC 6
NC 7
AMP2
AMP1
14
15
16
VBIAS
NC
13
AMP2OUT/VCC2
AMP1IN
12
NC
11
NC
10
NC
9
NC
NC 8
09431-001
ADL5243
Figure 1. Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADL5243
Data Sheet
TABLE OF CONTENTS Features .............................................................................................. 1
Basic Layout Connections ......................................................... 22
Applications ....................................................................................... 1
SPI Timing................................................................................... 23
General Description ......................................................................... 1
ADL5243 Amplifier 2 Matching .............................................. 25
Functional Block Diagram .............................................................. 1
ADL5243 Loop Performance .................................................... 31
Revision History ............................................................................... 2
Proper Driving Level for the Optimum ACLR ...................... 32
Specifications..................................................................................... 3
Thermal Considerations............................................................ 32
Absolute Maximum Ratings.......................................................... 10 ESD Caution ................................................................................ 10
Soldering Information and Recommended PCB Land Pattern ....................................................................................................... 32
Pin Configuration and Function Descriptions ........................... 11
Evaluation Board ............................................................................ 33
Typical Performance Characteristics ........................................... 12
Outline Dimensions ....................................................................... 38
Applications Information .............................................................. 22
Ordering Guide .......................................................................... 38
REVISION HISTORY 8/12—Rev. A to Rev. B Changes to General Description Section ....................................... 1 Changes to Table 1 ............................................................................. 3 Changes to Table 3 ...........................................................................11 Changes to Figure 3 .........................................................................12 Changes to Figure 33 .......................................................................17 Added Figure 47 and Figure 49, Renumbered Sequentially ......19 Change to Figure 58 ........................................................................22 Changes to ADL5243 Amplifier 2 Matching Section, Table 8, and Table 9 ........................................................................................25 Added Figure 61 and Figure 62......................................................26 Changes to Figure 63 and Figure 64 ..............................................27 Added Figure 65; Changes to Figure 66........................................28 Added Figure 67; Changes to Figure 68........................................29 Added Figure 69...............................................................................30
Changes to ADL5243 Loop Performance Section; Added Figure 71, Figure 72, and Table 10, Renumbered Sequentially....... 31 Added Proper Driving Level for the Optimum ACLR Section and Figure 73.................................................................................... 32 Changes to Evaluation Board Section and Table 11 ................... 33 Changes to Figure 75....................................................................... 34 Added Figure 76 .............................................................................. 35 Changes to Figure 77 and Figure 78.............................................. 36 Added Figure 79 .............................................................................. 37 8/11—Rev. 0 to Rev. A Changes to Features Section ............................................................1 7/11—Revision 0: Initial Version
Rev. B | Page 2 of 40
Data Sheet
ADL5243
SPECIFICATIONS VDD = 5 V, VCC = 5 V, VCC2 = 5 V, TA = 25°C. Table 1. Parameter OVERALL FUNCTION Frequency Range AMPLIFIER 1 FREQUENCY = 150 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 450 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 748 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 943 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure
Conditions
Min
Typ
100
Max
Unit
4000
MHz
Using the AMP1IN and AMP1OUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 3 dBm/tone
18.2 ±0.97 ±0.07 ±0.03 −10.4 −8.2 18.4 29.5 2.8
dB dB dB dB dB dB dBm dBm dB
20.6 ±0.10 ±0.36 ±0.01 −17.8 −16.5 19.5 38.4 2.8
dB dB dB dB dB dB dBm dBm dB
20.8 ±0.02 ±0.32 ±0.01 −22.0 −21.6 19.6 39.6 2.7
dB dB dB dB dB dB dBm dBm dB
Using the AMP1IN and AMP1OUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 3 dBm/tone Using the AMP1IN and AMP1OUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 3 dBm/tone Using the AMP1IN and AMP1OUT pins 19.0 ±18 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 18.5 ∆f = 1 MHz, POUT = 3 dBm/tone
Rev. B | Page 3 of 40
20.3 ±0.01 ±0.28 ±0.02 −24.0 −21.5 19.9 40.4 2.7
22.0
dB dB dB dB dB dB dBm dBm dB
ADL5243 Parameter AMPLIFIER 1 FREQUENCY = 1960 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 2140 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 2630 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 3600 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 2 FREQUENCY = 150 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure
Data Sheet Conditions Using the AMP1IN and AMP1OUT pins
Min
Typ
Max
19.5 ±0.02 ±0.26 ±0.04 −13.5 −12.4 19.6 40.4 2.9
±30 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 3 dBm/tone
Unit dB dB dB dB dB dB dBm dBm dB
Using the AMP1IN and AMP1OUT pins 17.5 ±30 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 17.5 ∆f = 1 MHz, POUT = 3 dBm/tone
19.2 ±0.02 ±0.26 ±0.05 −13.3 −12.2 19.8 40.2 2.9
21.5
dB dB dB dB dB dB dBm dBm dB
19.0 ±0.03 ±0.22 ±0.05 −17.3 −12.3 19.5 39.5 2.9
21.5
dB dB dB dB dB dB dBm dBm dB
Using the AMP1IN and AMP1OUT pins 17.5 ±60 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 17.5 ∆f = 1 MHz, POUT = 3 dBm/tone Using the AMP1IN and AMP1OUT pins ±100 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 3 dBm/tone
18.0 ±0.10 ±0.05 ±0.12 −30.7 −9.0 18.0 34.6 3.3
dB dB dB dB dB dB dBm dBm dB
20.8 ±1.1 ±0.3 ±0.03 −11.0 −6.5 22.8 40.6 6.3
dB dB dB dB dB dB dBm dBm dB
Using the AMP2IN and AMP2OUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone
Rev. B | Page 4 of 40
Data Sheet Parameter AMPLIFIER 2 FREQUENCY = 450 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 2 FREQUENCY = 748 MHz Gain vs. Frequency Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 2 FREQUENCY = 943 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 2 FREQUENCY = 1960 MHz Gain vs. Frequency Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 2 FREQUENCY = 2140 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure
ADL5243 Conditions Using the AMP2IN and AMP2OUT pins
Min
±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone
Typ
Max
Unit
16.4 ±0.5 ±0.35 ±0.07 −9.0 −8.0 23.2 38.1 6.2
dB dB dB dB dB dB dBm dBm dB
17.5 ±0.14 −14 −8.6 24.7 41.5 5.6
dB dB dB dB dBm dBm dB
16.5 ±0.05 ±0.39 ±0.10 −11.2 −8.1 25.0 43.3 5.3
dB dB dB dB dB dB dBm dBm dB
14.9 ±0.15 −14 −7.0 26.0 39.9 3.73
dB dB dB dB dBm dBm dB
Using the AMP2IN and AMP2OUT pins ±50 MHz S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone Using the AMP2IN and AMP2OUT pins ±18 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone Using the AMP2IN and AMP2OUT pins ±30 MHz S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone Using the AMP2IN and AMP2OUT pins 13.0 ±30 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone
Rev. B | Page 5 of 40
14.2 ±0.03 ±0.50 ±0.09 −10.7 −8.1 26.0 41.1 3.7
15.5
dB dB dB dB dB dB dBm dBm dB
ADL5243 Parameter AMPLIFIER 2 FREQUENCY = 2630 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 2 FREQUENCY = 3600 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure DSA FREQUENCY = 150 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept DSA FREQUENCY = 450 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept DSA FREQUENCY = 748 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept
Data Sheet Conditions Using the AMP2IN and AMP2OUT pins ±60 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone
Min
Typ
Max
Unit
13.0 ±0.13 ±0.56 ±0.09 −9.4 −8.3 24.5 40.4 4.1
dB dB dB dB dB dB dBm dBm dB
12.3 ±1.23 ±1.05 ±0.07 −15.0 −11.0 26.2 36.2 5.5
dB dB dB dB dB dB dBm dBm dB
−1.5 ±0.12 ±0.10 28.8 ±0.18 ±1.35 −13.5 −13.3 48.2
dB dB dB dB dB dB dB dB dBm
−1.4 ±0.02 ±0.12 30.7 ±0.14 ±0.39 −17.7 −17.4 44.0
dB dB dB dB dB dB dB dB dBm
−1.5 ±0.02 ±0.12 30.9 ±0.15 ±0.30 −17.1 −17.1 44.0
dB dB dB dB dB dB dB dB dBm
Using the AMP2IN and AMP2OUT pins ±200 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
∆f = 1 MHz, POUT = 5 dBm/tone
Rev. B | Page 6 of 40
Data Sheet Parameter DSA FREQUENCY = 943 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 1960 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 2140 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 2630 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept
ADL5243 Conditions Using the DSAIN and DSAOUT pins, minimum attenuation ±18 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±30 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±30 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±60 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
∆f = 1 MHz, POUT = 5 dBm/tone
Rev. B | Page 7 of 40
Min
Typ
Max
Unit
−1.6 ±0.01 ±0.13 30.9 ±0.15 ±0.28 −16.0 −15.9 30.5 50.7
dB dB dB dB dB dB dB dB dBm dBm
−2.5 ±0.04 ±0.18 30.8 ±0.15 ±0.35 −10.3 −9.6 31.5 49.6
dB dB dB dB dB dB dB dB dBm dBm
−2.6 ±0.02 ±0.19 30.9 ±0.13 ±0.32 −9.8 −9.3 31.5 49.6
dB dB dB dB dB dB dB dB dBm dBm
−2.8 ±0.02 ±0.21 31.2 ±0.18 ±0.24 −10.0 −9.6 31.5 48.3
dB dB dB dB dB dB dB dB dBm dBm
ADL5243 Parameter DSA FREQUENCY = 3600 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA Gain Settling Minimum Attenuation to Maximum Attenuation Maximum Attenuation to Minimum Attenuation LOOP FREQUENCY = 150 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure LOOP FREQUENCY = 450 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure LOOP FREQUENCY = 943 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure LOOP FREQUENCY = 2140 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure
Data Sheet Conditions Using the DSAIN and DSAOUT pins, minimum attenuation ±100 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins
Min
Typ
Max
Unit
−3.0 ±0.02 ±0.23 31.7 ±0.38 ±0.35 −12.3 −11.7 31.0 46.2
dB dB dB dB dB dB dB dB dBm dBm
36
ns
36
ns
37.4 ±0.1 28.0 −10.0 −7.0 22.5 38.5 3.0
dB dB dB dB dB dBm dBm dB
35.8 ±0.43 31.0 −12.5 −6.4 23.1 37.6 3.1
dB dB dB dB dB dBm dBm dB
34.0 ±0.10 29.3 −14.2 −10.1 25.1 42.8 2.9
dB dB dB dB dB dBm dBm dB
31.3 ±0.03 32.5 −9.3 −5.4 25.3 40.0 3.1
dB dB dB dB dB dBm dBm dB
AMP1 – DSA – AMP2, DSA at minimum attenuation ±50 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone AMP1 – DSA – AMP2, DSA at minimum attenuation ±50 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone AMP1–DSA–AMP2, DSA at minimum attenuation ±18 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone AMP1 – DSA – AMP2, DSA at minimum attenuation ±30 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone
Rev. B | Page 8 of 40
Data Sheet Parameter LOOP FREQUENCY = 2630 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure LOOP FREQUENCY = 3600 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN POWER SUPPLIES Voltage Supply Current
ADL5243 Conditions AMP1 – DSA – AMP2, DSA at minimum attenuation
Min
±60 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone
Typ
Max
Unit
29.5 ±0.56 30.0 −12.6 −5.8 24.6 39.3 3.1
dB dB dB dB dB dBm dBm dB
26.5 ±1.3 33.0 −8.0 −8.0 24.7 36.0 3.7
dB dB dB dB dB dBm dBm dB
AMP1 – DSA – AMP2, DSA at minimum attenuation ±200 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone CLK, DATA, LE, SEL, D0~D6 2.5 0.8 0.1 1.5 4.75 AMP1 AMP2 DSA
Rev. B | Page 9 of 40
5.0 89 86 0.5
5.25 120 120
V V µA pF V mA mA mA
ADL5243
Data Sheet
ABSOLUTE MAXIMUM RATINGS ESD CAUTION
Table 2. Parameter Supply Voltage (VDD, VCC, VCC2) Input Power AMP1IN AMP2IN (50 Ω Impedance) DSAIN Internal Power Dissipation θJA (Exposed Paddle Soldered Down) θJC (Exposed Paddle) Maximum Junction Temperature Lead Temperature (Soldering, 60 sec) Operating Temperature Range Storage Temperature Range
Rating 6.5 V 16 dBm 20 dBm 30 dBm 1.0 W 34.8°C/W 6.2°C/W 150°C 240°C −40°C to +85°C −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. B | Page 10 of 40
Data Sheet
ADL5243
32 31 30 29 28 27 26 25
SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
ADL5243 TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
VDD NC NC DSAOUT NC AMP2IN NC NC
NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
09431-002
NC AMP1IN NC NC NC NC AMP2OUT/VCC2 VBIAS
9 10 11 12 13 14 15 16
VDD NC NC DSAIN NC AMP1OUT/VCC NC NC
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. 1, 24 2, 3, 5, 7, 8, 9, 11, 12, 13, 14, 17, 18, 20, 22, 23 4 6
Mnemonic VDD NC
Description Supply Voltage for DSA. Connect this pin to a 5 V supply. No Connect. Do not connect to this pin.
DSAIN AMP1OUT/VCC
10 15
AMP1IN AMP2OUT/VCC2
16 19 21 25 26 27 28 29 30 31 32
VBIAS AMP2IN DSAOUT D6 D5 D4 D3 D2/LE D1/DATA D0/CLK SEL
RF Input to DSA. RF Output from Amplifier 1/Supply Voltage for Amplifier 1. Bias to Gain Block Amplifier 1 is provided through a choke to this pin when connected to VCC. RF Input to Gain Block Amplifier 1. RF Output from Amplifier 2/Supply Voltage for Amplifier 2. Bias to Driver Amplifier 2 is provided through a choke to this pin when connected to VCC2. Bias for Driver Amplifier 2. RF Input to Amplifier 2. RF Output from DSA. Data Bit in Parallel Mode (LSB). Connect to supply in serial mode. Data Bit in Parallel Mode. Connect to ground in serial mode. Data Bit in Parallel Mode. Connect to ground in serial mode. Data Bit in Parallel Mode. Connect to ground in serial mode. Data Bit in Parallel Mode/Latch Enable in Serial Mode. Data Bit in Parallel Mode (MSB)/Data in Serial Mode. Connect this pin to ground in parallel mode. This pin functions as a clock in serial mode. Select Pin. For parallel mode operation , connect this pin to the supply. For serial mode operation, connect this pin to ground. Exposed Paddle. The exposed paddle must be connected to ground.
EPAD
Rev. B | Page 11 of 40
ADL5243
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS 28
45
26
40
24
35
22
30
20
25
18
20
OIP3 40 35
P1dB (dBm)
GAIN 25 20 15
P1dB 10
0
0.4
0.8
1.2
1.6
+85°C +25°C –40°C
16
NOISE FIGURE
2.0
2.4
2.8
3.2
3.6
4.0
FREQUENCY (GHz)
0
0.4
0.8
1.2
1.6
2.0
2.8
3.2
FREQUENCY (GHz)
42
21.5
40
21.0
38
943MHz
450MHz 748MHz
36 1960MHz
20.5
2140MHz
34
OIP3 (dBm)
–40°C
19.5
+25°C
2630MHz
32 30
3600MHz
28
+85°C
18.5
2.4
Figure 6. AMP1: OIP3 at POUT = 3 dBm/Tone and P1dB vs. Frequency and Temperature
22.0
19.0
10 3.6
14
Figure 3. AMP1: Gain, P1dB, OIP3 at POUT = 3 dBm/Tone and Noise Figure vs. Frequency
20.0
15
09431-006
5 0
150MHz 26
18.0
24
17.5
22
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
FREQUENCY (GHz)
20 –4
09431-004
17.0
–2
0
2
4
6
8
10
12
14
16
3.6
4.0
POUT PER TONE (dBm)
09431-007
GAIN (dB)
OIP3 (dBm)
30
09431-003
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
45
Figure 7. AMP1: OIP3 vs. POUT and Frequency
Figure 4. AMP1: Gain vs. Frequency and Temperature 5.0
0 –5
4.5
S22
–15
NOISE FIGURE (dB)
S-PARAMETERS (dB)
–10
S11 –20
S12 –25 –30 –35
4.0
+85°C 3.5 3.0
+25°C
2.5
–40°C
–40 2.0
0.5
0.9
1.3
1.7
2.1
2.5
FREQUENCY (GHz)
2.9
3.3
3.7
4.1
Figure 5. AMP1: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
Rev. B | Page 12 of 40
1.5 0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
FREQUENCY (GHz)
Figure 8. AMP1: Noise Figure vs. Frequency and Temperature
09431-008
–50 0.1
09431-005
–45
Data Sheet
ADL5243 27.0
45
26.5
43
26.0
41
25.5
39
25.0
37
40 35
P1dB (dBm)
30
P1dB
25 20
GAIN 15 10
24.5
NF
5 0 0.925
0.930
0.935
0.940
0.945
0.950
0.955
0.960
0.965
FREQUENCY (GHz)
24.0 0.925
0.930
0.935
0.940
0.945
0.950
0.955
0.960
33 0.965
FREQUENCY (GHz)
Figure 9. AMP2–943 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency
Figure 12. AMP2–943 MHz: OIP3 at POUT = 5 dBm/Tone and P1dB vs. Frequency and Temperature
18.0
45 44
17.5
961MHz 43
925MHz
OIP3 (dBm)
–40°C
17.0
GAIN (dB)
35
+85°C +25°C –40°C
09431-012
45
OIP3 (dBm)
OIP3
09431-009
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
50
+25°C 16.5
+85°C 16.0
42
943MHz
41 40 39
15.5
0.930
0.935
0.940
0.945
0.950
0.955
0.960
0.965
FREQUENCY (GHz)
37 –4
09431-010
7.5
–5
7.0
S22
4
6
8
10
12
14
16
18
6.5
–10
NOISE FIGURE (dB)
S-PARAMETERS (dB)
2
Figure 13. AMP2–943 MHz: OIP3 vs. POUT and Frequency
0
S11
–20 –25
+85°C 6.0 5.5
+25°C
5.0
–40°C –40°C 4.5
S12 –30
4.0
0.85
0.90
0.95
1.00
FREQUENCY (GHz)
1.05
1.10
3.5 0.80
09431-011
–35 0.80
0
POUT PER TONE (dBm)
Figure 10. AMP2–943 MHz: Gain vs. Frequency and Temperature
–15
–2
Figure 11. AMP2–943 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
0.83
0.86
0.89
0.92
0.95
0.98
FREQUENCY (GHz)
1.01
1.04
1.07
1.10
09431-014
15.0 0.925
09431-013
38
Figure 14. AMP2–943 MHz: Noise Figure vs. Frequency and Temperature
Rev. B | Page 13 of 40
ADL5243
Data Sheet 28.0
43
27.5
41
27.0
39
26.5
37
26.0
35
OIP3 40
30
P1dB (dBm)
P1dB 25 20
GAIN
15
OIP3 (dBm)
35
10
+85°C +25°C –40°C
0 2.11
2.12
2.13
2.14
2.15
2.16
2.17
FREQUENCY (GHz)
Figure 15. AMP2–2140 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency
25.0 2.11
2.12
2.13
33
2.14
2.15
31 2.17
2.16
09431-018
25.5
NF
5
09431-015
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
45
FREQUENCY (GHz)
Figure 18. AMP2–2140 MHz: OIP3 at POUT = 5 dBm/Tone and P1dB vs. Frequency and Temperature
16.0
42
15.5
41
14.5
+25°C
14.0
+85°C
40
38
13.5
37
13.0
36
12.5
35
12.0 2.11
2.12
2.13
2.14
2.15
2.16
2.17
FREQUENCY (GHz)
2.14GHz
39
34 –6
–4
–2
0
2
4
6
8
10
12
14
16
18
20
22
POUT PER TONE (dBm)
09431-019
–40°C
OIP3 (dBm)
15.0
09431-016
GAIN (dB)
2.17GHz 2.11GHz
Figure 19. AMP2–2140 MHz: OIP3 vs. POUT and Frequency
Figure 16. AMP2–2140 MHz: Gain vs. Frequency and Temperature 5.5
0
5.0
–5
S22
–15
–20
4.0
+25°C 3.5
–40°C
3.0
S12 –25
2.5
2.05
2.10
2.15
2.20
FREQUENCY (GHz)
2.25
2.30
2.0 2.00
09431-017
–30 2.00
+85°C
4.5
Figure 17. AMP2–2140 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
2.03
2.06
2.09
2.12
2.15
2.18
FREQUENCY (GHz)
2.21
2.24
2.27
2.30
09431-020
–10
NOISE FIGURE (dB)
S-PARAMETERS (dB)
S11
Figure 20. AMP2–2140 MHz: Noise Figure vs. Frequency and Temperature
Rev. B | Page 14 of 40
ADL5243 OIP3
40 35
P1dB (dBm)
30
P1dB
25 20
42.0
27.5
41.5
27.0
41.0
26.5
40.5
26.0
40.0
25.5
39.5
25.0
39.0
24.5
38.5 38.0
24.0
NF
5
2.59
+85°C +25°C –40°C
23.5
2.61
2.63
2.65
2.67
2.69
FREQUENCY (GHz)
Figure 21. AMP2–2630 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency
23.0 2.57
2.59
2.61
2.65
37.0 2.69
2.67
FREQUENCY (GHz)
42 2.69GHz
41
14.5
2.63GHz
40 39
–40°C
2.57GHz
38
OIP3 (dBm)
13.5
GAIN (dB)
2.63
Figure 24. AMP2–2630 MHz: OIP3 at POUT = 5 dBm/Tone and P1dB vs. Frequency and Temperature
15.0
14.0
37.5 09431-024
10
0 2.57
28.0
GAIN
15
09431-021
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
45
OIP3 (dBm)
Data Sheet
+25°C
13.0 +85°C
12.5
37 36 35 34 33
12.0
32
11.5
2.61
2.63
2.65
2.67
2.69
FREQUENCY (GHz)
30 –6
–2
0
2
4
6
8
10
12
14
16
18
20
22
POUT PER TONE (dBm)
Figure 22. AMP2–2630 MHz: Gain vs. Frequency and Temperature
Figure 25. AMP2–2630 MHz: OIP3 vs. POUT and Frequency
0
6.0 5.5
–5
S11
5.0
NOISE FIGURE (dB)
S-PARAMETERS (dB)
–4
09431-025
2.59
09431-022
11.0 2.57
31
–10
S22 –15
–20
S12
+85°C
4.5
+25°C
4.0 3.5
–40°C 3.0
–25
2.55
2.60
2.65
2.70
FREQUENCY (GHz)
2.75
2.80
2.0 2.50
09431-023
–30 2.50
Figure 23. AMP2–2630 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
2.53
2.56
2.59
2.62
2.65
2.68
FREQUENCY (GHz)
2.71
2.74
2.77
2.80
09431-026
2.5
Figure 26. AMP2–2630 MHz: Noise Figure vs. Frequency and Temperature
Rev. B | Page 15 of 40
ADL5243
Data Sheet
0
1.0
0dB
450MHz 748MHz 943MHz
0.8
–5
1960MHz 2140MHz 2630MHz 3600MHz
0.6
ABSOLUTE ERROR (dB)
ATTENUATION (dB)
–10 –15 –20 –25 –30
0.4 0.2 0 –0.2 –0.4 –0.6
–35
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
FREQUENCY (GHz)
–1.0
09431-027
–40 0.1
0
24
28
32
–5
INPUT RETURN LOSS (dB)
ATTENUATION (dB)
20
0
4dB 8dB
–11
16
Figure 30. DSA: Absolute Error vs. Attenuation 0dB
–6
12
ATTENUATION (dB)
Figure 27. DSA: Attenuation vs. Frequency –1
8
4
09431-030
–0.8
31.5dB
–16
16dB –21
+85°C +25°C –40°C
–26
0dB –10
–15 31.5dB –20
–25
–31
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
FREQUENCY (GHz)
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
Figure 31. DSA: Input Return Loss vs. Frequency, All States
0.5
0
1960MHz 2140MHz 2630MHz 3600MHz
0.3
–5
OUTPUT RETURN LOSS (dB)
450MHz 748MHz 943MHz
4.1
FREQUENCY (GHz)
Figure 28. DSA: Attenuation vs. Frequency and Temperature
0.4
0.2 0.1 0 –0.1 –0.2 –0.3
0dB –10
–15 31.5dB
–20
–25
–0.5 0
4
8
12
16
20
24
ATTENUATION (dB)
28
32
–30 0.1
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
FREQUENCY (GHz)
Figure 32. DSA: Output Return Loss vs. Frequency, All States
Figure 29. DSA: Step Error vs. Attenuation
Rev. B | Page 16 of 40
09431-032
–0.4 09431-029
STEP ERROR (dB)
–30 0.1
09431-028
0.5
09431-031
31.5dB –36 0.1
Data Sheet
ADL5243 55
36
150 1960MHz
IIP3
35
50
100
33
40
PHASE (Degrees)
45
IIP3 (dBm)
34
35
32
50 2630MHz
0
–50
IP1dB
30 0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
25 3.6
–150
FREQUENCY (GHz)
943MHz
0
4
8
12
16
20
24
28
32
960
965
ATTENUATION (dB)
09431-036
–100
09431-033
30
31
Figure 36. DSA: Phase vs. Attenuation
Figure 33. DSA: Input P1dB and Input IP3 vs. Frequency, Minimum Attenuation State
3
CH3 2.00V
CH4 200mV
M10ns 10GS/s A CH3 IT 1.0ps/pt
1.24V
40
GAIN
35 30
P1dB
25 20 15 10
NF
5 0 925
09431-034
4
OIP3
45
930
935
940
945
950
955
FREQUENCY (MHz)
09431-037
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
50
Figure 37. Loop–943 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency, Minimum Attenuation State
Figure 34. DSA: Gain Settling Time, 0 dB to 31.5 dB
0
S22
–10
S-PARAMETERS (dB)
–20
3
4
S11 –30 –40 –50
S12 –60 –70
CH3 2.00V
CH4 200mV
M10ns 10GS/s A CH3 IT 1.0ps/pt
1.24V
Figure 35. DSA: Gain Settling Time, 31.5 dB to 0 dB
–90 0.70
0.75
0.80
0.85
0.90
0.95
FREQUENCY (GHz)
1.00
1.05
1.10
09431-038
–80 09431-035
IP1dB (dBm)
2140MHz
Figure 38. Loop–943 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
Rev. B | Page 17 of 40
ADL5243
Data Sheet 42
46 925MHz
2.14GHz
943MHz
961MHz
40
OIP3 (dBm)
42
OIP3 (dBm)
2.11GHz
41
44
40 38
2.17GHz
39 38 37
36
36
34
6
8
10
12
14
16
18
20
22
POUT PER TONE (dBm)
34 1
11
13
15
17
19
21
35
GAIN 30
P1dB 25 20 15 10
NF
5
2.12
2.13
2.14
2.15
2.16
2.17
Figure 40. Loop–2140 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency, Minimum Attenuation State
OIP3
40 35
GAIN
30
P1dB
25 20 15 10 5 0 2.57
NF
2.59
2.61
2.63
2.65
2.67
2.69
FREQUENCY (GHz)
09431-043
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
40
09431-040
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
9
45
OIP3
FREQUENCY (GHz)
Figure 43. Loop–2630 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency, Minimum Attenuation State
5
5 0
0
S22
–10
S22
–5
S-PARAMETERS (dB)
–5
S-PARAMETERS (dB)
7
Figure 42. Loop–2140 MHz: OIP3 vs. POUT and Frequency, Minimum Attenuation State
45
S11
–15 –20 –25 –30
–10
S11
–15 –20 –25 –30 –35
–35
S12
–40
S12
–40
–45
2.05
2.10
2.15
2.20
FREQUENCY (GHz)
2.25
2.30
–50 2.50
09431-041
–45 2.00
5
POUT PER TONE (dBm)
Figure 39. Loop–943 MHz: OIP3 vs. POUT and Frequency, Minimum Attenuation State
0 2.11
3
Figure 41. Loop–2140 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
2.55
2.60
2.65
2.70
2.75
FREQUENCY (GHz)
2.80
2.85
2.90
09431-044
4
09431-039
32
09431-042
35
Figure 44. Loop–2630 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
Rev. B | Page 18 of 40
Data Sheet
ADL5243 110
42
105
2.69GHz
100
SUPPLY CURRENT (mA)
2.63GHz
40
38 2.57GHz
37 36
80
70
6 8 10 12 POUT PER TONE (dBm)
14
16
18
60 –40 –30 –20 –10
09431-045
4
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
Figure 45. Loop–2630 MHz: OIP3 vs. POUT and Frequency, Minimum Attenuation State
Figure 48. AMP2: Supply Current vs. Voltage and Temperature 150 145 140
110
SUPPLY CURRENT (mA)
105 100 95
5.25V
90
5.00V
85
4.75V
80
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
09431-046
70 –40 –30 –20 –10
Figure 46. AMP1: Supply Current vs. Voltage and Temperature 105
100 –40°C
95
+25°C
90
85
+85°C
80
–2
0
2
4
6
8
10
12
14
16
18
20
POUT PER TONE (dBm)
22
09431-147
75
–4
135 130 125 120 115 110 105 100 95 90 85 80 75 70 –6 –4 –2
75
70 –6
4.75V
75
65
2
5.00V 5.00V
85
34
0
SUPPLY CURRENT (mA)
90
35
33
SUPPLY CURRENT (mA)
5.25V 95
Figure 47. AMP1: Supply Current vs. POUT and Temperature
Rev. B | Page 19 of 40
+25°C +85°C
–40°C
0
2
4
6
8
10 12 14 16 18 20 22 24 26
POUT PER TONE (dBm)
Figure 49. AMP2: Supply Current vs. POUT and Temperature
09431-149
OIP3 (dBm)
39
09431-047
41
Data Sheet
45
100
40
90
35
80 PERCENTAGE (%)
30 25 20 15
70 60 50 40 30
10
3.8
NOISE FIGURE (dB)
09431-051
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.3
20.0
GAIN (dB)
09431-048
19.9
19.8
19.7
19.6
19.5
19.4
19.3
19.2
19.1
19.0
18.9
18.8
18.7
18.6
18.5
18.4
0
18.3
10
0
2.4
20
5
2.5
PERCENTAGE (%)
ADL5243
Figure 53. AMP1: Noise Figure Distribution at 2140 MHz
Figure 50. AMP1: Gain Distribution at 2140 MHz
40
25
35 20 PERCENTAGE (%)
PERCENTAGE (%)
30
15
10
25 20 15 10
5
15.0
GAIN (dB)
09431-052
14.9
26.9
14.8
14.7
14.6
14.5
14.4
14.3
14.2
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
13.3
26.8
P1dB (dBm)
0 09431-049
20.5
20.4
20.3
20.2
20.1
20.0
19.9
19.8
19.7
19.6
19.5
19.4
19.3
19.2
19.1
19.0
18.9
0
18.8
5
Figure 54. AMP2: Gain Distribution at 2140 MHz
Figure 51. AMP1: P1dB Distribution at 2140 MHz 50
35
45 30
40 PERCENTAGE (%)
20 15
35 30 25 20 15
10
10 5
5
P1dB (dBm)
Figure 52. AMP1: OIP3 Distribution at 2140 MHz
Figure 55. AMP2: P1dB Distribution at 2140 MHz
Rev. B | Page 20 of 40
09431-053
26.7
26.6
26.5
26.4
26.3
26.2
26.1
26.0
25.9
25.8
25.7
25.6
25.5
25.4
OIP3 (dBm)
0
25.3
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
25.2
0
09431-050
PERCENTAGE (%)
25
Data Sheet
ADL5243
70
60
60
50
PERCENTAGE (%)
40 30
40
30
20
20
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
0
3.1
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 OIP3 (dBm)
3.0
0
NOISE FIGURE (dB)
Figure 57. AMP2: Noise Figure Distribution at 2140 MHz
Figure 56. AMP2: OIP3 Distribution at 2140 MHz
Rev. B | Page 21 of 40
09431-055
10
10
09431-054
PERCENTAGE (%)
50
ADL5243
Data Sheet
APPLICATIONS INFORMATION BASIC LAYOUT CONNECTIONS The basic connections for operating the ADL5243 are shown in Figure 58. The schematic of AMP2 is configured for 2140 MHz operation. SERIAL PARALLEL INTERFACE
VDD
VDD
0.01µF
C17
1 2 3 4
DSAIN AMP1OUT L1 470nH C15 68pF
NC
NC NC
DSAIN
AMP1OUT/VCC NC NC
NC AMP2IN NC NC
24 23 22
C5 100pF
C21 0.1µF
DSAOUT
21 20 19 18 17
AMP2IN C27 2.2pF
C28 1.8pF
C8 10pF
VCC2
9 10 11 12 13 14 15 16
C14 1.2nF
C13 1µF
DSAOUT
ADL5243
NC
6
8
VDD
NC
5
7
C4 0.1µF
VDD
NC AMP1IN NC NC NC NC AMP2OUT/VCC2 VBIAS
C1 100pF
SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6
32 31 30 29 28 27 26 25
L2 9.5nH C3 10pF
AMP1IN C22 1pF
C25 10nF
C20 10µF
VCC
AMP2OUT
Figure 58. Basic Connections
Rev. B | Page 22 of 40
09431-056
C23 10pF
Data Sheet
ADL5243
Amplifier 1 Power Supply AMP1 in the ADL5243 is a broadband gain block. The dc bias is supplied through Inductor L1 and is connected to the AMP1OUT pin. Three decoupling capacitors (C13, C14, and C25) are used to prevent RF signals from propagating on the dc lines. The dc supply ranges from 4.75 V to 5.25 V and should be connected to the VCC test pin.
Amplifier 1 RF Input Interface
Additionally, bias is provided through this pin. Figure 58 shows the output matching components and is configured for 2140 MHz.
DSA RF Input Interface Pin 4 is the RF input for the DSA of the ADL5243. The input impedance of the DSA is close to 50 Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C1) is required.
DSA RF Output Interface
Pin 10 is the RF input for AMP1 of the ADL5243. The amplifier is internally matched to 50 Ω at the input; therefore, no external components are required. Only a dc blocking capacitor (C21) is required.
Amplifier 1 RF Output Interface
Pin 21 is the RF output for the DSA of the ADL5243. The output impedance of the DSA is close to 50 Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C5) is required.
DSA SPI Interface
Pin 6 is the RF output for AMP1 of the ADL5243. The amplifier is internally matched to 50 Ω at the output as well; therefore, no external components are required. Only a dc blocking capacitor (C4) is required. The bias is provided through this pin via a choke inductor, L1.
Amplifier 2 Power Supply The collector bias for AMP2 is supplied through Inductor L2 and is connected to the AMP2OUT pin, whereas the base bias is provided through Pin 16. The base bias is connected to the same supply pin as the collector bias. Three decoupling capacitors (C3, C20, and C25) are used to prevent RF signals from propagating on the dc lines. The dc supply ranges from 4.75 V to 5.25 V and should be connected to the VCC2 test pin.
The DSA of the ADL5243 can operate in either serial or parallel mode. Pin 32 (SEL) controls the mode of operation. For serial mode operation, connect SEL to ground, and for parallel mode operation, connect SEL to VDD. In parallel mode, Pin 25 to Pin 30 (D6 to D1) are the data bits, with D6 being the LSB. Connect Pin 31 (D0) to ground during parallel mode of operation. In serial mode, Pin 29 is the latch enable (LE), Pin 30 is the data (DATA), and Pin 31 is the clock (CLK). Pin 26, Pin 27, and Pin 28 are not used in the serial mode and should be connected to ground. Pin 25 (D6) should be connected to VDD during the serial mode of operation. To prevent noise from coupling onto the digital signals, an RC filter can be used on each data line.
SPI TIMING
Amplifier 2 RF Input Interface
SPI Timing Sequence
Pin 19 is the RF input for AMP2 of the ADL5243. The input of the amplifier is easily matched to 50 Ω with a combination of series and shunt capacitors and a microstrip line serving as an inductor. Figure 58 shows the input matching components and is configured for 2140 MHz.
Figure 60 shows the timing sequence for the SPI function using a 6-bit operation. The clock can be as fast as 20 MHz. In serial mode operation, Register B5 (MSB) is first, and Register B0 (LSB) is last.
Amplifier 2 RF Output Interface Pin 15 is the RF input for AMP2 of the ADL5243. The output of the amplifier is easily matched to 50 Ω with a combination of series and shunt capacitors and a microstrip line serving as an inductor.
Table 4. Mode Selection Table Pin 32 (SEL) Connect to Ground Connect to Supply
Table 5. SPI Timing Specifications Parameter FCLK t1 t2 t3 t4 t5 t6
Limit 10 30 30 10 10 10 30
Unit MHz ns min ns min ns min ns min ns min ns min
Test Conditions/Comments Data clock frequency Clock high time Clock low time Data to clock setup time Clock to data hold time Clock low to LE setup time LE pulse width
Rev. B | Page 23 of 40
Functionality Serial mode Parallel mode
ADL5243
Data Sheet t1
t5
CLK
t2 t3
t4 MSB B5
DATA
B4
B3
B2
B1
LSB B0
09431-057
t6 LE
Figure 59. SPI Timing Diagram (Data Loaded MSB First)
D0/CLK
MSB B5
D1/DATA
B4
B3
B2
B1
LSB B0
09431-058
D2/LE
D6
Figure 60. SPI Timing Sequence
Table 6. DSA Attenuation Truth Table—Serial Mode Attenuation State 0 dB (Reference) 0.5 dB 1.0 dB 2.0 dB 4.0 dB 8.0 dB 16.0 dB 31.5 dB
B5 (MSB) 1 1 1 1 1 1 0 0
B4 1 1 1 1 1 0 1 0
B3 1 1 1 1 0 1 1 0
B2 1 1 1 0 1 1 1 0
B1 1 1 0 1 1 1 1 0
B0 (LSB) 1 0 1 1 1 1 1 0
D4 1 1 1 0 1 1 1 0
D5 1 1 0 1 1 1 1 0
D6 (LSB) 1 0 1 1 1 1 1 0
Table 7. DSA Attenuation Truth Table—Parallel Mode Attenuation State 0 dB (Reference) 0.5 dB 1.0 dB 2.0 dB 4.0 dB 8.0 dB 16.0 dB 31.5 dB
D1 (MSB) 1 1 1 1 1 1 0 0
D2 1 1 1 1 1 0 1 0
D3 1 1 1 1 0 1 1 0
Rev. B | Page 24 of 40
Data Sheet
ADL5243 the spacing is 153 mils and 25 mils respectively. The component spacing is referenced from the center of the component to the edge of the package. Figure 61 to Figure 69 show the graphical representation of the matching network. It is recommended to configure a RC feedback network and bias the AMP2 input through external R for optimal performance at frequency bands less than 500 MHz as shown at Figure 61 and Figure 62. In this case, VBIAS pin must be left open.
ADL5243 AMPLIFIER 2 MATCHING The AMP2 input and output of the ADL5243 can be matched to 50 Ω with two or three external components and the microstrip line used as an inductor. Table 8 lists the required matching components values. All capacitors are Murata GRM155 series (0402 size), and Inductor L2 is a Coilcraft® 0603CS series (0603 size). For all frequency bands, the placement of Capacitors C22, C26, and C28 is critical. Table 9 lists the recommended component spacing of C22, C26, and C28 for the various frequencies. The placement of R12 and C27 is fixed for the matching network on evaluation board and Table 8. Component Values on Evaluation Board Frequency 150 MHz 450 MHz 748 MHz 943 MHz 1960 MHz 2140 MHz 2350 MHz 2630 MHz 3600 MHz 1
C27 2.7n H 0Ω 0Ω 0Ω 2.7 pF 2.2 pF 3.3 pF 2.7 pF 1.0 pF
C26 1.5 pF N/A N/A 3.9 pF N/A N/A 1.6 pF 1.1 pF 1.5 KΩ
C28 N/A 5.1pF 5.1 pF N/A 1.0 pF 1.8 pF 1.5 KΩ 1.5 KΩ 1.2 pF
C8 1500 pF 1000 pF 12 pF 6 pF 10 pF 10 pF 10 pF 10 pF 10 pF
C22 0.5 pF 0.5 pF 1.3 pF 1.3 pF 1.0 pF 1.0 pF 1.0 pF 1.3 pF 1.2 pF
C23 4700 pF 1000 pF 18 pF 100 pF 20 pF 10 pF 20 pF 20 pF 20 pF
L2 390 nH 110 nH 56 nH 56 nH 9.5 nH 9.5 nH 9.5 nH 9.5 nH 9.5 nH
R10 21 Ω 21 Ω 18 Ω 18 Ω 0Ω 0Ω 0Ω 0Ω 0Ω
R20 1 N/A 5.6 Ω 5.6 Ω N/A N/A N/A N/A N/A N/A
R12 22 nH 3.9 nH 3.9 nH 3.3 nH 0Ω 0Ω 0Ω 0Ω 1.0 nH
R16 3.16 kΩ 3.16 kΩ N/A N/A N/A N/A N/A N/A N/A
R15 750 Ω 750 Ω N/A N/A N/A N/A N/A N/A N/A
C10 1 nF 1 nF N/A N/A N/A N/A N/A N/A N/A
R20 is not reserved on the evaluation board.
Table 9. Component Spacing on Evaluation Board Frequency 150 MHz 450 MHz 748 MHz 943 MHz 1960 MHz 2140 MHz 2350 MHz 2630 MHz 3600 MHz
C26 : λ1(mils) 213 N/A N/A 236 N/A N/A 153 126 342
C28 : λ2(mils) N/A 230 315 N/A 366 366 195 161 366
Rev. B | Page 25 of 40
C22 : λ3(mils) 408 485 201 394 244 244 244 240 106
R31 0Ω 0Ω N/A N/A N/A N/A N/A N/A N/A
R30 N/A N/A 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω
ADL5243
Data Sheet NC 20
ADL5243
λ1
R10 21Ω
AMP2IN 19
NC
NC
AMP2OUT//VCC2
VBIAS
C27 2.7nH
13
14
15
16
NC 18
NC 17
AMP2IN C8 1500pF
C26 1.5pF
R31 0Ω
R15 750Ω R16 3.16kΩ
C10 1nF L2 390nH
λ3 R12 22nH
VCC
C22 0.5pF C23 4700pF
09431-161
AMP2OUT
Figure 61. AMP2: Matching Circuit at 150 MHz
NC 20
λ2
ADL5243
R10 21Ω
AMP2IN 19
NC
NC
AMP2OUT//VCC2
VBIAS
C27 0Ω
13
14
15
16
NC 18
C28 5.1pF
R31 0Ω
AMP2IN C8 1000pF
R20 5.6Ω
NC 17 R15 750Ω
R16 3.16kΩ
C10 1nF λ3
L2 110nH R12 3.9nH
VCC
C22 0.5pF
AMP2OUT 09431-162
C23 1000pF
Figure 62. AMP2: Matching Circuit at 450 MHz
Rev. B | Page 26 of 40
Data Sheet
ADL5243 NC 20
λ2 R10 18Ω
ADL5243 AMP2IN 19
C28 5.1pF
NC
NC
AMP2OUT/VCC2
VBIAS
C27 0Ω
13
14
15
16
AMP2IN
C8 12pF
R20 5.6Ω
NC 18
NC 17
L2 56nH
λ3
R12 3.9nH
C22 1.3pF C23 18pF
09431-061
AMP2OUT
Figure 63. AMP2: Matching Circuit at 748 MHz
NC 20 λ1
ADL5243
R10 18Ω
AMP2IN 19
NC
NC
AMP2OUT//VCC2
VBIAS
C27 0Ω
13
14
15
16
λ3
C26 3.9pF
AMP2IN
C8 6pF
NC 18
NC 17
L2 56nH R12 3.3nH
C22 1.3pF
AMP2OUT 09431-062
C23 100pF
Figure 64. AMP2: Matching Circuit at 943 MHz
Rev. B | Page 27 of 40
ADL5243
Data Sheet NC 20
λ2
ADL5243
R10 0Ω
AMP2IN
AMP2IN 19 C28 1.0pF
NC
NC
AMP2OUT//VCC2
VBIAS
C27 2.7pF
13
14
15
16
C8 10pF
NC 18
NC 17
L2 9.5nH
λ3
R12 0Ω
C22 1.0pF C23 20pF
09431-165
AMP2OUT
Figure 65. AMP2: Matching Circuit at 1960 MHz
NC 20
λ2
ADL5243
R10 0Ω
AMP2IN 19
NC
NC
AMP2OUT/VCC2
VBIAS
C27 2.2pF
13
14
15
16
λ3
C28 1.8pF
AMP2IN
C8 10pF
NC 18
NC 17
L2 9.5nH R12 0Ω
C22 1pF
AMP2OUT 09431-064
C23 10pF
Figure 66. AMP2: Matching Circuit at 2140 MHz
Rev. B | Page 28 of 40
Data Sheet
ADL5243 NC 20
ADL5243
λ2 λ1
R10 0Ω
AMP2IN
AMP2IN 19
NC
NC
AMP2OUT//VCC2
VBIAS
C27 3.3pF
13
14
15
16
C26 1.6pF
C28 1.5kΩ
C8 10pF
NC 18
NC 17
L2 9.5nH
λ3
R12 0Ω
C22 1.0pF C23 20pF
09431-167
AMP2OUT
Figure 67. AMP2: Matching Circuit at 2350 MHz
NC 20
ADL5243
λ2 λ1
R10 0Ω
AMP2IN 19
NC
NC
AMP2OUT//VCC2
VBIAS
C27 2.7pF
13
14
15
16
λ3
C26 1.1pF
C28 1.5kΩ
AMP2IN C8 10pF
NC 18
NC 17
L2 9.5nH R12 0Ω
C22 1.3pF
AMP2OUT 09431-065
C23 20pF
Figure 68. AMP2: Matching Circuit at 2630 MHz
Rev. B | Page 29 of 40
ADL5243
Data Sheet NC 20
ADL5243
λ2 λ1
R10 0Ω
AMP2IN 19
NC
NC
AMP2OUT//VCC2
VBIAS
C27 1.0pF
13
14
15
16
λ3
C26 1.5kΩ
C28 1.2pF
AMP2IN C8 10pF
NC 18
NC 17
L2 9.5nH R12 0Ω
C23 20pF
C22 1.2pF
AMP2OUT 09431-169
R12 1nH
Figure 69. AMP2: Matching Circuit at 3600 MHz
Rev. B | Page 30 of 40
Data Sheet
ADL5243 λ4
ADL5243 LOOP PERFORMANCE The typical configuration of the ADL5243 is to connect in AMP1-DSA-AMP2 mode, as shown in Figure 70. Because AMP1 and DSA are broadband in nature and internally matched, only an ac coupling capacitor is required between them. The AMP2 is externally matched for each frequency band of operation, and these matching elements should be placed between the DSA and AMP2 and at the output of AMP2. Matching circuits for AMP2 are shown in Figure 61 through Figure 69. This works well in a loop in each case but matching circuits between the DSA and AMP2 requires slight retuning, such as adding a shunt capacitor at the DSA output or changing the location of a shunt capacitor for optimum performance in a loop at certain frequency bands. Figure 71 and Figure 72 show the retuned matching circuits from Figure 66 and Figure 69 at 2140 MHz and 3600 MHz, respectively. Figure 37 to Figure 45 show the performance of the ADL5243 when connected in a loop for the three primary frequency bands of operation, namely 943 MHz, 2140 MHz, and 2630 MHz.
DSAOUT 21 C11 1.3pF NC 20
NC
NC
AMP2OUT/VCC2
VBIAS
C27 2.2pF
13
14
15
16
VCC
C28: λ2 (mils) 366 342
C22: λ3 (mils) 244 106
C28 1.8pF
C6 10pF
NC 18
NC 17
L2 9.5nH
λ3
R12 0Ω
C22 1pF
C11: λ4 (mils) 122
C23 10pF
AMP2OUT
N/A
09431-171
2140 MHz 3600 MHz
C26: λ1 (mils) N/A 126
R33 0Ω AMP2IN 19
Table 10. Component Spacing in a Loop on Evaluation Board Frequency
λ2
ADL5243
VCC2
VDD/SPI
Figure 71. ADL5243 Matching Circuit at 2140 MHz in a Loop
DSAOUT 21
AMP1
DSA
IMN
AMP2
OMN
RFOUT
NC 20
ADL5243
λ2 λ1
ADL5243 09431-067
R33 0Ω
AMP2IN 19 C27 1.0pF
NC
AMP2OUT/VCC2
VBIAS
Figure 70. ADL5243 Loop Block Diagram
NC 13
14
15
16
λ3
C26 1.2pF
C28 1.5kΩ
C6 10pF
NC 18
NC 17
L2 9.5nH C22 1pF R12 1.2nH
C23 10pF
AMP2OUT 09431-172
RFIN
Figure 72. ADL5243 Matching Circuit at 3600 MHz in a Loop Rev. B | Page 31 of 40
ADL5243
Data Sheet
PROPER DRIVING LEVEL FOR THE OPTIMUM ACLR It is usually required to drive the amplifier as high as possible in order to maximize output power. However, properly driving AMP1 and AMP2 at the ADL5243 is required to achieve optimum ACLR performance. Once output power approaches P1dB and OIP3, there is ACLR degradation. The driving level of amplifier with a modulated signal should be backed off properly from P1dB by at least the amount of a signal crest factor for optimum ACLR. So assuming a gain and P1dB of AMP1 at 2140 MHz are 19 dB and 19 dBm respectively, the output power, which is backed off by 11 dB crest factor at the modulated signal case, is 8 dBm. Therefore, the proper input driving level should be under −11 dBm. –30
SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN
–35 –40
AMP1, ADJ
AMP2, ADJ
–45
AMP1, ALT
AMP2, ALT
Figure 74 shows the recommended land pattern for the ADL5243. To minimize thermal impedance, the exposed paddle on the 5 mm × 5 mm LFCSP package is soldered down to a ground plane. To improve thermal dissipation, 25 thermal vias are arranged in a 5 × 5 array under the exposed paddle. If multiple ground layers exist, they should be tied together using vias. For more information on land pattern design and layout, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
ACLR (dBc)
–50 –55 –60 –65 –70 –75 –80 –85
PIN (dBm)
–8
–4
0
4
8
09431-173
–90 –95 –40 –36 –32 –28 –24 –20 –16 –12
For the best thermal performance, it is recommended to add as many thermal vias as possible under the exposed pad of the LFCSP. The above thermal resistance numbers assume a minimum of 25 thermal vias arranged in a 5 × 5 array with a via diameter of 13 mils, via pad of 25 mils, and pitch of 25 mils. The vias are plated with copper, and the drill hole is filled with a conductive copper paste. For optimal performance, it is recommended to fill the thermal vias with a conductive paste of equivalent thermal conductivity, as mentioned above, or use an external heat sink to dissipate the heat quickly without affecting the die junction temperature. It is also recommended to extend the ground pattern as shown in Figure 74 to improve thermal efficiency.
1
Figure 73. Single Carrier WCDMA Adjacent Chanel Power Ratio vs. Input Power at AMP1 and AMP2, 2140 MHz
The ADL5243 is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP. The thermal resistance from junction to air (θJA) is 34.8°C/W. The thermal resistance for the product was extracted assuming a standard 4-layer JEDEC board with 25 copper platter thermal vias. The thermal vias are filled with conductive copper paste, AE3030, with a thermal conductivity of 7.8 W/mk and thermal expansion as follows: α1 of 4 × 10−5/°C and α2 of 8.6 × 10−5/°C. The thermal resistance from junction to case (θJC) is 6.2°C/W, where case is the exposed pad of the lead frame package.
Rev. B | Page 32 of 40
25 MIL VIA PAD WITH 13 MIL VIA
8
DSAOUT
17
09431-068
THERMAL CONSIDERATIONS
DSAIN
24
Figure 74. Recommended Land Pattern
Data Sheet
ADL5243
EVALUATION BOARD The schematic of the ADL5243 evaluation board is shown in Figure 75. All RF traces on the evaluation board have a characteristic impedance of 50 Ω and are fabricated from Rogers3003 material. The traces are CPWG with a width of 25 mils, spacing of 20 mils, and dielectric thickness of 10 mils. The input and output to the DSA and amplifier should be ac-coupled with capacitors of an appropriate value to ensure broadband performance. The bias to AMP1 is provided through a choke connected to the AMP1OUT pin and, similarly, bias to AMP2 is provided through a choke connected to the AMP2OUT pin. Bypassing capacitors are recommended on all supply lines to minimize RF coupling. The DSA and the amplifiers can be individually biased or connected to the VDD plane through Resistors R1, R2, and R11. The schematic of AMP2 on evaluation board is configured for 2140 MHz operation. When configuring the ADL5243 evaluation board in the AMP1-DSA-AMP2 loop, remove Capacitors C1, C4, C5, and C8 and remove Resistor R10. Place 10 pF in place of C24 and C6, and 0 Ω in place of R32 and R33. If needed, placing a shunt capacitor (1.3 pF) at the output of the DSA improves the output return loss of this loop as described at the ADL5243 Loop Performance section.
On the digital signal traces, provisions for an RC filter are made to clean any potential coupled noise. In normal operation, series resistors are 0 Ω and shunt resistors and capacitors are open. The evaluation board is designed to control DSA in either parallel or serial mode by connecting the SEL pin to the supply or ground by a switch. For adjusting attenuation at DSA, the ADL5243 can be programmed in two ways: through the on-board USB interface from a PC USB port, or through an SDP board, which will become the Analog Devices common control board in the future. The on-board USB interface circuitry of the evaluation board is powered directly by the PC. USB based programming software is available to download from the ADL5243 product page at www.analog.com. Figure 71 shows the window of the programming software where the user selects serial or parallel mode for the attenuation adjustment at DSA. The selection of the mode in the window should match the mode of the evaluation board switch. It is highly recommended to refer the evaluation board layout for the optimal and stable performance of each block as well as for the improvement of thermal efficiency.
Table 11. Evaluation Board Configurations Options Component C1, C5 C4, C21 C13, C14, C15
Function AC coupling caps for DSA. AC coupling capacitors for AMP1. Power supply bypassing capacitors for AMP1. Capacitor C15 should be closest to the device.
L1 C8 C23 C22
The bias for AMP1 comes through L1 when connected to a 5 V supply. L1 should be high impedance for the frequency of operation, while providing low resistance for the dc current. AMP2 input ac coupling capacitor. AMP2 output ac coupling capacitor. AMP2 shunt output tuning capacitor.
C26 C27 C28
ANP2 shunt input tuning capacitor. AMP2 series input tuning capacitor. AMP2 shunt input tuning capacitor.
C3, C25, C20
Power supply bypassing capacitors for AMP2. Capacitor C3 should be closest to the device.
L2
The bias for AMP2 comes through L2 when connected to a 5 V supply. L2 should be high impedance for the frequency of operation, while providing low resistance for the dc current. Power supply bypassing capacitor for DSA. Placeholder for the series component for the other frequency band. Replace with capacitors and resistors to connect the device in a loop. Resistors to connect the supply for the amplifier and the DSA to the same VDD plane. Switch to change between serial and parallel mode operation; connect to a supply for parallel mode and to ground for serial mode operation.
C17 R10, R12 C6, C24, R32, R33 R1, R2, R11 S1
Rev. B | Page 33 of 40
Default Value C1, C5 = 10 pF C4, C21 = 10 pF C13 = 10 μF C14 = 10 nF C15 = 10 pF L1 = 33 nH C8 = 10 pF C23 = 10 pF C22 = 1.0 pF at 244 mils from edge of package DNP C27 = 2.2 pF C28 = 1.8 pF at 366 mils from edge of package C3 = 10 pF C25 = 10 nF C20 = 10 μF L2 = 9.5 nH C17 = 0.1 μF R10, R12 = 0 Ω C6, C24, R32, R33 = open R1, R2 = open 3-pin rocker
AGND
Figure 75. ADL5243 Evaluation Board
Rev. B | Page 34 of 40
0Ω DNI
R1
2 3 4 5
AGND
1
AMP1OUT
AMP1IN 1
AGND
VDD
1
2 3 4 5
AGND
2 3 4 5
1
DSAIN
10pF
C21
C13 10µF
VCC RED
10pF
C4
10pF
C1
C17 0.1µF
0
DNI R2
L1 33nH
AGND
C14 0.01µF
C24 10pF DNI
R32 0Ω DNI
VDD
AGND
C15 10pF
AGND
1 2 3 4 5 6 7 8
AGND
C22 1pF
AGND
C23 10pF
R12 0
C10
AGND
9.5nH
L2
0Ω
R30
0.001µF DNI
24 23 22 21 20 19 18 17
U1
CLK_D0 DATA_D1 LE_D2 D3 D4 D5 D6
VDD VDD NC NC NC NC ADL5243ACPZ DSAOUT DSAIN NC NC AMP2IN AMP1OUT/VCC NC NC NC NC
AGND
VDD 1 RED
1
PAD 32 31 30 29 28 27 26 25 EPAD SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6
NC AMP1IN NC NC NC NC AMP2OUT/VCC2 VBIAS
9 10 11 12 13 14 15 16
S1 3 2
R15 750Ω DNI
R16 3.16kΩ DNI
R31 0Ω DNI
5 4 3 2 AGND
AMP2OUT 1
C3 10pF
AGND
2.2pF
C27
AGND
C11 1.3pF DNI
R33 0Ω DNI R10
AGND
C20 10µF
0Ω
DNI R11
10pF
C8
10pF
VCC2 1 RED
AGND
R20 0Ω
0Ω C28 1.8pF
C25 10000pF
C26 1.1pF DNI
C6 10pF DNI
C5
VDD
AGND
AMP2IN
5 4 3 2
1
AGND
DSAOUT
5 4 3 2
1
ADL5243 Data Sheet
09431-069
D1
C37 1µF
A C SML-210MTT86
R4 2kΩ
U3
DGND
7 1 IN1 OUT1 8 2 IN2 OUT2 6 3 SD_N FB PAD GND PAD 5
ADP3334ACPZ
DGND
C35 0.1µF
DGND
3V3_USB
R3 78.7kΩ
FB
C44 1000pF
C36 0.1µF
R9 140kΩ
IN
IN
IN IN
R45 2kΩ
C38 0.1µF
WAKEUP
RESETN
SCL SDA
C47 1µF
Rev. B | Page 35 of 40
Figure 76. USB/SDP Interface Circuitry on the Customer Evaluation Board R18 100kΩ
LE_D2
R44 100kΩ
R43 TBD0603 DNI
CLK_D0
DATA_D1
DGND1 BLK
DGND
1
AGND
DGND
0Ω
R46
0Ω
R17
0Ω
R42
0Ω
R6
DNI
DNI
DNI
C45 0.1µF
DECOUPLING FOR U1
C39 0.1µF
C33 0.1µF
1 2 3 6 7
8
DGND
U5
0Ω
R22
0Ω
R21
C46 0.1µF
DGND
DNI
C49 0.1µF
R47 100kΩ
R5 2kΩ
C48 0.1µF
DGND
DGND
A0 VCC A1 SDA 5 A2 SCL WP 24LC32A-I/MS VSS E014160 4 JEDEC_TYPE=MSOP8
U2 8 VCC A0 A1 A2 5 SCL SDA WC_N GND 4 24LC64-I-SN
DGND
1 2 3 6 7
C9 10pF
D6 D5 D4 D3
C34 0.1µF
R7 100kΩ DNI
AGND
RDY0_SLRD RDY1_SLWR
WAKEUP RESERVED
XTALIN RESET_N
SCL SDA
P2
DGND
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 FX8-120S-SV(21)
DGND
1 2
44 14
5 42
15 16
AVCC
0.1µF
C31
10pF
C50
GND
1
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT OUT OUT OUT
PB1 PB2 PB3 PB4 PB5 PB6 PB7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
DGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 FX8-120S-SV(21)
P2
5V_SDP RED (FROM MAIN BOARD; 200mA MINIMUM) 5V_SDP
PA7
1
2kΩ
R8
OUT
IFCLK CLKOUT CTL0_FLAGA CTL1_FLAGB CTL2_FLAGC
C51 22pF
XTALOUT
XTALIN
CR2
3
A C SML-210MTT86
DM DP
CASE 2 4
Y1 24.000000MHZ
CY7C68013A-56LTXC E013815 JEDEC_TYPE=QFN56_8X8_PAD5_2X4_5
PB0_FD0 PB1_FD1 PB2_FD2 PB3_FD3 PB4_FD4 PB5_FD5 PB6_FD6 PB7_FD7 PD0_FD8 PD1_FD9 PD2_FD10 PD3_FD11 PD4_FD12 PD5_FD13 PD6_FD14 PD7_FD15 PAD
18 19 20 21 22 23 24 25 45 46 47 48 49 50 51 52
33 34 35 36 37 38 39 40
4 8 9 13 54 29 30 31
U4
DGND
XTALOUT DPLUS DMINUS IFCLK CLKOUT CTL0_FLAGA CTL1_FLAGB CTL2_FLAGC
VCC
PA0_INT0_N PA1_INT1_N PA2_SLOE PA3_WU2 PA4_FIFOADR0 PA5_FIFOADR1 PA6_PKTEND PA7_FLAGD_SLCS_N
17 28
3 6
27 41
11 26
32 53
7
10
43 56
IO
12
55 PAD
5V_USB
DGND
OUT
PB0
DGND
DGND
C52 22pF
CLK_D0
D3 D4 D5 D6
LE_D2
DATA_D1
DGND
OUT OUT OUT OUT OUT OUT OUT
0Ω
R25
0Ω
R23
0Ω
R20
0Ω
R19
0Ω
R24
0Ω
0Ω R54
GND PINS
P1
DGND
R29 1.00kΩ DNI
DGND
R28 1.00kΩ DNI
DGND
R27 1.00kΩ DNI
DGND
R26 1.00kΩ DNI
R55 1.00kΩ DNI
C19 330pF DNI
C18 330pF DNI
C16 330pF DNI
C12 330pF DNI
C53 330pF DNI
897-43-005-00-100001
G1 G2 G3 G4
1 2 3 4 5
TSW-105-08-G-D DNI PLACEHOLDER
DGND
P3
R53
PA0 PA1 PA2 PA3 PA4 PA5 PA6
5V_USB
1 2 3 4 5 6 7 8 9 10
R13 1.00kΩ DNI
C55 330pF DNI
DGND
R14 1.00kΩ DNI
D6
D5
D4
D3
C56 330pF DNI
CLK_D0
DATA_D1
LE_D2
09431-176
3V3_USB
Data Sheet ADL5243
Data Sheet
09431-071
ADL5243
09431-070
Figure 78. Evaluation Board Layout—Bottom
Figure 77. Evaluation Board Layout—Top
Rev. B | Page 36 of 40
ADL5243
09431-179
Data Sheet
Figure 79. Evaluation Board Control Software
Rev. B | Page 37 of 40
ADL5243
Data Sheet
OUTLINE DIMENSIONS 5.00 BSC SQ
0.60 MAX 0.60 MAX 25
32 1
24
0.50 BSC
3.45 3.30 SQ 3.15
EXPOSED PAD
17 TOP VIEW
1.00 0.85 0.80 SEATING PLANE
0.80 MAX 0.65 TYP
12° MAX
0.30 0.25 0.18
0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
8 16
9 BOTTOM VIEW
0.25 MIN
3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
05-23-2012-A
4.75 BSC SQ
PIN 1 INDICATOR
PIN 1 INDICATOR
Figure 80. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters
ORDERING GUIDE Model 1 ADL5243ACPZ-R7 ADL5243-EVALZ 1
Temperature Range −40°C to +85°C
Package Description 32-Lead Lead Frame Chip Scale Package LFCSP_VQ Evaluation Board
Z = RoHS Compliant Part.
Rev. B | Page 38 of 40
Package Option CP-32-3
Data Sheet
ADL5243
NOTES
Rev. B | Page 39 of 40
ADL5243
Data Sheet
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09431-0-8/12(B)
Rev. B | Page 40 of 40
