Transcript
LT1792 Low Noise, Precision, JFET Input Op Amp U
FEATURES ■ ■ ■ ■ ■ ■
DESCRIPTIO
The LT®1792 achieves a new standard of excellence in noise performance for a JFET op amp. The 4.2nV/√Hz voltage noise combined with low current noise and picoampere bias currents make the LT1792 an ideal choice for amplifying low level signals from high impedance capacitive transducers.
100% Tested Low Voltage Noise: 6nV/√Hz Max A Grade 100% Temperature Tested Voltage Gain: 1.2 Million Min Offset Voltage Over Temp: 800µV Max Gain-Bandwidth Product: 5.6MHz Typ Guaranteed Specifications with ±5V Supplies
U APPLICATIO S ■ ■ ■ ■
■ ■
Photocurrent Amplifiers Hydrophone Amplifiers High Sensitivity Piezoelectric Accelerometers Low Voltage and Current Noise Instrumentation Amplifier Front Ends Two and Three Op Amp Instrumentation Amplifiers Active Filters
The LT1792 is unconditionally stable for gains of 1 or more, even with load capacitances up to 1000pF. Other key features are 600µV VOS and a voltage gain of over 4 million. Each individual amplifier is 100% tested for voltage noise, slew rate and gain bandwidth. The design of the LT1792 has been optimized to achieve true precision performance with an industry standard pinout in the SO-8 package. Specifications are also provided for ±5V supplies. , LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
Low Noise Hydrophone Amplifier with DC Servo
R3 3.9k
5V TO 15V 2
–
40 7
LT1792
3
C1*
6
+
R2 200Ω
OUTPUT C2 0.47µF
4 –5V TO –15V R6 100k
6
2
3
R5 1M
LT1097
R7 1M DC OUTPUT ≤ 2.5mV FOR TA < 70°C OUTPUT VOLTAGE NOISE = 128nV/√Hz AT 1kHz (GAIN = 20) C1 ≈ CT ≈ 100pF TO 5000pF; R4C2 > R8CT; *OPTIONAL
+
R8 100M
–
CT HYDROPHONE
R4 1M
PERCENT OF UNITS (%)
R1* 100M
1kHz Input Noise Voltage Distribution VS = ±15V TA = 25°C
270 OP AMPS TESTED
30
20
10
0 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 INPUT VOLTAGE NOISE (nV/√Hz) 1792 TA02 1792 TA01
1
LT1792 W W
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AXI U
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ABSOLUTE
RATI GS
(Note 1)
Supply Voltage ..................................................... ±20V Differential Input Voltage ...................................... ±40V Input Voltage (Equal to Supply Voltage) ............... ±20V Output Short-Circuit Duration ........................ Indefinite Operating Temperature Range ............... – 40°C to 85°C
Specified Temperature Range Commercial (Note 8) ......................... – 40°C to 85°C Industrial ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec) ................ 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW VOS ADJ 1
8 NC
–IN A 2
+
+IN A 3 V
–
A
7 V
6 OUT 5 VOS ADJ
4
LT1792ACN8 LT1792CN8 LT1792AIN8 LT1792IN8
ORDER PART NUMBER
TOP VIEW VOS ADJ 1
8 NC
–IN A 2
7 V+
+IN A 3 V
–
A
LT1792ACS8 LT1792CS8 LT1792AIS8 LT1792IS8
6 OUT 5 VOS ADJ
4
N8 PACKAGE 8-LEAD PDIP
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 140°C, θJA = 130°C/W
TJMAX = 160°C, θJA = 190°C/W
S8 PART MARKING 1792A 1792
1792AI 1792I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = 0V, unless otherwise noted. (Note 9) LT1792AC/LT1792AI MIN TYP MAX
LT1792C/LT1792I MIN TYP MAX
VS = ± 5V
0.2 0.4
0.6 1.0
0.2 0.4
0.8 1.3
mV mV
Input Offset Current
Warmed Up (Note 3)
100
400
100
400
pA
IB
Input Bias Current
Warmed Up (Note 3)
300
800
300
800
pA
en
Input Noise Voltage
0.1Hz to 10Hz
2.4
2.4
µVP-P
Input Noise Voltage Density
fO = 10Hz fO = 1000Hz
8.3 4.2
6.0
8.3 4.2
6.0
nV/√Hz nV/√Hz
fO = 10Hz, fO = 1000Hz (Note 4)
10
10
1011 1011 1010
1011 1011 1010
Ω Ω Ω
14 27
14 27
pF pF
SYMBOL
PARAMETER
VOS
Input Offset Voltage
IOS
in
Input Noise Current Density
RIN
Input Resistance Differential Mode Common Mode
CIN
Input Capacitance
VCM
Input Voltage Range (Note 5)
CMRR
Common Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
2
CONDITIONS (Note 2)
VCM = –10V to 8V VCM = 8V to 11V VS = ±5V
UNITS
fA/√Hz
13.0 –10.5
13.5 –11.0
13.0 –10.5
13.5 –11.0
V V
VCM = –10V to 13V
85
105
82
100
dB
VS = ±4.5V to ±20V
88
105
83
98
dB
LT1792
ELECTRICAL CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
LT1792AC/LT1792AI MIN TYP MAX
LT1792C/LT1792I MIN TYP MAX
AVOL
Large-Signal Voltage Gain
VO = ±12V, RL = 10k VO = ±10V, RL = 1k
1200 600
4800 4000
1000 500
4500 3000
V/mV V/mV
VOUT
Output Voltage Swing
RL = 10k RL = 1k
±13.0 ±12.0
±13.2 ±12.3
±13.0 ±12.0
±13.2 ±12.3
V V
SR
Slew Rate
RL ≥ 2k (Note 7)
2.3
3.4
2.3
3.4
V/µs
GBW
Gain-Bandwidth Product
fO = 100kHz
4.0
5.6
4.0
5.6
MHz
IS
Supply Current Offset Voltage Adjustment Range
VS = ±5V
4.2 4.2
RPOT (to VEE) = 10k
10
5.20 5.15
4.2 4.2
5.20 5.15
10
UNITS
mA mA mV
The ● denotes specifications which apply over the temperature range 0°C ≤ TA ≤ 70°C. VS = ±15V, VCM = 0V, unless otherwise noted. (Note 9) SYMBOL
PARAMETER
VOS
Input Offset Voltage
∆VOS ∆Temp
Average Input Offset Voltage Drift
IOS
CONDITIONS (Note 2)
MIN
LT1792AC TYP MAX
MIN
LT1792C TYP MAX
UNITS
VS = ± 5V
● ●
0.4 0.6
0.8 1.2
0.8 1.2
2.7 3.2
mV mV
(Note 6)
●
4
10
7
40
µV/°C
Input Offset Current
●
180
500
180
500
pA
IB
Input Bias Current
●
500
1800
500
1800
pA
VCM
Input Voltage Range
● ●
12.9 –10.0
13.4 –10.8
CMRR
Common Mode Rejection Ratio
VCM = –10V to 12.9V
●
81
104
79
99
dB
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ±20V
●
85
99
81
97
dB
AVOL
Large-Signal Voltage Gain
VO = ±12V, RL = 10k VO = ±10V, RL = 1k
● ●
900 500
3600 2600
800 400
3400 2400
VOUT
Output Voltage Swing
RL = 10k RL = 1k
● ●
SR
Slew Rate
RL ≥ 2k (Note 7)
●
2.1
3.1
2.1
3.1
V/µs
GBW
Gain-Bandwidth Product
fO = 100kHz
●
3.2
4.5
3.2
4.5
MHz
IS
Supply Current VS = ±5V
● ●
12.9 –10.0
±12.9 ±13.2 ±11.9 ±12.15
4.2 4.2
13.4 –10.8
V V
V/mV V/mV
±12.9 ±13.2 ±11.9 ±12.15
5.30 5.25
4.2 4.2
V V
5.30 5.25
mA mA
3
LT1792
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the temperature range – 40°C ≤ TA ≤ 85°C. VS = ±15V, VCM = 0V, unless otherwise noted. (Notes 8, 9) LT1792AC/LT1792AI MIN TYP MAX
LT1792C/LT1792I MIN TYP MAX
VS = ±5V
● ●
0.5 0.8
1.0 1.4
1.2 1.5
3.7 4.2
mV mV
(Note 6)
●
4
10
7
40
µV/°C
Input Offset Current
●
300
800
300
800
pA
IB
Input Bias Current
●
1200
4000
1200
4000
pA
VCM
Input Voltage Range
● ●
12.6 –10.0
13.0 –10.5
12.6 –10.0
13.0 –10.5
V V
CMRR
Common Mode Rejection Ratio
VCM = –10V to 12.6V
●
80
103
78
98
dB
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ± 20V
●
83
98
79
96
AVOL
Large-Signal Voltage Gain
VO = ±12V, RL = 10k VO = ±10V, RL = 1k
● ●
850 400
3300 2200
750 300
3000 2000
V/mV V/mV
VOUT
Output Voltage Swing
RL = 10k RL = 1k
● ●
±12.8 ±11.8
±13.1 ±12.1
±12.8 ±11.8
±13.1 ±12.1
V V
SR
Slew Rate
RL ≥ 2k
●
2.0
3.0
2.0
3.0
V/µs
GBW
Gain-Bandwidth Product
fO = 100kHz
●
2.9
4.3
2.9
4.3
MHz
IS
Supply Current VS = ±5V
● ●
SYMBOL
PARAMETER
VOS
Input Offset Voltage
∆VOS ∆Temp
Average Input Offset Voltage Drift
IOS
CONDITIONS (Note 2)
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Typical parameters are defined as the 60% yield of parameter distributions of individual amplifiers. Note 3: Warmed-up IB and IOS readings are extrapolated to a chip temperature of 32°C from 25°C measurements and 32°C characterization data. Note 4: Current noise is calculated from the formula: in = (2qIB)1/2 where q = 1.6 • 10 –19 coulomb. The noise of source resistors up to 200M swamps the contribution of current noise. Note 5: Input voltage range functionality is assured by testing offset voltage at the input voltage range limits to a maximum of 2.3mV (A grade), to 2.8mV (C grade).
4
4.2 4.2
5.40 5.35
4.2 4.2
UNITS
dB
5.40 5.35
mA mA
Note 6: This parameter is not 100% tested. Note 7: Slew rate is measured in AV = – 1; input signal is ±7.5V, output measured at ±2.5V. Note 8: The LT1792AC and LT1792C are guaranteed to meet specified performance from 0°C to 70°C and are designed, characterized and expected to meet these extended temperature limits, but are not tested at – 40°C and 85°C. The LT1792I is guaranteed to meet the extended temperature limits. The LT1792AC and LT1792AI grade are 100% temperature tested for the specified temperature range. Note 9: The LT1792 is measured in an automated tester in less than one second after application of power. Depending on the package used, power dissipation, heat sinking, and air flow conditions, the fully warmed-up chip temperature can be 10°C to 50°C higher than the ambient temperature.
LT1792
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TYPICAL PERFOR A CE CHARACTERISTICS Voltage Noise vs Chip Temperature
Voltage Noise vs Frequency
VOLTAGE NOISE (1µV/DIV)
RMS VOLTAGE NOISE DENSITY (nV/√Hz)
100
10
VS = ±15V TA = 25°C
9
VOLTAGE NOISE (AT 1kHz) (nV/√Hz)
0.1Hz to 10Hz Voltage Noise
10
1/f CORNER 30Hz
8 7 6 5 4 3 2 1
1 2
0
6 4 TIME (SEC)
8
1
10
10
100 1k FREQUENCY (Hz)
300
200 BIAS CURRENT 100 OFFSET CURRENT
V+
VS = ±15V
30 10 3 1 IB 0.3 IOS 0.1 0.03 100 125
1792 G22
60 40 20 0 100k 1M FREQUENCY (Hz)
4.0 3.5 3.0
10M 1792 G06
V – = – 5V TO – 20V
–20
60 100 20 TEMPERATURE (°C)
140 1792 G05
Voltage Gain vs Frequency 180
TA = 25°C
160
100
140
VOLTAGE GAIN (dB)
80
10k
–1.5
V –+ 2.0 – 60
120 POWER SUPPLY REJECTION RATIO (dB)
COMMON MODE REJECTION RATIO (dB)
TA = 25°C VS = ± 15V
V + = 5V TO 20V
– 2.0
Power Supply Rejection Ratio vs Frequency
120
1k
–1.0
1792 G04
Common Mode Rejection Ratio vs Frequency
100
0
– 0.5
2.5
0.01 – 75 – 50 – 25 0 25 50 75 TEMPERATURE (°C)
15
Common Mode Limit vs Temperature COMMON MODE LIMIT REFERRED TO POWER SUPPLY (V)
INPUT BIAS AND OFFSET CURRENT (nA)
INPUT BIAS AND OFFSET CURRENTS (pA)
100
10 –10 –5 0 5 COMMON-MODE RANGE (V)
1792 G03
Input Bias and Offset Current vs Chip Temperature
TA = 25°C VS = ±15V NOT WARMED UP
100 125
1792 G02
Input Bias and Offset Current Over the Common Mode Range
0 –15
0 –75 –50 –25 0 25 50 75 TEMPERATURE (°C)
10k
1792 G01
400
VS = ±15V
80 +PSRR 60 –PSRR 40
120 100 80 60 40 20
20
0
0
10
100
1k 10k 100k FREQUENCY (Hz)
1M
10M 1792 G07
– 20 0.01
1
10k 100 FREQUENCY (Hz)
1M
100M 1792 G08
5
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TYPICAL PERFOR A CE CHARACTERISTICS Gain and Phase Shift vs Frequency TA = 25°C VS = ±15V CL = 10pF
100 120
30
140
20 GAIN 10
160
0
180
1 10 FREQUENCY (MHz)
0.1
AV = 1 CL = 10pF VS = ±15V, ±5V
200 100
–10
5V/DIV
PHASE
PHASE SHIFT (DEG)
VOLTAGE GAIN (dB)
40
Large-Signal Transient Response
Small-Signal Transient Response 80
20mV/DIV
50
1µs/DIV
1792 G10
AV = 1 CL = 10pF RL = 2k VS = ±15V
1792 G11
5µs/DIV
1792 G09
Output Voltage Swing vs Load Current
40
–55°C
– 1.4 –1.6
OVERSHOOT (%)
VS = ±5V TO ±20V
2.0 1.8
125°C
1.6
30
20
10 –55°C
1.2
SR 6
3 GBWP
2
4
0 0.1
1
100 1000 10 CAPACITIVE LOAD (pF)
TOTAL HARMONIC DISTROTION + NOISE (%)
SO-8 PACKAGE 60 45 N8 PACKAGE 30 15
0
0 25 50 75 – 75 – 50 – 25 0 TEMPERATURE (°C)
5 2 3 4 1 TIME AFTER POWER ON (MINUTES)
6
1792 G15
0 100 125 1792 G14
THD and Noise vs Frequency for Noninverting Gain
VS = ±15V TA = 25°C
75
10000 1792 G13
Warm-Up Drift 90
2
AV = 10
1792 G12
CHANGE IN OFFSET VOLTAGE (µV)
8
4
1
25°C
V – +1.0 –10 –8 –6 –4 –2 0 2 4 6 8 10 ISINK ISOURCE OUTPUT CURRENT (mA)
6
10
AV = 1
1.4
0
12
VS = ± 15V
5
1
ZL = 2k 15pF VO = 20VP-P AV = 1, 10, 100 MEASUREMENT BANDWIDTH = 10Hz TO 80kHz
0.1
AV = 100
0.01
AV = 10
0.001
AV = 1
NOISE FLOOR
THD and Noise vs Frequency for Inverting Gain TOTAL HARMONIC DISTROTION + NOISE (%)
OUTPUT VOLTAGE SWING (V)
–1.2
6
VS = ±15V TA = 25°C RL ≥ 10k VO = 100mVP-P AV = 10 RF = 10k CF = 20pF
SLEW RATE (V/µs)
50 125°C
25°C
GAIN-BANDWIDTH PRODUCT (fO = 100kHz) (MHz)
V + – 0.8 –1.0
Slew Rate and Gain-Bandwidth Product vs Temperature
Capacitive Load Handling
1
ZL = 2k 15pF VO = 20VP-P AV = – 1, – 10, – 100 MEASUREMENT BANDWIDTH = 10Hz TO 80kHz
0.1
0.01
AV = – 100 AV = – 10
0.001
AV = – 1
NOISE FLOOR
0.0001
0.0001 20
100
1k FREQUENCY (Hz)
10k 20k 1792 G16
20
100
1k FREQUENCY (Hz)
10k 20k 1792 G17
LT1792 U W
TYPICAL PERFOR A CE CHARACTERISTICS THD and Noise vs Output Amplitude for Inverting Gain
1
TOTAL HARMONIC DISTORTION + NOISE (%)
TOTAL HARMONIC DISTORTION + NOISE (%)
THD and Noise vs Output Amplitude for Noninverting Gain ZL = 2k 15pF, fO = 1kHz AV = 1, 10, 100 MEASUREMENT BANDWIDTH = 10Hz TO 22kHz
0.1
AV = 100 0.01 AV = 10 0.001
AV = 1
0.0001 0.3
1 10 OUTPUT SWING (VP-P)
1 ZL = 2k 15pF, fO = 1kHz AV = – 1, – 10, – 100 MEASUREMENT BANDWIDTH = 10Hz TO 22kHz
0.1
AV = –100 0.01 AV = –10 0.001
AV = –1
0.0001
30
0.3
1 10 OUTPUT SWING (VP-P)
30
1792 G18
1792 G19
Short-Circuit Output Current vs Temperature 40
Supply Current vs Temperature 5
VS = ±15V
SUPPLY CURRENT (mA)
OUTPUT CURRENT (mA)
35 30 SINK
SOURCE
25 20
VS = ±15V 4
VS = ± 5V
15 10 – 75 – 50 – 25 0 25 50 75 TEMPERATURE (°C)
3 – 75 – 50 – 25 0 25 50 75 TEMPERATURE (°C)
100 125
100 125
1792 G20
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1792 G21
S I FOR ATIO
The LT1792 may be inserted directly into OPA124, AD743, AD745, AD645, AD544 and AD820 sockets with improved noise performance. Offset nulling will be compatible with these devices with the wiper of the potentiometer tied to the negative supply (Figure 1a). No appreciable change in offset voltage drift with temperature will occur when the device is nulled with a potentiometer ranging from 10k to 200k. Finer adjustments can be made with resistors in series with the potentiometer (Figure 1b). Being a low voltage noise JFET op amp, the LT1792 can replace many bipolar op amps that are used in amplifying low level signals from high impedance transducers. The
15V
15V 2
–
2
7
–
7 6
6 3
+
3
4 5
∆VOS = ±10mV
1
4 5
1792 F01a
∆VOS = ±1mV
1 10k
50k – 15V
+
10k
50k – 15V
(a)
1792 F01b
(b) Figure 1
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APPLICATI
1k
best bipolar op amps, with higher current noise, will eventually lose out to the LT1792 when transducer impedance increases. The low voltage noise of the LT1792 allows it to surpass most single JFET op amps available. For the best performance versus area available anywhere, the LT1792 is offered in the SO-8 surface mount package with no degradation in performance.
H z) INPUT NOISE VOLTAGE (nV/√
The low voltage and current noise offered by the LT1792 makes it useful in a wide range of applications, especially where high impedance, capacitive transducers are used such as hydrophones, precision accelerometers and photo diodes. The total output noise in such a system is the gain times the RMS sum of the op amp input referred voltage noise, the thermal noise of the transducer, and the op amp bias current noise times the transducer impedance. Figure 2 shows total input voltage noise versus source resistance. In a low source resistance (<5k) application the op amp voltage noise will dominate the total noise. This means the LT1792 will beat out any JFET op amp, only the lowest noise bipolar op amps have the edge at low source resistances. As the source resistance increases from 5k to 50k, the LT1792 will match the best bipolar op amps for noise performance, since the thermal noise of the transducer (4kTR) begins to dominate the total noise. A further increase in source resistance, above 50k, is where the op amp’s current noise component (2qIB RTRANS) will eventually dominate the total noise. At these high source resistances, the LT1792 will out perform the lowest noise bipolar op amp due to the inherently low
LT1007*
–
100
+
CS
LT1792†
10 LT1792 LT1007
RESISTOR NOISE ONLY
1 100
1k
10k 100k 1M 10M SOURCE RESISTANCE (Ω)
1792 F02
Vn = AV √Vn2(OP AMP) + 4kTR + 2qIB • R2
Figure 2. Comparison of LT1792 and LT1007 Total Output 1kHz Voltage Noise Versus Source Resistance
current noise of FET input op amps. Clearly, the LT1792 will extend the range of high impedance transducers that can be used for high signal-to-noise ratios. This makes the LT1792 the best choice for high impedance, capacitive transducers. The high input impedance JFET front end makes the LT1792 suitable in applications where very high charge sensitivity is required. Figure 3 illustrates the LT1792 in its inverting and noninverting modes of operation. A charge amplifier is shown in the inverting mode example; here the gain depends on the principal of charge conservation at RF CF
RB
–
–
R1
OUTPUT
+
RS
TRANSDUCER
CB ≅ CS RB = RS RS > R1 OR R2
100M
SOURCE RESISTANCE = 2RS = R * PLUS RESISTOR † PLUS RESISTOR 1000pF CAPACITOR
CB
CS
RS
+
TRANSDUCER
CB
RB
1792 F03
Figure 3. Noninverting and Inverting Gain Configurations
8
LT1007†
VO RS
R2
CS
LT1792*
CS RS
OUTPUT
CB = CF CS RB = RF RS dQ dV Q = CV; = I = C dt dt
LT1792
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the input of the LT1792. The charge across the transducer capacitance, CS, is transferred to the feedback capacitor CF, resulting in a change in voltage, dV, equal to dQ/CF. The gain therefore is CF/CS. For unity gain, the CF should equal the transducer capacitance plus the input capacitance of the LT1792 and RF should equal RS. In the noninverting mode example, the transducer current is converted to a change in voltage by the transducer capacitance; this voltage is then buffered by the LT1792 with a gain of 1 + R1/R2. A DC path is provided by RS, which is either the transducer impedance or an external resistor. Since RS is usually several orders of magnitude greater than the parallel combination of R1 and R2, RB is added to balance the DC offset caused by the noninverting input bias current and RS. The input bias currents, although small at room temperature, can create significant errors at higher temperature, especially with transducer resistances of up to 100M or more. The optimum value for RS is determined by equating the thermal noise (4kTRS) to the current noise times RS, [(2qIB) • RS], resulting in RB = 2VT/IB (VT = 26mV at 25°C). A parallel capacitor, CB, is used to cancel the phase shift caused by the op amp input capacitance and RB. Reduced Power Supply Operation
expense of reduced dynamic range. To illustrate this benefit, let’s take the following example: An LT1792CS8 operates at an ambient temperature of 25°C with ±15V supplies, dissipating 159mW of power (typical supply current = 5.3mA). The SO-8 package has a θJA of 190°C/W, which results in a die temperature increase of 30.2°C or a room temperature die operating temperature of 55.2°C. At ±5V supplies, the die temperature increases by only one third of the previous amount or 10.1°C resulting in a typical die operating temperature of only 35.1°C. A 20 degree reduction of die temperature is achieved at the expense of a 20V reduction in dynamic range. To take full advantage of a wide input common mode range, the LT1792 was designed to eliminate phase reversal. Referring to the photographs shown in Figure 4, the LT1792 is shown operating in the follower mode (AV = 1) at ±5V supplies with the input swinging ±5.2V. The output of the LT1792 clips cleanly and recovers with no phase reversal. This has the benefit of preventing lock-up in servo systems and minimizing distortion components. High Speed Operation
The LT1792 can be operated from ±5V supplies for lower power dissipation resulting in lower IB and noise at the
The low noise performance of the LT1792 was achieved by making the input JFET differential pair large to maximize the first stage gain. Increasing the JFET geometry
INPUT: ±5.2V Sine Wave
LT1792 Output
1792 F04a
1792 F03b
Figure 4. Voltage Follower with Input Exceeding the Common Mode Range ( VS = ±5V)
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CF
also increases the parasitic gate capacitance, which if left unchecked, can result in increased overshoot and ringing. When the feedback around the op amp is resistive (RF), a pole will be created with RF, the source resistance and capacitance (RS, CS), and the amplifier input capacitance (CIN = 27pF). In low gain configurations and with RS and RF in the kilohm range (Figure 5), this pole can create excess phase shift and even oscillation. A small capacitor (CF) in parallel with RF eliminates this problem. With RS(CS + CIN) = RFCF, the effect of the feedback pole is completely removed.
RF
–
RS
CIN
+
CS
OUTPUT
1792 F05
Figure 5
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TYPICAL APPLICATI
S Accelerometer Amplifier with DC Servo C1 1250pF
R1 100M
C2 2µF
R3 2k
R2 18k
– 6
+
2
–
3
R5 20M
R4C2 = R5C3 > R1 (1 + R2/R3) C1 OUTPUT = 0.8mV/pC* = 8.0mV/g** DC OUTPUT ≤ 2.7mV OUTPUT NOISE = 6nV/√ Hz AT 1kHz *PICOCOULOMBS **g = EARTH’S GRAVITATIONAL CONSTANT
C3 2µF
7 6
LT1792
3
R4 20M
LT1792
5V TO 15V ACCELEROMETER B & K MODEL 4381 OR EQUIVALENT
2
OUTPUT
+
1792 TA03
4 – 5V TO –15V
10Hz Fourth Order Chebyshev Lowpass Filter (0.01dB Ripple) C1 33nF
R2 237k
R1 237k
R3 249k
VIN C2 100nF
C3 10nF
R5 154k 15V 2
–
7 LT1792
3
6
R4 154k
R6 249k
2
–
C4 330nF
3
+
+
4
LT1792
6
VOUT
–15V TYPICAL OFFSET ≈ 0.8mV 1% TOLERANCES FOR VIN = 10VP-P, VOUT = –121dB AT f > 330Hz = – 6dB AT f = 16.3Hz LOWER RESISTOR VALUES WILL RESULT IN LOWER THERMAL NOISE AND LARGER CAPACITORS
10
1792 TA06
LT1792 UO
TYPICAL APPLICATI
S Low Noise Light Sensor with DC Servo C1 2pF R1 1M 2
–
3
+
6
LT1792
OUTPUT
C2 0.022µF
D2 1N914 V+ R3 1k
2N3904
R5 1k
HAMAMATSU S1336-5BK
7 6
2
+
D1 1N914
–
CD
3
R2 100k
LT1792 4
R4 1k
V–
R2C2 > C1R1 CD = PARASITIC PHOTODIODE CAPACITANCE VO = 100mV/µWATT FOR 200nm WAVE LENGTH 330mV/µWATT FOR 633nm WAVE LENGTH
V–
1792 TA05
Paralleling Amplifiers to Reduce Voltage Noise
3
2
+ 6
An LT1792
1k
–
51Ω
1k 10k 3
2
15V
+ 6
A2 LT1792
1k
2
–
3
+
–
7 LT1792
1k
51Ω
6
OUTPUT
4
15V –15V 3
2
+
7 6
A1 LT1792
–
4 –15V
51Ω
1k
1k
1. ASSUME VOLTAGE NOISE OF LT1792 AND 51Ω SOURCE RESISTOR = 4.3nV/√ H z 2. GAIN WITH n LT1792s IN PARALLEL = n × 200 3. OUTPUT NOISE = √ n × 200 × 4.3nV/√ H z OUTPUT NOISE 4.3 4. INPUT REFERRED NOISE = = nV/√ Hz n × 200 √n 5. NOISE CURRENT AT INPUT INCREASES √ 1792 TA04 n TIMES
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1792 UO
TYPICAL APPLICATI
S
Light Balance Detection Circuit
I1
Unity-Gain Buffer with Extended Load Capacitance Drive Capability
R1 1M
R2 1k
C1 2pF TO 8pF
C1
–
PD1
–
I2
VOUT
LT1792
+
+
VIN
VOUT
LT1792
PD2
R1 33Ω CL 1792 TA08
C1 = CL ≤ 0.1µF OUTPUT SHORT-CIRCUIT CURRENT (∼ 30mA) WILL LIMIT THE RATE AT WHICH THE VOLTAGE CAN CHANGE ACROSS LARGE CAPACITORS
1792 TA07
VOUT = 1M × (I1 – I2) PD1,PD2 = HAMAMATSU S1336-5BK WHEN EQUAL LIGHT ENTERS PHOTODIODES, VOUT < 3mV.
I=C
U
PACKAGE DESCRIPTIO
( ) dV dt
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package 8-Lead PDIP (Narrow 0.300)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1510)
(LTC DWG # 05-08-1610)
0.400* (10.160) MAX 8
7
6
8
(
+0.035 0.325 –0.015 +0.889 8.255 –0.381
)
0.150 – 0.157** (3.810 – 3.988)
0.228 – 0.244 (5.791 – 6.197)
1
0.009 – 0.015 (0.229 – 0.381)
5
5
0.255 ± 0.015* (6.477 ± 0.381)
0.300 – 0.325 (7.620 – 8.255)
0.189 – 0.197* (4.801 – 5.004) 7 6
2
3
4 0.130 ± 0.005 (3.302 ± 0.127)
0.045 – 0.065 (1.143 – 1.651)
0.008 – 0.010 (0.203 – 0.254)
0.065 (1.651) TYP
0.100 ± 0.010 (2.540 ± 0.254)
1 0.010 – 0.020 × 45° (0.254 – 0.508)
0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1197
2
3
4
0.053 – 0.069 (1.346 – 1.752)
0.004 – 0.010 (0.101 – 0.254)
0°– 8° TYP
0.016 – 0.050 0.406 – 1.270
0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.050 (1.270) TYP SO8 0996
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
RELATED PARTS PART NUMBER
DESCRIPTION
LT1113
Low Noise Dual JFET Op Amp
Dual Version of LT1792, VNOISE = 4.5nV/√Hz
LT1169
Low Noise Dual JFET Op Amp
Dual Version of LT1793, IB = 10pA, VNOISE = 6nV/√Hz
LT1793
Low Noise Single Op Amp
Lower IB Version of LT1792, IB = 10pA, VNOISE = 6nV/√Hz
12
Linear Technology Corporation
COMMENTS
1792f LTTP 0599 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1999
