Transcript
1.8 V, Micropower, Zero-Drift, Rail-to-Rail Input/Output Op Amps ADA4051-1/ADA4051-2
Data Sheet
PIN CONFIGURATIONS
Very low supply current: 13 μA typical Low offset voltage: 15 μV maximum Offset voltage drift: 20 nV/°C Single-supply operation: 1.8 V to 5.5 V High PSRR: 110 dB minimum High CMRR: 110 dB minimum Rail-to-rail input/output Unity-gain stable Extended industrial temperature range
OUT 1 V– 2
ADA4051-1
5
V+
4
–IN
TOP VIEW (Not to Scale)
+IN 3
08056-064
FEATURES
+IN 1 V– 2
APPLICATIONS
ADA4051-1
V+
4
OUT
TOP VIEW (Not to Scale)
–IN 3
Pressure and position sensors Temperature measurements Electronic scales Medical instrumentation Battery-powered equipment Handheld test equipment
5
08056-066
Figure 1. 5-Lead SOT-23 (RJ-5)
OUT A 1
8
V+
–IN A 2
ADA4051-2
7
OUT B
+IN A 3
TOP VIEW (Not to Scale)
6
–IN B
5
+IN B
V– 4
08056-001
Figure 2. 5-Lead SC-70 (KS-5)
Figure 3. 8-Lead MSOP (RM-8) OUT A 1
+IN A 3
ADA4051-2 TOP VIEW (Not to Scale)
7 OUT B 6 –IN B 5 +IN B
V– 4
NOTES 1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED TO V–.
08056-065
–IN A 2
8 V+
Figure 4. 8-Lead LFCSP (CP-8-13)
GENERAL DESCRIPTION The ADA4051-1/ADA4051-2 are CMOS, micropower, zerodrift operational amplifiers utilizing an innovative chopping technique. These amplifiers feature rail-to-rail input/output swing and extremely low offset voltage while operating from a 1.8 V to 5.5 V power supply. In addition, these amplifiers offer high power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) while operating with a typical supply current of 13 μA per amplifier. This combination of features makes the ADA4051-1/ADA4051-2 amplifiers ideal choices for battery-powered applications where high precision and low power consumption are important.
Rev. C
The ADA4051-1/ADA4051-2 are specified for the extended industrial temperature range of −40°C to +125°C. The ADA4051-1 amplifier is available in 5-lead SOT-23 and 5-lead SC-70 packages. The ADA4051-2 amplifier is available in an 8-lead MSOP and an 8-lead LFCSP. The ADA4051-1/ADA4051-2 are members of a growing series of zero-drift op amps offered by Analog Devices, Inc. Refer to Table 1 for a list of these devices. Table 1. Op Amps Supply Single Dual Quad
Low Power, 5 V AD8538 AD8539
5V AD8628 AD8629 AD8630
16 V AD8638 AD8639
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ADA4051-1/ADA4051-2
Data Sheet
TABLE OF CONTENTS Features .............................................................................................. 1
Thermal Resistance .......................................................................7
Applications ....................................................................................... 1
Power Sequencing .........................................................................7
Pin Configurations ........................................................................... 1
ESD Caution...................................................................................7
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................8
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 17
Specifications..................................................................................... 3
Input Voltage Range ................................................................... 18
Electrical Characteristics—1.8 V Operation ............................ 3
Output Phase Reversal ............................................................... 18
Electrical Characteristics—5 V Operation................................ 5
Outline Dimensions ....................................................................... 19
Absolute Maximum Ratings............................................................ 7
Ordering Guide .......................................................................... 20
REVISION HISTORY 3/16—Rev. B to Rev. C Changed CP-8-2 to CP-8-13 ........................................ Throughout Changes to Figure 4 .......................................................................... 1 Changes to Offset Voltage Parameter and Input Resistance Parameter, Table 2............................................................................. 3 Changes to Offset Voltage Parameter and Input Resistance Parameter, Table 3............................................................................. 5 Changes to Table 5 ............................................................................ 7 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 1/10—Rev. A to Rev. B Added ADA4051-1, 5-Lead SC-70 Package .................... Universal Added Figure 2; Renumbered Sequentially .................................. 1 Changes to Figure 4 and General Description Section ............... 1 Changes to Electrical Characteristics—1.8 V Operation Section and Table 2 ......................................................................................... 3 Changes to Electrical Characteristics—5 V Operation Section and Table 3 ......................................................................................... 4 Changes to Table 5 ............................................................................ 5 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 18
10/09—Rev. 0 to Rev. A Added ADA4051-1, 5-Lead SOT-23 Package ................. Universal Added ADA4051-2, 8-Lead LFCSP Package .................. Universal Changes to the Features and General Description Section, Added Figure 1 and Figure 3............................................................1 Moved Electrical Characteristics—1.8 V Operation Section .....3 Changes to Offset Voltage Parameter and Supply Current per Amplifier Parameter, Table 2 ...........................................................3 Moved Electrical Characteristics—5 V Operation Section .........4 Changes to Offset Voltage Parameter and Supply Current per Amplifier Parameter, Table 2 ...........................................................4 Changes to Thermal Resistance Section and Table 5 ...................5 Changes to Figure 22 and Figure 25................................................9 Changes to Theory of Operation Section.................................... 15 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 18 7/09—Revision 0: Initial Version
Rev. C | Page 2 of 22
Data Sheet
ADA4051-1/ADA4051-2
SPECIFICATIONS ELECTRICAL CHARACTERISTICS—1.8 V OPERATION VSY = 1.8 V, VCM = VSY/2 V, TA = 25°C, RL = 100 kΩ to GND, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage ADA4051-2 ADA4051-1
Symbol
Offset Voltage Drift Input Bias Current
∆VOS/∆T IB
Input Offset Current
IOS
Test Conditions/Comments
Min
Typ
Max
Unit
2 2
15 17 27 0.1 50 200 100 150 1.8
µV µV µV µV/°C pA pA pA pA V dB dB dB
VOS 0 V ≤ VCM ≤ 1.8 V 0 V ≤ VCM ≤ 1.8 V −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C
0.02 5
−40°C ≤ TA ≤ +125°C
Input Voltage Range Common-Mode Rejection Ratio
CMRR
Large-Signal Voltage Gain
AVO
Input Resistance Differential Mode Common Mode Input Capacitance, Differential Mode Input Capacitance, Common Mode OUTPUT CHARACTERISTICS Output Voltage High
Output Voltage Low
Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier ADA4051-2 ADA4051-1 DYNAMIC PERFORMANCE Slew Rate
10 −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C 0 V ≤ VCM ≤ 1.8 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ to VCM, 0.1 V ≤ VOUT ≤ VSY − 0.1 V −40°C ≤ TA ≤ +125°C
0 105 100 106
VOL
ISC ZOUT PSRR
130
100
RINDM RINCM CINDM CINCM VOH
125
RL = 100 kΩ to VCM −40°C ≤ TA ≤ +125°C RL = 10 kΩ to VCM −40°C ≤ TA ≤ +125°C RL = 100 kΩ to VCM −40°C ≤ TA ≤ +125°C RL = 10 kΩ to VCM −40°C ≤ TA ≤ +125°C VOUT = VSY or GND f = 1 kHz, G = 10
1.796 1.79 1.76 1.7
1.8 V ≤ VSY ≤ 5.5 V −40°C ≤ TA ≤ +125°C
110 106
dB 8 250 2 5
MΩ GΩ pF pF
1.799
V V V V mV mV mV mV mA Ω
1.796 1 3
3 9 20 40
13 1 135
dB dB
ISY
Settling Time
SR+ SR− tS
Gain Bandwidth Product Phase Margin Channel Separation
GBP ΦM CS
VOUT = VSY/2 VOUT = VSY/2 −40°C ≤ TA ≤ +125°C
13 15
RL = 10 kΩ, CL = 100 pF, G = 1 RL = 10 kΩ, CL = 100 pF, G = 1 To 0.1%, VIN = 1 V p-p, RL = 10 kΩ, CL = 100 pF CL = 100 pF, G = 1 CL = 100 pF, G = 1 VIN = 1.7 V, f = 100 Hz
0.04 0.03 120
V/µs V/µs µs
115 40 140
kHz Degrees dB
Rev. C | Page 3 of 22
17 18 20
µA µA µA
ADA4051-1/ADA4051-2 Parameter NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
Data Sheet Symbol
Test Conditions/Comments
en p-p en in
f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz
Rev. C | Page 4 of 22
Min
Typ 1.96 95 100
Max
Unit µV p-p nV/√Hz fA/√Hz
Data Sheet
ADA4051-1/ADA4051-2
ELECTRICAL CHARACTERISTICS—5 V OPERATION VSY = 5.0 V, VCM = VSY/2 V, TA = 25°C, RL = 100 kΩ to GND, unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage ADA4051-2 ADA4051-1
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
2 2
15 17 27 0.1 70 200 100 150 5
µV µV µV µV/°C pA pA pA pA V dB dB dB
VOS
Offset Voltage Drift Input Bias Current
∆VOS/∆T IB
Input Offset Current
IOS
0 V ≤ VCM ≤ 5 V 0 V ≤ VCM ≤ 5 V −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C
0.02 20
−40°C ≤ TA ≤ +125°C
Input Voltage Range Common-Mode Rejection Ratio
CMRR
Large-Signal Voltage Gain
AVO
Input Resistance Differential Mode Common Mode Input Capacitance, Differential Mode Input Capacitance, Common Mode OUTPUT CHARACTERISTICS Output Voltage High
Output Voltage Low
Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier ADA4051-2 ADA4051-1 DYNAMIC PERFORMANCE Slew Rate
40 −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C 0 V ≤ VCM ≤ 5 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ to VCM, 0.1 V ≤ VOUT ≤ VSY − 0.1 V −40°C ≤ TA ≤ +125°C
0 110 106 115
VOL
ISC ZOUT PSRR
135
106
RINDM RINCM CINDM CINCM VOH
135
RL = 100 kΩ to VCM −40°C ≤ TA ≤ +125°C RL = 10 kΩ to VCM −40°C ≤ TA ≤ +125°C RL = 100 kΩ to VCM −40°C ≤ TA ≤ +125°C RL = 10 kΩ to VCM −40°C ≤ TA ≤ +125°C VOUT = VSY or GND f = 1 kHz, G = 10
4.996 4.985 4.96 4.9
1.8 V ≤ VSY ≤ 5.5 V −40°C ≤ TA ≤ +125°C
110 106
dB 8 250 2 5
MΩ GΩ pF pF
4.998
V V V V mV mV mV mV mA Ω
4.99 1 9
4 13 30 90
15 1 135
dB dB
ISY
Settling Time
SR+ SR− tS
Gain Bandwidth Product Phase Margin Channel Separation
GBP ΦM CS
VOUT = VSY/2 VOUT = VSY/2 −40°C ≤ TA ≤ +125°C
13 15
RL = 10 kΩ, CL = 100 pF, G = 1 RL = 10 kΩ, CL = 100 pF, G = 1 To 0.1%, VIN = 1 V p-p, RL = 10 kΩ, CL = 100 pF CL = 100 pF, G = 1 CL = 100 pF, G = 1 VIN = 4.99 V, f = 100 Hz
0.06 0.04 110
V/µs V/µs µs
125 40 140
kHz Degrees dB
Rev. C | Page 5 of 22
17 18 20
µA µA µA
ADA4051-1/ADA4051-2 Parameter NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
Data Sheet Symbol
Test Conditions/Comments
en p-p en in
f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz
Rev. C | Page 6 of 22
Min
Typ 1.96 95 100
Max
Unit µV p-p nV/√Hz fA/√Hz
Data Sheet
ADA4051-1/ADA4051-2
ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE
Table 4. Parameter Supply Voltage Input Voltage Input Current1 Differential Input Voltage2 Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec)
θJA is specified for the worst-case conditions, that is, a device soldered on a circuit board for surface-mount packages with its exposed paddle soldered to a pad, if applicable. Table 5 shows simulated thermal values for a 4-layer (2S2P) JEDEC standard thermal test board, unless otherwise specified.
Rating 6V ±VSY ± 0.3 V ±10 mA ±VSY Indefinite −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C
Table 5. Thermal Resistance
The input pins have clamp diodes to the power supply pins. Limit the input current to 10 mA or less whenever input signals exceed the power supply rail by 0.3 V. 2 Inputs are protected against high differential voltages by internal series 1.33 kΩ resistors and back-to-back diode-connected N-MOSFETs (with a typical VT of 0.7 V for VCM of 0 V). 1
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Package Type 5-Lead SOT-23 (RJ-5) 5-Lead SC-70 (KS-5) 8-Lead MSOP (RM-8) 8-Lead LFCSP (CP-8-13) 1-Layer JEDEC Board 2-Layer JEDEC Board 2-Layer JEDEC Board with 2 × 2 Vias
θJA 190 534 142
Unit °C/W °C/W °C/W
272 145 55
°C/W °C/W °C/W
POWER SEQUENCING The op amp supplies must be established simultaneously with or before any input signals are applied. If this is not possible, the input current must be limited to 10 mA.
ESD CAUTION
Rev. C | Page 7 of 22
ADA4051-1/ADA4051-2
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 300
300 VSY = 5V VCM = VSY/2
VSY = 1.8V VCM = VSY/2 250
NUMBER OF AMPLIFIERS
200
150
100
200
150
100
50
50
–10
–8
–6
–4
–2
0
2
4
6
8
0
08056-002
0 10
VOS (µV)
–10
–8
–6
–4
–2
0
2
4
6
8
10
08056-005
NUMBER OF AMPLIFIERS
250
VOS (µV)
Figure 5. Input Offset Voltage Distribution
Figure 8. Input Offset Voltage Distribution
8
10
VSY = 5V –40°C ≤ TA ≤ 125°C
VSY = 1.8V –40°C ≤ TA ≤ +125°C
6
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
8
6
4
4
2
2
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
TCVOS (µV/°C)
0
08056-003
0
TCVOS (µV/°C)
Figure 6. Input Offset Voltage Drift Distribution with Temperature
Figure 9. Input Offset Voltage Drift Distribution with Temperature
15
15
VSY = 1.8V
VSY = 5V 10
5
5
VOS (µV)
10
0 DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5 DEVICE 6 DEVICE 7 DEVICE 8 DEVICE 9 DEVICE 10
–5
–10
0 DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5 DEVICE 6 DEVICE 7 DEVICE 8 DEVICE 9 DEVICE 10
–5
–10
–15 0.3
0.6
0.9
1.2
1.5
1.8
VCM (V)
0
1
2
3
4
5
VCM (V)
Figure 7. Input Offset Voltage vs. Input Common-Mode Voltage
Figure 10. Input Offset Voltage vs. Input Common-Mode Voltage
Rev. C | Page 8 of 22
08056-007
–15
0
08056-004
VOS (µV)
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
08056-006
0
Data Sheet
ADA4051-1/ADA4051-2
TA = 25°C, unless otherwise noted. 100
100 IB+
VSY = 5V
IB+
80
60
60
IB (pA)
80
40
20
0
0
–20 25
50
75
100
125
TEMPERATURE (°C)
IB–
40
20
–20
08056-008
25
50
Figure 11. Input Bias Current vs. Temperature
125
400
VSY = 1.8V
VSY = 5V
150
300
100
200
50
100
IB (pA)
0 –50
0 –100
IB+, 25°C IB–, 25°C IB+, 85°C IB–, 85°C IB+, 125°C IB–, 125°C
–100 –150
–300
–200 0.3
0.6
0.9
1.2
1.5
1.8
VCM (V)
–400
08056-009
0
100
10
1
0.1
1
10
LOAD CURRENT (mA)
08056-010
–40°C +25°C +85°C +125°C
0.01
1.5
2.5
2.0
3.0
3.5
4.0
4.5
5.0
Figure 15. Input Bias Current vs. Common-Mode Voltage and Temperature
OUTPUT VOLTAGE (VOH) TO SUPPLY RAIL (mV)
1000
0.01 0.001
1.0
VCM (V)
VSY = 1.8V
0.1
0.5
0
Figure 12. Input Bias Current vs. Common-Mode Voltage and Temperature
10,000
IB+, 25°C IB–, 25°C IB+, 85°C IB–, 85°C IB+, 125°C IB–, 125°C
–200
08056-012
IB (pA)
100
Figure 14. Input Bias Current vs. Temperature
200
OUTPUT VOLTAGE (VOH) TO SUPPLY RAIL (mV)
75 TEMPERATURE (°C)
Figure 13. Output Voltage (VOH) to Supply Rail vs. Load Current and Temperature
10,000 VSY = 5V
1000
100
10
1
0.1
0.01 0.001
–40°C +25°C +85°C +125°C
0.01
0.1
1
10
100
LOAD CURRENT (mA)
Figure 16. Output Voltage (VOH) to Supply Rail vs. Load Current and Temperature
Rev. C | Page 9 of 22
08056-013
IB (pA)
IB–
08056-011
VSY = 1.8V
ADA4051-1/ADA4051-2
Data Sheet
TA = 25°C, unless otherwise noted. 10,000
1000
100
10
1
0.1
–40°C +25°C +85°C +125°C
0.01 0.001
1
0.1
0.01
10
100
LOAD CURRENT (mA)
VSY = 5V
1000
100
10
1
–40°C +25°C +85°C +125°C
0.1
0.01 0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
Figure 17. Output Voltage (VOL) to Supply Rail vs. Load Current and Temperature
08056-017
OUTPUT VOLTAGE (VOL) TO SUPPLY RAIL (mV)
VSY = 1.8V
08056-014
OUTPUT VOLTAGE (VOL) TO SUPPLY RAIL (mV)
10,000
Figure 20. Output Voltage (VOL) to Supply Rail vs. Load Current and Temperature
5000
1800 RL = 100kΩ
RL = 100kΩ
4998
OUTPUT VOLTAGE [VOH] (mV)
OUTPUT VOLTAGE [VOH] (mV)
1799
1798
1797
RL = 10kΩ
1796
4996 4994 4992 RL = 10kΩ
4990 4988 4986
1795
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
50
65
80
95
110
125
125
14
VSY = 1.8V VCM = VSY/2
VSY = 5V VCM = VSY/2
OUTPUT VOLTAGE [VOL] (mV)
12
10 8 6 4
RL = 10kΩ
2
10 RL = 10kΩ
8 6 4 2
RL = 100kΩ
–25
–10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
125
08056-016
RL = 100kΩ 0 –40
35
Figure 21. Output Voltage (VOH) vs. Temperature
12
OUTPUT VOLTAGE [VOL] (mV)
20
TEMPERATURE (°C)
Figure 18. Output Voltage (VOH) vs. Temperature
14
5
08056-018
–25
VSY = 5V VCM = VSY/2 4982 –40 –25 –10
08056-015
1794 –40
08056-019
4984
VSY = 1.8V VCM = VSY/2
Figure 19. Output Voltage (VOL) vs. Temperature
0 –40
–25
–10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
Figure 22. Output Voltage (VOL) vs. Temperature
Rev. C | Page 10 of 22
Data Sheet
ADA4051-1/ADA4051-2
TA = 25°C, unless otherwise noted. 30
30
VCM = VSY/2
ADA4051-2 ADA4051-1 25
TOTAL SUPPLY CURRENT (µA)
15
10
20
15
10 ADA4051-2, ADA4051-2, ADA4051-1, ADA4051-1,
5
5 VCM = VSY/2 1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
0 –40
OPEN-LOOP GAIN (dB)
PHASE
45
0
0
PHASE (Degrees)
90
180 VSY = 5V CL= 100pF
40
135 90
PHASE
20
45
GAIN
0
0
–90
–135
–60 100
08056-022
1M
–135 1k
100k
10k
1M
FREQUENCY (Hz)
Figure 24. Open-Loop Gain and Phase vs. Frequency
Figure 27. Open-Loop Gain and Phase vs. Frequency
50
50 VSY = 1.8V RL = 10kΩ CL = 50pF
VSY = 5V RL = 10kΩ CL = 50pF
40 30
CLOSED-LOOP GAIN (dB)
30 20 10 0 –10 –20
20 10 0 –10 –20 –30
–30 G=1 G = 10 G = 100
–40
1k
10k
100k
FREQUENCY (Hz)
1M
–50 100
08056-061
–50 100
125
110
–40
FREQUENCY (Hz)
40
95
–90
–40
–40
80
65
–45
–45
100k
50
–20
–20
10k
35
60
135
GAIN
CLOSED-LOOP GAIN (dB)
OPEN-LOOP GAIN (dB)
40
1k
20
80
180 VSY = 1.8V CL= 100pF
–60 100
5
Figure 26. Total Supply Current vs. Temperature
80
20
–10
TEMPERATURE (°C)
Figure 23. Total Supply Current vs. Supply Voltage
60
–25
PHASE (Degrees)
0.5
08056-025
0
08056-020
0
1.8V 5V 1.8V 5V 08056-023
20
G=1 G = 10 G = 100 1k
10k
100k
FREQUENCY (Hz)
Figure 28. Closed-Loop Gain vs. Frequency
Figure 25. Closed-Loop Gain vs. Frequency
Rev. C | Page 11 of 22
1M
08056-062
TOTAL SUPPLY CURRENT (µA)
25
ADA4051-1/ADA4051-2
Data Sheet
TA = 25°C, unless otherwise noted. 10k
10k VSY = 5V
1k
1k
100
100
ZOUT (Ω)
10
1
10
1
10k
1M
100k
FREQUENCY (Hz)
0.1 1k
08056-026
0.1 1k
G = −1 G = −10 G = −100 10k
100k
1M
FREQUENCY (Hz)
Figure 29. Output Impedance vs. Frequency
Figure 32. Output Impedance vs. Frequency
110
110
VSY = 5V 100
90
90
80
70
80
70
60
60
50
50
100
1k
10k
100k
1M
FREQUENCY (Hz)
40 10
100
1k
10k
100k
Figure 30. CMRR vs. Frequency
Figure 33. CMRR vs. Frequency
120
120 VSY = 5V
100
80
80
PSRR (dB)
100
60 PSRR+
40
60 PSRR+
40
20
20 PSRR– 1k
10k
PSRR– 100k
FREQUENCY (Hz)
1M
08056-028
PSRR (dB)
VSY = 1.8V
0 100
1M
FREQUENCY (Hz)
08056-030
CMRR (dB)
100
08056-027
CMRR (dB)
VSY = 1.8V
40 10
08056-029
G = −1 G = −10 G = −100
Figure 31. PSRR vs. Frequency
0 100
1k
10k
100k
FREQUENCY (Hz)
Figure 34. PSRR vs. Frequency
Rev. C | Page 12 of 22
1M
08056-031
ZOUT (Ω)
VSY = 1.8V
Data Sheet
ADA4051-1/ADA4051-2
TA = 25°C, unless otherwise noted. VSY = ±2.5V VIN = 50mV p-p RL = 10kΩ CL= 50pF
50
40
OVERSHOOT (%)
30
20
40
−OVERSHOOT 30
20
−OVERSHOOT
+OVERSHOOT
+OVERSHOOT
10
0 10
08056-032
0 10
100 LOAD CAPACITANCE (pF)
08056-035
10
100
LOAD CAPACITANCE (pF)
Figure 35. Small-Signal Overshoot vs. Load Capacitance
Figure 38. Small-Signal Overshoot vs. Load Capacitance
VSY = 1.8V RL = 10kΩ CL = 100pF G=1 VIN = 1.5V p-p
08056-033
VOLTAGE (1V/DIV)
VOLTAGE (500mV/DIV)
VSY = 5V RL = 10kΩ CL = 100pF G=1 VIN = 4V p-p
TIME (100µs/DIV)
08056-036
OVERSHOOT (%)
50
60
VSY = ±0.9V VIN = 50mV p-p RL = 10kΩ CL= 50pF
TIME (100µs/DIV)
Figure 39. Large-Signal Transient Response
Figure 36. Large-Signal Transient Response
VSY = 5V RL = 10kΩ CL = 100pF G=1 VIN = 50mV p-p
TIME (100µs/DIV)
08056-034
VOLTAGE (10mV/DIV)
VOLTAGE (10mV/DIV)
VSY = 1.8V RL = 10kΩ CL = 100pF G=1 VIN = 50mV p-p
TIME (100µs/DIV)
Figure 37. Small-Signal Transient Response
Figure 40. Small-Signal Transient Response
Rev. C | Page 13 of 22
08056-037
60
ADA4051-1/ADA4051-2
Data Sheet
TA = 25°C, unless otherwise noted. VSY = 5V INPUT VOLTAGE NOISE (0.5µV/DIV)
TIME (4s/DIV)
TIME (4s/DIV)
Figure 41. Input Voltage Noise, 0.1 Hz to 10 Hz
Figure 44. Input Voltage Noise, 0.1 Hz to 10 Hz 1k
VSY = 1.8V
100
10
100
1k
10k
FREQUENCY (Hz)
10
1 10
INPUT VOLTAGE 0 0.5 0 –0.5
INPUT VOLTAGE (100mV/DIV)
0.05
VSY = ±2.5V G = –10
0.3
OUTPUT VOLTAGE (500mV/DIV)
0.2 0.1 INPUT VOLTAGE
0
OUTPUT VOLTAGE
–0.1
TIME (40µs/DIV)
–1.5
1 0 –1
–1.0
–2 08056-040
INPUT VOLTAGE (50mV/DIV)
0.4
VSY = ±0.9V G = –10
OUTPUT VOLTAGE
10k
Figure 45. Voltage Noise Density vs. Frequency
0.15
–0.05
1k
FREQUENCY (Hz)
Figure 42. Voltage Noise Density vs. Frequency
0.10
100
OUTPUT VOLTAGE (1V/DIV)
1 10
100
08056-042
VOLTAGE NOISE DENSITY (nV/√Hz)
VSY = 5V
08056-039
VOLTAGE NOISE DENSITY (nV/√Hz)
1k
08056-041
1.96µV p-p
08056-038
1.94µV p-p
Figure 43. Positive Overload Recovery
TIME (40µs/DIV)
Figure 46. Positive Overload Recovery
Rev. C | Page 14 of 22
–3
08056-043
INPUT VOLTAGE NOISE (0.5µV/DIV)
VSY = 1.8V
Data Sheet
ADA4051-1/ADA4051-2
TA = 25°C, unless otherwise noted. 0.05
0.1
1.5
–0.15
1.0 0.5 OUTPUT VOLTAGE
–0.1 –0.2
4
–0.3
3
–0.4
2 1 OUTPUT VOLTAGE
0 –0.5
TIME (40µs/DIV)
Figure 50. Negative Overload Recovery
ERROR BAND
VSY = ±2.5V VIN = 1V p-p RL = 10kΩ CL = 100pF
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 49. Negative Settling Time to 0.1%
5 OUTPUT VOLTAGE
ERROR BAND
0 –5 VSY = ±2.5V VIN = 1V p-p RL = 10kΩ CL = 100pF TIME (40µs/DIV)
Figure 52. Negative Settling Time to 0.1%
Rev. C | Page 15 of 22
OUTPUT VOLTAGE (5mV/DIV)
INPUT VOLTAGE
08056-049
–5
INPUT VOLTAGE (500mV/DIV)
0
08056-046
5
OUTPUT VOLTAGE (5mV/DIV)
Figure 51. Positive Settling Time to 0.1%
INPUT VOLTAGE
VSY = ±0.9V VIN = 1V p-p RL = 10kΩ CL = 100pF
–5
TIME (40µs/DIV)
Figure 48. Positive Settling Time to 0.1%
OUTPUT VOLTAGE
0
OUTPUT VOLTAGE (5mV/DIV)
–5 VSY = ±0.9V VIN = 1V p-p RL = 10kΩ CL = 100pF
5 OUTPUT VOLTAGE
08056-048
0
INPUT VOLTAGE (500mV/DIV)
5 OUTPUT VOLTAGE
OUTPUT VOLTAGE (5mV/DIV)
INPUT VOLTAGE
08056-045
INPUT VOLTAGE (500mV/DIV)
INPUT VOLTAGE
ERROR BAND
–1
TIME (40µs/DIV)
Figure 47. Negative Overload Recovery
ERROR BAND
0
VSY = ±2.5V G = –10
08056-044
VSY = ±0.9V G = –10
INPUT VOLTAGE OUTPUT VOLTAGE (1V/DIV)
–0.10
INPUT VOLTAGE (100mV/DIV)
OUTPUT VOLTAGE (500mV/DIV)
–0.05
INPUT VOLTAGE (500mV/DIV)
INPUT VOLTAGE (50mV/DIV)
0
08056-047
INPUT VOLTAGE
0
ADA4051-1/ADA4051-2
Data Sheet
TA = 25°C, unless otherwise noted. –100 VIN = 0.5V VIN = 1V VIN = 1.7V
1kΩ CHANNEL SEPARATION (dB)
–110
–120
–130
–140
VSY = 1.8V G = –100 RL= 10kΩ CL= 50pF
200
2k
20k
FREQUENCY (Hz)
–110
–120
–130
–140
VSY = 5V G = –100 RL= 10kΩ CL = 50pF
–150 20
200
1.5
5
OUTPUT SWING (V)
6
1.2
0.9
0.6
4
3
2
VSY = 1.8V VIN = 1.7V G=1 RL= 10kΩ CL = 50pF
1
1k
10k
100k
FREQUENCY (Hz)
VSY = 5V VIN = 4.9V G=1 RL= 10kΩ CL = 50pF
0 100
08056-051
0 100
20k
Figure 56. Channel Separation vs. Frequency
1.8
1k
10k
100k
FREQUENCY (Hz)
Figure 54. Output Swing vs. Frequency
Figure 57. Output Swing vs. Frequency
VSY = ±2.5V G=1 RL= NO LOAD CL = NO LOAD
VOLTAGE (1V/DIV)
VSY = ±0.9V G=1 RL= NO LOAD CL = NO LOAD
VOUT
VOUT
VIN
VIN TIME (200µs/DIV)
08056-052
VOLTAGE (500mV/DIV)
OUTPUT SWING (V)
Figure 53. Channel Separation vs. Frequency
0.3
2k FREQUENCY (Hz)
TIME (200µs/DIV)
Figure 55. No Phase Reversal
Figure 58. No Phase Reversal
Rev. C | Page 16 of 22
08056-055
–150 20
VIN = 1V VIN = 3V VIN = 4.99V
100kΩ
08056-050
CHANNEL SEPARATION (dB)
1kΩ
08056-053
100kΩ
08056-054
–100
Data Sheet
ADA4051-1/ADA4051-2
THEORY OF OPERATION
To accomplish the best noise vs. power trade-off, the chopping technique is the better approach when designing a low offset amplifier because there is no increased in-band noise. It is preferable to suppress the offset-related ripple inside a chopper amplifier because the offset-related ripple would otherwise need to be eliminated by an extra off-chip postfilter. Figure 59 shows the block diagram design of the ADA4051-1/ ADA4051-2 chopper amplifiers employing a local feedback loop called autocorrection feedback (ACFB). The main signal path contains an input chopping switch network (CHOP1), a first transconductance amplifier (Gm1), an output chopping switch network (CHOP2), a second transconductance amplifier (Gm2), and a third transconductance amplifier (Gm3). CHOP1 and CHOP2 operate at 40 kHz of chopping frequency to modulate the initial offset and 1/f noise from Gm1 up to the chopping frequency. A fourth transconductance amplifier (Gm4) in the ACFB senses the modulated ripple at the output of CHOP2, caused by the initial offset voltage of Gm1. Then, the ripple is demodulated down to a dc domain through a third chopping switch network (CHOP3), operating with the same chopping clock as CHOP1 and CHOP2. Finally, a null transconductance amplifier (Gm5) tries to null any dc component at the output of Gm1 that would otherwise appear in the overall output as ripple. A switched-capacitor notch filter (NF) functions to selectively suppress the undesired offset-related ripple without disturbing the desired input signal from the overall input. The desired input dc signal appears as a dc signal at the output of CHOP2. Then, the initial offset is modulated up to the chopping frequency by CHOP3 and filtered out by the NF. Therefore, initial offset does not create any feedback and does not disturb the desired input signal. The NF is synchronized with the chopping clock to filter out the modulated component. In the same manner, the offset of Gm5 is filtered out by the combination of CHOP3 and the NF, enabling accurate ripple sensing at the output of CHOP2. In parallel with the high dc gain path, a feedforward transconductance amplifier (Gm6) is added to bypass the phase shift introduced by the ACFB at the chopping frequency. Gm6 is designed to have the same transconductance as Gm1 to avoid
CHOP1
CHOP2
Gm1
Gm2
+IN
C2 Gm3 OUT
–IN C1
C3
Gm5
NF CHOP3 Gm4 08056-060
Gm6 (= Gm1)
Figure 59. ADA4051-1/ADA4051-2 Chopper Amplifiers Block Diagram
The voltage noise density, which is equal to the thermal noise floor dominated by the Gm1, is essentially flat from dc to the chopping frequency because CHOP1 and CHOP2 eliminate the 1/f noise generated in Gm1 and the ACFB does not contribute any additional noise. Although the ACFB suppresses the ripple related to the chopping, there is a remaining voltage ripple. To further suppress the remaining ripple down to a desired level, it is recommended to have a postfilter at the output of the amplifier. The remaining voltage ripple originates from two sources. The first type of ripple is due to the residual ripple associated with the initial offset of the Gm1. It is proportional to the magnitude of the initial offset and creates a spectrum at the chopping frequency (fCHOP). When the amplifier is configured as a unitygain buffer, this ripple has a typical value of 4.9 μV rms and a maximum of 34.7 μV rms. The second type of ripple is due to the intermodulation between the high frequency input signal and the chopping frequency. This ripple depends on the input frequency (fIN) and creates a spectrum at frequencies equal to the difference between the chopping frequency and the input frequency (fCHOP − fIN), as well as at frequencies equal to the summation of the chopping frequency and the input frequency (fCHOP + fIN). The magnitude of the ripple for different input frequencies is shown in Figure 60. 500
400
300
200
100
0
0
1
2
3
4
5
6
7
INPUT FREQUENCY (kHz)
8
9
10
08056-063
Auto-zeroing and chopping are two techniques widely used in high precision CMOS amplifiers to achieve low offset, low offset drift, and no 1/f noise. Each of these techniques has pros and cons. Auto-zeroing results in more in-band noise due to aliasing introduced by sampling. On the other hand, chopping produces offset-related ripple because it modulates the initial offset associated with the amplifier up to its chopping frequency.
pole-zero doublets. This design prevents any instability introduced by the ACFB in the overall feedback loop.
MODULATED OUTPUT RIPPLE (µV rms)
The ADA4051-1/ADA4051-2 micropower chopper operational amplifiers feature a novel, patent-pending technique that suppresses offset-related ripple in a chopper amplifier. Instead of filtering the ripple in the ac domain, this technique nulls the initial offset of the amplifier in the dc domain, thus preventing ripple at the overall output.
Figure 60. ADA4051-1/ADA4051-2 Modulated Output Ripple vs. Input Frequency
Rev. C | Page 17 of 22
ADA4051-1/ADA4051-2
Data Sheet
The design architecture of the ADA4051-1/ADA4051-2 specifically targets precision signal conditioning applications requiring accurate and stable performance from dc to 10 Hz bandwidth. In summary, the main features of the ADA4051-1/ ADA4051-2 chopper amplifiers are • •
• •
Considerable suppression of the offset-related ripple No effect on the desired input signal as long as its frequency is much lower than the chopping frequency shown in Figure 60 Achievement of low offset similar to a conventional chopper amplifier No introduction of excess noise
The ADA4051-1/ADA4051-2 chopper amplifiers provide a railto-rail input range with a 1.8 V to 5.5 V supply voltage range and 20 µA supply current consumption over the −40°C to +125°C extended industrial temperature range. The gain bandwidth is 125 kHz as a unity-gain stable amplifier up to 100 pF load capacitance.
INPUT VOLTAGE RANGE The ADA4051-1/ADA4051-2 have internal ESD protection diodes. These diodes are connected between the inputs and each supply rail to protect the input MOSFETs from an electrical discharge event and are reversed-biased during normal operation. This protection scheme allows voltages as high as approximately 0.3 V beyond the supplies (±VSY ± 0.3 V) to be applied at the input of either terminal without causing permanent damage. If either input exceeds one of the supply rails by more than 0.3 V, these ESD diodes become forward-biased and large amounts of current begin to flow through them. Without current limiting, this excessive current would cause permanent damage to the device. If the inputs are expected to be subject to overvoltage conditions, install a resistor in series with each input to limit the input current to 10 mA maximum.
The ADA4051-1/ADA4051-2 also have internal circuitry that protects the input stage from high differential voltages. This circuitry is composed of internal 1.33 kΩ resistors in series with each input and back-to-back diode-connected N-MOSFET (with a typical VT of 0.7 V for a VCM of 0 V) after these series resistors. With normal negative feedback operating conditions, the ADA4051-1/ ADA4051-2 amplifiers correct their output to ensure that the two inputs are at the same voltage. However, if the device is configured as a comparator or there are unusual operating conditions, the input voltages can be forced to different potentials, which may cause excessive current to flow through the internal diodeconnected N-MOSFETs. Although the ADA4051-1/ADA4051-2 are rail-to-rail input amplifiers, take care to ensure that the potential difference between the inputs does not exceed ±VSY to avert permanent damage to the device.
OUTPUT PHASE REVERSAL Although output phase reversal can occur with other amplifiers when the input common-mode voltage range is exceeded, the ADA4051-1/ADA4051-2 amplifiers are designed to prevent any output phase reversal, provided both inputs are maintained approximately within 0.3 V above and below the supply voltages (±VSY ± 0.3 V). With other amplifiers, the outputs may jump in the opposite direction to the supply rail when a common-mode voltage moves outside the common-mode range. This usually occurs when one of the internal stages of the amplifier no longer has sufficient bias voltage across it and subsequently turns off. However, with the ADA4051-1/ADA4051-2 amplifiers, if one or both inputs exceed the input voltage range but remain within the ±VSY ± 0.3 V range, an internal loop opens and the output remains in saturation mode, without phase reversal, until the input voltage is brought back to within the input voltage range limits as shown in Figure 55 and Figure 58.
Rev. C | Page 18 of 22
Data Sheet
ADA4051-1/ADA4051-2
OUTLINE DIMENSIONS 3.00 2.90 2.80
5
1.70 1.60 1.50
4
1
2
3.00 2.80 2.60
3
0.95 BSC 1.90 BSC
1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN
0.20 MAX 0.08 MIN 10° 5° 0°
SEATING PLANE
0.50 MAX 0.35 MIN
0.55 0.45 0.35
0.60 BSC
11-01-2010-A
1.30 1.15 0.90
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 61. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters
2.20 2.00 1.80
1.35 1.25 1.15
5 1
4 2
3
2.40 2.10 1.80
0.65 BSC
0.10 MAX COPLANARITY 0.10
1.10 0.80
0.30 0.15
SEATING PLANE
0.40 0.10
0.22 0.08
0.46 0.36 0.26
COMPLIANT TO JEDEC STANDARDS MO-203-AA
Figure 62. 5-Lead Thin Shrink Small Outline Transistor Package [SC-70] (KS-5) Dimensions shown in millimeters
Rev. C | Page 19 of 22
072809-A
1.00 0.90 0.70
ADA4051-1/ADA4051-2
Data Sheet 3.20 3.00 2.80
8
3.20 3.00 2.80
1
5.15 4.90 4.65
5
4
PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75
15° MAX 1.10 MAX
0.40 0.25
6° 0°
0.80 0.55 0.40
0.23 0.09
10-07-2009-B
0.15 0.05 COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 63. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
1.84 1.74 1.64
3.10 3.00 SQ 2.90
1.55 1.45 1.35
EXPOSED PAD
0.50 0.40 0.30
0.80 0.75 0.70 0.30 0.25 0.20
1
4 BOTTOM VIEW
TOP VIEW
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF
PIN 1 INDICATOR (R 0.15)
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
12-07-2010-A
PIN 1 INDEX AREA
SEATING PLANE
0.50 BSC 8
5
Figure 64. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters
ORDERING GUIDE Model 1 ADA4051-1ARJZ-R2 ADA4051-1ARJZ-R7 ADA4051-1ARJZ-RL ADA4051-1AKSZ-R2 ADA4051-1AKSZ-R7 ADA4051-1AKSZ-RL ADA4051-2ACPZ-R2 ADA4051-2ACPZ-R7 ADA4051-2ACPZ-RL ADA4051-2ARMZ ADA4051-2ARMZ-R7 ADA4051-2ARMZ-RL 1
Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C
Package Description 5-Lead Small Outline Transistor Package [SOT-23] 5-Lead Small Outline Transistor Package [SOT-23] 5-Lead Small Outline Transistor Package [SOT-23] 5-Lead Thin Shrink Small Outline Transistor Package [SC-70] 5-Lead Thin Shrink Small Outline Transistor Package [SC-70] 5-Lead Thin Shrink Small Outline Transistor Package [SC-70] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP]
Z = RoHS Compliant Part.
Rev. C | Page 20 of 22
Package Option RJ-5 RJ-5 RJ-5 KS-5 KS-5 KS-5 CP-8-13 CP-8-13 CP-8-13 RM-8 RM-8 RM-8
Branding A0U A0U A0U A0U A0U A0U A2M A2M A2M A2M A2M A2M
Data Sheet
ADA4051-1/ADA4051-2
NOTES
Rev. C | Page 21 of 22
ADA4051-1/ADA4051-2
Data Sheet
NOTES
©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08056-0-3/16(C)
Rev. C | Page 22 of 22
