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256mb, 512mb, 1gb (x64, Dr) 200-pin Ddr2 Sdram

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Micron Confidential and Proprietary Advance‡ 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Features DDR2 SDRAM SODIMM MT8HSF3264HD – 256MB MT8HSF6464HD – 512MB MT8HSF12864HD – 1GB For component data sheets, refer to Micron’s Web site: www.micron.com/ddr2 Features Figure 1: • 200-pin, small outline, dual in-line memory module (SODIMM) • Fast data transfer rates: PC2-3200, PC2-4200, or PC25300 • 256MB (32 Meg x 64), 512MB (64 Meg x 64), and 1GB (128 Meg x 64) • VDD = VDDQ = +1.8V • VDDSPD = +3.0V to +3.6V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Differential data strobe (DQS, DQS#) option • Four-bit prefetch architecture • DLL to align DQ and DQS transitions with CK • Multiple internal device banks for concurrent operation • Programmable CAS latency (CL) • Posted CAS additive latency (AL) • WRITE latency = READ latency - 1 tCK • Programmable burst lengths: 4 or 8 • Adjustable data-output drive strength • 64ms, 8,192-cycle refresh • On-die termination (ODT) • Serial presence-detect (SPD) with EEPROM • Gold edge contacts • Dual rank • Temperature sensor pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_1.fm - Rev. A 4/06 EN 200-Pin SODIMM (MO-224 R/C “A”) PCB height: 1.18in (29.97mm) Options Marking 2 • I C bus SPD and temperature sensor • Package 200-pin SODIMM (lead-free) • Frequency/CL1 3.0ns @ CL = 5 (DDR2-667)2 3.75ns @ CL = 4 (DDR2-533) 5.0ns @ CL = 3 (DDR2-400) • PCB height 1.18in (29.97mm) HSF Y -667 -53E -40E Notes: 1. CL = CAS (READ) latency. 2. Not available in 1GB density. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Features Table 1: Address Table Refresh count Row addressing Device bank addressing Device page size per bank Device configuration Column addressing Module rank addressing Table 2: 256MB 512MB 1GB 8K 8K (A0–A12) 4 (BA0, BA1) 1KB 256Mb (16 Meg x 16) 512 (A0–A8) 2 (S0#, S1#) 8K 8K (A0–A12) 4 (BA0, BA1) 1KB 512Mb (32 Meg x 16) 1K (A0–A9) 2 (S0#, S1#) 8K 8K (A0–A12) 8 (BA0, BA1, BA2) 1KB 1Gb (64 Meg x 16) 1K (A0–A9) 2 (S0#, S1#) Key Timing Parameters Data Rate (MT/s) Speed Grade CL = 3 CL = 4 CL = 5 (ns) tRP (ns) tRC (ns) -667 -53E -40E 400 400 400 533 533 400 667 – – 15 15 15 15 15 15 55 55 55 Table 3: tRCD Part Numbers and Timing Parameters Part Number1 MT8HSF3264HDY-667__ MT8HSF3264HDY-53E__ MT8HSF3264HDY-40E__ MT8HSF6464HDY-667__ MT8HSF6464HDY-53E__ MT8HSF6464HDY-40E__ MT8HSF12864HDY-667__ MT8HSF12864HDY-53E__ MT8HSF12864HDY-40E__ Notes: pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_1.fm - Rev. A 4/06 EN Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 256MB 256MB 256MB 512MB 512MB 512MB 1GB 1GB 1GB 32 Meg x 64 32 Meg x 64 32 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 5.3 GB/s 4.3 GB/s 3.2 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 4-4-4 3-3-3 5-5-5 4-4-4 3-3-3 5-5-5 4-4-4 3-3-3 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8HSF6464HDY-40EC2. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Serial Presence-Detect Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 AC Timing and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 EVENT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 SMBus Slave Subaddress Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Capability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Temperature Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Upper Temperature Boundary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Lower Temperature Boundary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Critical Temperature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Temperature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Serial Presence-Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 SPD Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 SPD Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 SPD Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 SPD Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDGTOC.fm - Rev. A 4/06 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 7: Figure 8: Figure 9: Figure 10: 200-Pin SODIMM (MO-224 R/C “A”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 EVENT# Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Definition of Start and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Acknowledge Response From Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 SPD EEPROM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 200-Pin DDR2 SODIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDGLOF.fm - Rev. A 4/06 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Part Numbers and Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Absolute Maximum DC Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 DDR2 IDD Specifications and Conditions – 256MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DDR2 IDD Specifications and Conditions – 512MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DDR2 IDD Specifications and Conditions – 1GB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Module and Component Speed Grade Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Temperature Sensor EEPROM AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Temperature Sensor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Pointer Register Bits 0–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Pointer Register Bits 0–2 Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Capability Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Capability Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Configuration Register Bits 0–15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Configuration Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Upper Temperature Boundary Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Lower Temperature Boundary Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Critical Temperature Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Temperature Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Temperature Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 EEPROM Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 EEPROM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Serial Presence-Detect EEPROM and Temperature Sensor DC Operating Conditions . . . . . . . . . . .26 Serial Presence-Detect EEPROM AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Serial Presence-Detect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDGLOT.fm - Rev. A 4/06 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 4: Pin Assignments 200-Pin SODIMM Front 200-Pin SODIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 VSS 52 DQ4 54 DQ5 56 VSS 58 DM0 60 VSS 62 DQ6 64 DQ7 66 VSS 68 DQ12 70 DQ13 72 VSS 74 DM1 76 VSS 78 CK0 80 CK0# 82 VSS 84 DQ14 86 DQ15 88 VSS 90 VSS 92 DQ20 94 DQ21 96 VSS 98 EVENT# 100 DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CKE1 VDD NC NC VDD A11 A7 A6 VDD A4 A2 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 A0 VDD BA1 RAS# S0# VDD ODT0 NC VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 Vss DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC NC/BA2 VDD A12 A9 A8 VDD A5 A3 Note: Figure 2: 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 A1 VDD A10/AP BA0 WE# VDD CAS# S1# VDD ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DQ42 DQ43 VSS DQ48 DQ49 VSS NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD Pin 85 is NC for 256MB and 512MB, BA2 for 1GB. Pin Locations Front View U1 Back View U2 U3 U4 U5 U10 PIN 1 U9 U7 (all odd pins) PIN 199 PIN 200 Indicates a VDD or VDDQ pin pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN U8 U6 6 (all even pins) PIN 2 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Table 4 on page 6 for more information Pin Numbers Symbol Type Description 114, 119 ODT0, ODT1 Input 30, 32, 164, 166 CK0, CK0# CK1, CK1# Input 79, 80 CKE0, CKE1 Input 110, 115 S0#, S1# Input 108, 109, 113 RAS#, CAS#, WE# Input 85 (1GB), 106, 107 BA0, BA1, BA2 (1GB) Input 89, 90, 91, 92, 93, 94, 97, 98, 99, 100, 101, 102, 105 A0–A12 Input 10, 26, 52, 67, 130, 147, 170, 185 DM0–DM7 UDM = DM0, DM2, DM5, DM7 LDM = DM 1, DM3, DM4, DM6 Input On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is applied to these pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LMR command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all device banks idle), or ACTIVE powerdown (row ACTIVE in any device bank). CKE is synchronous for power-down entry, power-down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level once VDD is applied during first power-up. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH operation, VREF must be maintained to this input. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied, BA0–BA1/BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command. Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Pin Assignments and Descriptions Table 5: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to Table 4 on page 6 for more information Pin Numbers 4, 5, 6, 7, 14, 16, 17, 19, 20, 22, 23, 25, 35, 36, 37, 38, 43, 44, 45, 46, 55, 56, 57, 58, 61, 62, 63, 64, 73, 74, 75, 76, 123, 124, 125, 126, 134, 135, 136, 137, 140, 141, 142, 143, 151, 152, 153, 154, 157, 158, 159, 160, 173, 174, 175, 176, 179, 180, 181, 182, 189, 191, 192, 194 11, 13, 29, 31, 49, 51, 68, 70, 129, 131, 146, 148, 167, 169, 186, 188 Symbol Type DQ0–DQ63 I/O DQS0–DQS7, DQS0#–DQS7# I/O Description Data input/output: Bidirectional data bus. 197 SCL 198, 200 SA0–SA1 195 SDA 50 EVENT# 81, 82, 87, 88, 95, 96, 103, 104, 111, 112, 117, 118 1 2, 3, 8, 9, 12, 15, 18, 21, 24, 27, 28, 33, 34, 39, 40, 41, 42, 47, 48, 53, 54, 59, 60, 65, 66, 71, 72, 77, 78, 121, 122, 127, 128, 132, 133, 138, 139, 144, 145, 149, 150, 155, 156, 161, 162, 165, 168, 171, 172, 177, 178, 183, 184, 187, 190, 193, 196 199 69, 83, 84, 85 (256MB and 512MB), 86, 116, 120, 163 VDD Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LMR command. Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-detect address inputs: These pins are used to configure the presence-detect device. Input/ Serial presence-detect data: SDA is a bidirectional pin used to Output transfer addresses and data into and out of the presence-detect portion of the module. Output Event signal based off the temperature for the temperature sensor option. Supply Power supply: +1.8V ±0.1V. VREF VSS Supply SSTL_18 reference voltage. Supply Ground. pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN VDDSPD NC Supply Serial EEPROM positive power supply: +3.0V to +3.6V. – No connect: These pins should be left unconnected. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Functional Block Diagram Functional Block Diagram Unless otherwise noted, resistor values are 22Ω. Micron module part numbers are explained in the module part numbering guide at www.micron.com/numbering. Modules use the following DDR2 SDRAM devices: MT47H16M16BP (256MB); MT47H32M16BT (512MB); and MT47H64M16BT (1GB). Figure 3: Functional Block Diagram 3 S1# S0# UDQS UDQS# UDM DQS0 DQS0# DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1# DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ DQ DQ DQ DQ DQ DQ DQ LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQS2 DQS2# DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3# DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ CS# U1 CS# U2 UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ CS# LDQS LDQS# LDM DQS4 DQS4# DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U9 DQS5 DQS5# DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS# LDQS LDQS# LDM DQS6 DQS6# DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U8 DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ DQS7 DQS7# DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ BA0-BA1/BA2: DDR2 SDRAMs A0-A12/A13: DDR2 SDRAMs VDDSPD RAS#: DDR2 SDRAMs VDD, VDDQ CAS#: DDR2 SDRAMs VREF WE#: DDR2 SDRAMs VSS CKE0: DDR2 SDRAMs CKE1: DDR2 SDRAMs ODT0: DDR2 SDRAMs ODT1: DDR2 SDRAMs pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ U3 CS# LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ U4 U7 Serial PD 3Ω BA0–BA1/BA2 A0–A12 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 CS# Serial PD DDR2 SDRAMS SCL DDR2 SDRAMS DDR2 SDRAMS, EEPROM TEMP SENSOR WP SDA A0 A1 A2 CS# U5 U1, U2, U8, U9 100Ω U10 Temp Sensor A1 U6 100Ω CK0 CK0# EVENT SA0 SA1 EVT A0 CS# CK1 CK1# U3, U4, U5, U6 SDA A2 EVENT SA0 SA1 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM General Description General Description The MT8HSF3264HD, MT8HSF6464HD, and MT8HSF12864HD DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 256MB, 512MB, and 1GB memory modules organized in x72 configuration. DDR2 SDRAM modules use internally configured quad-bank (256MB, 512MB) or eight-bank (1GB) DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus extended mode register 2 (EMR2). pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Electrical Specifications Electrical Specifications Stresses greater than those listed below (in Table 6) may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 6: Absolute Maximum DC Ratings Parameter VDD supply voltage relative to VSS VDDQ supply voltage relative to VSS VDDL supply voltage relative to Vss Voltage on any pin relative to VSS Storage temperature DDR2 SDRAM device operating temperature (ambient) Operating temperature (ambient) Command/Address, Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN ≤0.95V; (All other pins not under RAS#, CAS#, WE# S#, test = 0V) CKE CK, CK# DM Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs and DQ, DQS, DQS# ODT are disabled VREF leakage current; VREF = Valid VREF level Symbol Min Max Units VDD VDDQ VDDL –1.0 –0.5 –0.5 2.3 2.3 2.3 V V V VIN, VOUT TSTG Tcase TOPR II –0.5 –55 0 0 2.3 100 85 65 V °C °C °C –40 40 –20 –10 20 10 IOZ –10 10 µA IVREF –16 16 µA µA Capacitance At DDR2 data rates, Micron encourages designers to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Electrical Specifications Table 7: DDR2 IDD Specifications and Conditions – 256MB Values shown for DDR2 SDRAM components only Parameter/Condition t t t Symbol -667 -53E -40E Units IDD0a 380 340 320 mA IDD1a 420 380 360 mA IDD2Pb 40 40 40 mA IDD2Qb 400 280 200 mA IDD2Nb 320 280 240 mA 240 200 160 mA 48 48 48 mA IDD3Nb 440 320 240 mA IDD4Wa 880 740 580 mA IDD4Ra 780 660 500 mA IDD5b 1,440 1,360 1,320 mA IDD6b 40 40 40 mA IDD7a 1,020 980 940 mA t Operating one bank active-precharge current; CK = CK (IDD), RC = RC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; tCK = Fast PDN exit tCK (IDD); CKE is LOW; Other control and address bus inputs MR[12] = 0 are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 t t Active standby current; All device banks open; CK = CK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open, continuous burst WRITEs; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open, continuous burst READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching; See IDD7 conditions in component data sheet for detail IDD3Pb Note: a: Value calculated as one module rank in this operating condition, and all other ranks in IDD2P (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Electrical Specifications Table 8: DDR2 IDD Specifications and Conditions – 512MB Values shown for DDR2 SDRAM components only Parameter/Condition t t t Symbol -667 -53E -40E Units IDD0a 500 460 460 mA IDD1a 600 540 520 mA IDD2Pb 40 40 40 mA IDD2Qb 440 360 320 mA IDD2Nb 480 400 360 mA 280 240 200 mA 80 80 80 mA IDD3Nb 560 480 400 mA IDD4Wa 940 780 620 mA IDD4Ra 960 800 640 mA IDD5b 1,760 1,680 1,600 mA IDD6b 40 40 40 mA IDD7a 1,340 1,320 1,300 mA t Operating one bank active-precharge current; CK = CK (IDD), RC = RC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; tCK = Fast PDN exit tCK (IDD); CKE is LOW; Other control and address bus inputs MR[12] = 0 are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 t t Active standby current; All device banks open; CK = CK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open, continuous burst WRITEs; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open, continuous burst READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching; See IDD7 conditions in component data sheet for detail IDD3Pb Note: a: Value calculated as one module rank in this operating condition, and all other ranks in IDD2P (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Electrical Specifications Table 9: DDR2 IDD Specifications and Conditions – 1GB Values shown for DDR2 SDRAM components only Parameter/Condition t t t Symbol -667 -53E -40E Units IDD0a 560 460 460 mA IDD1a 660 540 520 mA IDD2Pb 56 40 40 mA IDD2Qb 520 360 320 mA IDD2Nb 560 400 320 mA 320 240 200 mA 40 40 40 mA IDD3Nb 600 440 400 mA IDD4Wa 1,100 780 660 mA IDD4Ra 1,120 800 740 mA IDD5b 2,160 2,000 1,920 mA IDD6b 56 40 40 mA IDD7a 1,640 1,440 1,440 mA t Operating one bank active-precharge current; CK = CK (IDD), RC = RC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; tCK = Fast PDN exit tCK (IDD); CKE is LOW; Other control and address bus inputs MR[12] = 0 are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 t t Active standby current; All device banks open; CK = CK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open, continuous burst WRITEs; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open, continuous burst READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching; See IDD7 conditions in component data sheet for detail IDD3Pb Note: a: Value calculated as one module rank in this operating condition, and all other ranks in IDD2P (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM AC Timing and Operating Conditions AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron’s Web site: www.micron.com/ddr2. Module speed grades correlate with component speed grades as shown in the following table: Table 10: Table 11: Module and Component Speed Grade Table Module Speed Grade Component Speed Grade -667 -53E -40E -3 -37E -5E Temperature Sensor EEPROM AC Timing Parameter/Condition Time the bus must be free before a new transition can start SDA and SCL fall time Data hold time Start condition hold time Clock HIGH period Clock LOW period SDA and SCL rise time SCL clock frequency Data setup time Start condition setup time Stop condition setup time Clock frequency pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN Symbol Min tBUF 4.7 tF tHD:DAT tHD:STA tHIGH tLOW 300 300 4.0 4 4.7 tR tSU:STA tSU:STO tCK 15 50 1000 400 fSCL tSU:DAT Max 250 4.7 4 10 100 Units µs ns ns µs µs µs ns KHz ns µs µs KHz Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Temperature Sensor Temperature Sensor The optional temperature sensor continuously monitors the module’s temperature and can be read back at any time over the I2C bus shared with the SPD. This sensor complies with the JEDEC standard JC-42.4, covering a range from -20–125°C. EVENT# Pin The temperature sensor also adds the EVENT# pin. Not used by the SPD, EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor’s configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. The open-drain output of EVENT# under the three separate operating modes is illustrated in Figure 4 on page 17. Event thresholds are programmed in the 0x01 register using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and only returns to the logic HIGH state once temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. Once the critical trip point has been reached, the temperature sensor goes into comparator mode and the critical EVENT# cannot be cleared through software. SMBus Slave Subaddress Decoding The temperature sensor’s physical address differs from current SPD device physical addresses: 0011 for A0, A1, A2, and RW in binary, where A2, A1, and A0 are the three slave subaddress pins and RW pin is the READ/WRITE flag. If the slave base address is fixed for the SPD and temperature sensor, then the pins set the subaddress bits of the slave address, enabling the devices to be located anywhere within the eight slave address locations. For example, they could be set from 30h to 3Eh. pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Temperature Sensor Figure 4: EVENT# Pin Functionality Temp Critical Hysteresis affects these trip points Alarm Window (MAX) Alarm Window (MIN) S/V clears event Time EVENT# interrupt mode EVENT# comparator mode EVENT# critical temp-only mode Table 12: Temperature Sensor Registers Name Pointer register Capability register Configuration register Alarm temperature upper boundary register Alarm temperature lower boundary register Critical temperature register Temperature register pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 17 Address (Hex) Power-On Default n/a 0x00 0x01 0x02 0x03 0x04 0x05 Undefined 0x0001 0x0000 0x0000 0x0000 0x0000 Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Pointer Register Pointer Register The pointer register selects which of the 16-bit registers is being accessed in subsequent READ and WRITE operations. This register is a WRITE only register. Table 13: Pointer Register Bits 0–7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 Register select Register select Register select Register select Table 14: Pointer Register Bits 0–2 Descriptions Bit2 Bit1 Bit0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Register Capability register Configuration register Alarm temperature upper boundary register Alarm temperature lower boundary register Critical temperature register Temperature register Capability Register The capability register indicates the features and functionality supported by the temperature sensor. This register is a read-only register. Table 15: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 RFU RFU RFU RFU RFU RFU RFU RFU Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RFU RFU RFU TRES1 TRES0 Wider range Precision Has alarm and critical temperature Table 16: Bit 0 1 2 Capability Register Bits Capability Register Bit Descriptions Description Basic capability 1: Has alarm and critical trip point capabilities Accuracy 0: ±2°C over the active range and ±3°C over the monitor range 1: ±1°C over the active range and ±2°C over the monitor range Wider range 0: Values lower than 0°C is clamped to a binary value of 0 1: Temperatures below 0°C can be read pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Configuration Register Table 16: Capability Register Bit Descriptions Bit Description 4:3 Temperature resolution 00: 05°C LSB 01: 0.25°C LCB 10: 0.125°C LSB 11: 0.0625°C LSB 0: Must be set to zero 15:5 Configuration Register Table 17: Configuration Register Bits 0–15 Bit15 Bit14 Bit13 Bit12 Bit11 RFU RFU RFU RFU RFU Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Critical lock bit Alarm lock bit Clear event Event output status Event output control Critical event only Event polarity Event mode Table 18: Bit 0 1 2 3 4 5 6 7 Bit10 Bit9 Hysteresis Bit8 Shutdown mode Configuration Register Bit Descriptions Description Event mode 0: Comparator mode 1: Interrupt mode Cannot be changed if either of the lock bits are set EVENT# polarity 0: Active LOW 1: Active HIGH Cannot be changed if either of the lock bits are set Critical event only 0: Event# trips on alarm or critical temperature event 1: EVENT# trips only if critical temperature is reached Event output control 0: Event output disabled 1: Event output enabled Event status 0: EVENT# has not been asserted by this device 1: EVENT# is being asserted due to a alarm window or critical temperature condition This is a read-only field in the register; the event causing the event can be determined from the read temperature register Clear event 0: No effect 1: Clears the event when the temperature sensor is in the interrupt mode This is a WRITE only field in the register and is self clearing Alarm window lock bit 0: Alarm trips will are not locked and can be changed 1: Alarm trips are not locked and can not be changed Critical trip lock bit 0: Critical trip is not locked and can be changed 1: Critical trip are not locked and can not be changed pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Configuration Register Table 18: Bit 8 10:9 Configuration Register Bit Descriptions Description Shutdown mode 0: Enabled 1: Shutdown The shutdown mode is a power saving mode that disables the temperature sensor Hysteresis enable 00: Disable 01: Enable at 1.5°C 10: Enable at 3°C 11: Enable at 6°C When enabled, a hysteresis is applied to temperature movement around the trip points. For example, if the hysteresis register is enabled to a delta of 6°C, the preset trip points will toggle when temperature reaches the programmed value. The value resets when temperature drops below trip points minus the set hysteresis level (critical temperature - 6°C). The hysteresis is applied to both the above alarm window and the below alarm window bits found in the read-only temperature register. EVENT# is also affected by this register. Figure 5: Hysteresis TH TH-Hyst TL TL-Hyst Below Window Bit Above Window Bit TH - Value set in the alarm temperature upper boundary trip register TL - Value set in the alarm temperature lower boundary trip register Hyst - Value set in the hysteresis bits of the configuration register Table 19: Hysteresis Condition Sets Clears Below Alarm Window Bit Temperature gradient Falling Rising pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN Above Alarm Window Bit Critical temperature TL-Hyst TL 20 Temperature gradient Rising Falling Critical temperature TH TH-Hyst Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Temperature Format Temperature Format The temperature trip point registers and temperature readout register use a “2’s complement” format to enable negative numbers. The least significant bit (LSB) is equal to 0.0625°C or 0.25°C depending on which register is referenced. As an example, assuming a LSB of 0.0625°C: • A value of 0x018C would equal 24.75°C • A value of 0x06C0 would equal 108°C • A value of 0x1E74 would equal –24.75°C Upper Temperature Boundary Register The upper temperature boundary register is used to set the maximum value of the alarm window. The LSB for this register is 0.25°C. All RFU bits in the register will always report zero. Table 20: Upper Temperature Boundary Register Bits 15 14 13 12 11 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Alarm window upper boundary temperature Lower Temperature Boundary Register The lower temperature boundary register is used to set the minimum value of the alarm window. The LSB for this register is 0.25oC. All RFU bits in the register will always report zero. Table 21: Lower Temperature Boundary Register Bits 15 14 13 12 11 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Alarm window lower boundary temperature Critical Temperature Register The critical temperature register is used to set the maximum temperature above the alarm window. The LSB for this register is 0.25°C. All RFU bits in the register will always report zero. Table 22: Critical Temperature Register Bits 15 14 13 12 0 0 0 MSB 11 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Critical temperature trip point pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Temperature Format Temperature Register The temperature register is a read-only register that provides the current temperature detected by the temperature sensor. The LSB for this register is 0.0625°C with a resolution of 0.0625°C. The most significant bit (MSB) is 128°C in the readout section of this register. The upper three bits of the register are used to monitor the trip points that are set in the previous three registers. Table 23: 15 Temperature Register Bits 14 13 Above Above Below critical alarm alarm trip window window Table 24: 12 11 10 9 8 5 4 3 2 1 0 LSB Temperature Temperature Register Bit Descriptions Description 13 Below alarm window 0: Temperature is equal to or above the lower boundary 1: Temperature is below alarm window Above alarm window 0: Temperature is equal to or below the upper boundary 1: Temperature is above alarm window Above critical trip point 0: Temperature is below critical trip point 1: Temperature is above critical trip point 15 6 MSB BIT 41 7 pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (see Figures 6 and 7 on page 24). SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SPD Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting 8 bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the 8 bits of data (see Figure 8 on page 24). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit 8 bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Figure 6: Data Validity SCL SDA Data stable Figure 7: Data change Data stable Definition of Start and Stop SCL SDA Start bit Figure 8: Stop bit Acknowledge Response From Receiver (( )) SCL from master (( )) (( )) Data output from transmitter (( )) Data output from receiver Acknowledge pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Table 25: EEPROM Device Select Code The most significant bit (b7) is sent first Device Type Identifier Select Code Memory area select code (two arrays) Protection register select code Table 26: RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW EEPROM Operating Modes Mode Current address READ Random address READ Sequential READ Byte WRITE Page WRITE Figure 9: Chip Enable RW Bit WC Bytes 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 ≥1 1 ≤ 16 Initial Sequence START, device select, RW = ‘1’ START, device select, RW = ‘0’, address RESTART, device select, RW = ‘1’ Similar to current or random address READ START, device select, RW = ‘0’ START, device select, RW = ‘0’ SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA In t DH t AA t BUF SDA Out UNDEFINED pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Table 27: Serial Presence-Detect EEPROM and Temperature Sensor DC Operating Conditions All voltages referenced to VSS; VDDSPD = +3.0V to +3.6V Parameter/Condition Supply voltage with temperature sensor option Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA SPD input leakage current: VIN = GND to VDD SPD output leakage current: VOUT = GND to VDD SPD standby current Power supply current, READ: SCL clock frequency = 100 KHz Power supply current, WRITE: SCL clock frequency = 100 KHz Average temperature sensor current Table 28: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 3.0 2.1 -0.6 – 0.10 0.05 1.6 0.4 2 3.6 VDDSPD + 0.5 0.8 0.4 3 3 4 1 3 500 V V V V µA µA µA mA mA µA Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +3.0V to +3.6V Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN Symbol Min Max Units Notes tAA 0.2 1.3 200 0.9 µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT tSU:STA t SU:STO t WRC 100 0.6 0.6 10 2 2 3 4 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Table 29: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte Description Entry (Version) 0 1 2 3 4 Number of SPD bytes used by Micron Total number of bytes in SPD device Fundamental memory type Number of row addresses on assembly Number of column addresses on assembly DIMM height and module ranks Module data width Reserved Module voltage interface levels DDR2 cycle time, tCK (CL = MAX value, see byte 18) 128 256 DDR2 SDRAM 13 9, 10 80 08 08 0D 09 80 08 08 0D 0A 80 08 08 0D 0A 1.18in, Dual rank 64 – SSTL 1.8V -667 -53E -40E -667 -53E -40E 61 40 00 05 30 3D 50 45 50 60 00 82 10 61 40 00 05 30 3D 50 45 50 60 00 82 10 61 40 00 05 30 3D 50 45 50 60 00 82 10 00 00 0C 04 38 18 01 04 00 03 01 3D 50 45 60 50 00 45 00 3C 28 3C 2D 28 00 00 0C 04 38 18 01 04 00 03 01 3D 50 45 60 50 00 45 00 3C 28 3C 2D 28 00 00 0C 08 38 18 01 04 00 03 01 3D 50 45 60 50 00 45 00 3C 28 3C 2D 28 5 6 7 8 9 10 DDR2 access from clock,tAC (CL = MAX value, see byte 18) 11 12 13 Module configuration type Refresh rate/type DDR2 SDRAM device width (primary device) Error-checking DDR2 data width Reserved Burst lengths supported Number of banks on DDR2 device CAS latencies supported 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Module thickness DDR2 DIMM type DDR2 module attributes DDR2 device attributes: weak driver (01) or 50Ω ODT (03) DDR2 cycle time, tCK, MAX CL - 1 SDRAM access from CK, tAC, MAX CL - 1 SDRAM cycle time, tCK, MAX CL - 2 SDRAM access from CK, tAC, MAX CL - 2 MIN row precharge time, tRP MIN row active to row active, tRRD MIN RAS#-to-CAS# delay, tRCD MIN RAS# pulse width, tRAS pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 7.81µs/SELF 16 N/A – 4, 8 4 or 8 -667 (5, 4, 3) -53E/-40E (4, 3) SODIMM -667 -53E/-40E -667 -53E/-40E -667/-53E -40E -667 -53E/-40E(N/S) -667 -53E/-40E(N/S) -667/-53E -40E 27 MT8HSF3264HD MT8HSF6464HD MT8HSF12864HD Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Table 29: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte Description 31 Module rank density 32 Address and command setup time, tISb 33 Address and command hold time, tIHb 34 Data/data mask input setup time, tDSb 35 Data/data mask input hold time, tDHb 36 37 Write recovery time, tWR WRITE-to-READ command delay, tWTR 38 READ-to-PRECHARGE command delay, tRTP Mem analysis probe Extension for bytes 41 and 42 MIN active auto refresh time, tRC 39 40 41 42 43 44 45 MIN AUTO REFRESH-to-ACTIVE/ AUTO REFRESH command period, tRFC DDR2 device MAX cycle time, tCKMAX DDR2 device MAX DQS-DQ skew time, tDQSQ DDR2 device MAX read data hold skew factor, tQHS 46 47–61 62 63 PLL relock time Optional features, not supported SPD revision Checksum for bytes 0–62 64 65–71 72 73–90 91 92 93 94 95-98 99–117 118 119 Manufacturer’s JEDEC ID code Manufacturer’s JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (Continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Manufacturer-specific data (RSVD) Temperature sensor location and accuracy MAX temperature offset pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN Entry (Version) 128MB, 256MB, 512MB -667/-53E -40E -667 -53E -40E -667/-53E -40E -667 -53E -40E -667/-53E -40E -667/-53E -40E -667 -53E -40E -667 -53E -40E Release 1.2 -667 -53E -40E MICRON (Continued) 01–12 1–9 0 28 MT8HSF3264HD MT8HSF6464HD MT8HSF12864HD 20 40 80 20 35 27 37 47 10 15 17 22 27 3C 1E 28 1E 20 35 27 37 47 10 15 17 22 27 3C 1E 28 1E 20 35 27 37 47 10 15 17 22 27 3C 1E 28 1E 00 00 3C 37 4B 00 00 3C 37 69 00 06 3C 37 7F 80 18 1E 23 22 28 2D 00 00 12 E0 8B F2 2C FF 01–0C Variable data 01–09 00 Variable data Variable data Variable data – TBD TBD 80 18 1E 23 22 28 2D 00 00 12 1F CA 31 2C FF 01–0C Variable data 01–09 00 Variable data Variable data Variable data – 0C 16 80 18 1E 23 22 28 2D 00 00 12 7F 2A 91 2C FF 01–0C Variable data 01–09 00 Variable data Variable data Variable data – TBD TBD Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Table 29: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte Description Entry (Version) 120 MAX offset error 121 DIMM PSI 122–127 Manufacturer-specific data (RSVD) Notes: pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN MT8HSF3264HD MT8HSF6464HD MT8HSF12864HD TBD TBD – 05 25 – TBD TBD – 1. The tRAS SPD value shown is based on the JEDEC standard value of 45ns; the actual device specification is tRAS = 40ns. 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Advance 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SDRAM SODIMM Module Dimensions Module Dimensions MAX All dimensions are in inches (millimeters); or typical where noted. The dimensional diagram is for reference only. Refer toMIN the MO document for complete design dimensions. Figure 10: 200-Pin DDR2 SODIMM FRONT VIEW 0.150 (3.80) MAX 2.667 (67.75) 2.656 (67.45) 0.079 (2.00) R (2X) U1 U2 U3 U4 1.187 (31.15) 1.175 (29.85) U10 0.071 (1.80) (2X) 0.787 (20.00) TYP 0.236 (6.00) TYP 0.043 (1.10) 0.0197 (0.50) R 0.079 (2.00) TYP 0.018 (0.45) TYP 2.504 (63.60) TYP PIN 1 0.024 (0.60) TYP PIN 199 0.035 (0.90) BACK VIEW U5 U6 U8 U9 U7 0.138 (3.50) TYP PIN 200 1.87 (47.4) TYP 0.165 (4.2) TYP PIN 2 0.45 (11.4) TYP 0.64 (16.26) TYP ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Advance: This data sheet contains initial descriptions of products still under development. pdf: 09005aef80ebed66, source: 09005aef80ebbc49 HSF8C32_64_128x64HDG_2.fm - Rev. A 4/06 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved.