Transcript
US006148389A
United States Patent
119]
So [54]
[11]
Patent Number:
[45]
Date of Patent:
PC CIRCUITS. SYSTEMS AND METHODS
5.694.600
Inventor:
John Ling Wing S0. Plano. Tex.
6/1998
5.828.848
[73] Assrgnee: Texas Instruments Incorporated.
Nov. 14. 2000
12/1997 Pletcher et a1. ....................... .. 710/201
5.768.613
{75]
6,148,389
Asghar .................................... .. 712/35
10/1998 MacCormick et a1. ............... .. 709/247
FOREIGN PATENT DOCUMENTS
Dallas. Tex. WO97/17654
5/1997
WIPO .
[21] App]. No.: 09/372,457 [22
I
62
Filed:
1
I521
Aug‘ 11’ 1999 Related Us. Applica?on Data
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NLY‘2‘.%’§$.53BF’
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Primary E.\‘ami/1cr—Danie1 H. Pan Attorney/1510111. 01' Firm—Robert D. Marshall. Jr.: W. James Brady. III; Frederick J. Telecky. Jr.
N .O8/823.257. M .24. 1997. P t.
O
t“
a
Int. U-S- Cl.7 Cl- -----------............................. ‘ ..
ABSTRACT
An improved
712/35; 713/361 712/42 Of Search ................................ ..
[56]
1571
42.
systen] that includes a [nail]
microprocessor. a ?le-based operating system. and a DSP microprocessor arranged so that [he
can execute main
710/129- 2611 709/147: 7ll/li1~ 101201
CPU operations during time intervals in which the main
205’ "06‘ 208" “20: 781/104 References Cited
CPU is otherwise occupied. thereby increasing the band width of the system is provicled. This PC system may Include multiple CPUs and/or multiple DSPs.
U.S, PATENT DOCUMENTS 5.289.546
2/1994 Hetherington ........................ .. 381/104
10 Claims, 39 Drawing Sheets
II6
\
PCI BUS >
L9
305 \
PCI BUS MASTER/SLAVE INTERFACE
32
\304
STATUS ?lNT 32% 32% 310
PC] CONFIGURATION
306/ CONTROL AND STATUS REGISTER
PCI
1/0
SPACE REGISTERS 308 an
CTL
PCI
DUAL-PORT
READ-WRITE FIFO
DSP
I/O
SPACE REGISTERS
15
SZOCSX INTERFACE/STEREO CODEC DMA CONTROL
DATA
\312
US. Patent
Nov. 14, 2000
Sheet 1 0f 39
6,148,389
FIG. 7 102
CPU
104
NSP APP.
112
\
FILTERS TRANS
CACHE
'
108\ HOST
BRIDGE
l 0
MEM.
CONV.
@
\
< 1F"_ RF |
:
\
MAIN
PC] BUS
#>
"__l1
|
120
ISO-IT] :
, 1
/
105p
200 /
ATM/ I P1394 SIDEBAND EMBEDDED TLAN 1 (USB) 32OCXX
I---
---I
’
MODEM
VDSVD
U20 STEREO AUDIO
SPEAKERPHONE
DSVD
CORE
®
124
Q
/
SPEECH
IS 5 S A
D
>
/ 128
H\6
FIG‘ 2
PCI BUS
Q
128 :
TRUESPEECH SLAVE
WINMODEM SCATTER-GATHER SLAVE BUS-MASTER
\.,\
>
ISA BUS :
SOUNDBLASTER 1/0 PORT DMA
\ 210
SINGLE-PORT FIFO (TO HOST) RAM (10 D1sP)/ 214
US. Patent
Nov. 14, 2000
IIG
Sheet 2 0f 39
FIG.
\
Q
6,148,389
3
PCl BUS
{E
Q99
>
PGI BUS MASTER/SLAVE INTERFAGE
\304
305 \ 32% STATUS ?INT ???g 3T0/ ?CTL PC] CONFIGURATION
PC!
306/ CONTROL AND
PCI
I/o
STATuS REGISTER
DSP
DUAL-PORT
SPAGE REGISTERS
V0
READ—WRITE FIFo
\312
SPAGE REGISTERS
/ 308 CTL
‘5
DATA
32OC5X INTERFAGE/STERED CODEC DMA CONTROL
Fl G .
\316
4
116 /
PCI
Q
I
>
4
‘I
SINGLE PC‘
460
\
PCI
>
SINGLE PC!
LOAD
4 4 420
LOAD
V
12
/
V
LOCAL ARBITER (OPTIONAL) M
MASTER/SLAVE I/F I
A
ACCELERATION TI
II
IDSP
CONTROLLER
V
BUS
CARD BUS ——[SLDT 1 .lL
(BUS MASTER)
(BUS MASTER) “Elm 2
IDSP
428 ——
‘
TI
GRAPHICS/ VIDEO \' CONTROLLER 434 A2 A
IZV
‘06|'_____l fv '
FRAME
'
I BUFFER PUMA L__._____l
US. Patent
Nov. 14, 2000
Sheet 3 0f 39
6,148,389
“3
PC]v
<
F-
_
_
_
—
_ —
—
_
___l
|
CPU
484 \
|:
424
MASTER/SLAVE
If 420
l
MEMORY
!
CONTROL
|
GRAPHICS
"E
VIDEO
432 Jr
I
[USP :
0
-
\T 428
‘- “““““ “
106
DATA
/
488f BUFFER
FIG UMA
'
P5 Q
IDSP#1 = PCI DSVD
PC‘
SOUTH BRIDGE I
IDSP#2 = PCMCIA/ VIDEO ADAPTER
(MPEG 1) IDSP#3 = #00
@ ‘5A
IDSP#4 = ISA SOUND
FIG. 6 SUPERSCALER EXTENSION U PIPE
a
FIG 5
NORTH BRIDGE
@
4
V PIPE
DSPOP
US. Patent
Nov. 14, 2000
Sheet 4 0f 39
FI G. PRIMARY
E21‘ ‘RI
6,148,389
6a DUAL ACCESS ON CHIP CORE MEMoRY
A I
SECONDARY
PROG/DATA
SINGLE ACCESS 0N CHIP MEMoRY
I I
TERTIARY
PROG/DATA
EXTERNAL SINGLE ACCESS MEMoRY
I I
OUATERNARY
DRAM
HOST MEMoRY
I_]_g
DIS K 3 TRA 0 GE
2742
A
II
vRT I uA L
DISK
DSP CACHING SCHEME
WIN 95 MULTITHREADED MULTI-TASKING OS PRE-EMPTIVE SCHEDULER REALTIME PRIORITIES /
REALTIME SERVICES IDSP
FIG. 8 s/III CACHE VIA PAGING \
DSP ON CHIP
DARAM B0, B1, B2
US. Patent
Nov. 14, 2000
Sheet 8 0f 39
6,148,389
102
\
104 \
MAIN
CPU
CACHE
MEMORY
FI G.
78
1 108/ PCI 0111005
1\12
1160
116b
F \ PCl BUS 0
1810
128
PCI/PCI /PC| BUS l 1 K,1
PC] SLAVE
Pol/AT
PC1 SLOT
AT SLOT
1
1
PCI 1 F _
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DSP
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5
WAVE
1918 ‘ DRIVER l/F [-
-
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— _
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—
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WINDOWS WAVE DRIVER —+1LRESOURCE MANAGER - RM1_l1<—
191ORECORD/PLAYBACK
I
1914\
1
ACM/ACM DRIVER
DATA FORMAT CONVERSION
11051 DSP DRIVER
PC 11031 s/w 1 0s1> s/w 32OC5xDSP KERNEL SOFTWARE x1922
1 FIG
79
DSP AUDIO/CONVERTER \1926
1 DSP CODEC DRIVER
x1930
1 STEREO CODEC
1934
US. Patent
Nov. 14,2000
6,148,389
Sheet 9 0f 39
FI G .
2O
1 16
PCI BUS
/
PCI MASTER/SLAVE l/F II
AQA
M
SATUS
II
INT
32/
32/
on
II
IV
PC!
DSP
I/O SPACE
FIFO
RECS “
CTL
\ 308
ISAIUS 7 1/0 SPACE
I
/ 16 310 ”
REGS
DATA
>300
\ 31 2
IT
M
DSP
1950
I/F
DSP
/ 218
PS MEM / 16 00 1952
@?— I950
c0050
/ 8 BI T 1956
GLOBAL MEM \1954 1 962
8 0 R16 Bl T
FI G. 2 7 PROGRAM POINTER
SOURCE POINTER
'- DESTINATION POINTER
SOURCE DMA TRANSFER TABLE
DESTINATION DMA TRANSFER TABLE
ORIGINATING ON A 4K BYTE BOUNDARY AND
128K BYTES OF CONTIGUOUS MEMORY ORIGINATING ON A 4K BYTE BOUNDARY AND
DOUBLE WORD ALICNED
DOUBLE WORD ALIGNED
128K BYTES OF CONTIGUOUS MEMORY ORIGINATING ON A 4K BYTE BOUNDARY AND DOUBLE WORD ALIGNED
PROGRAM /DATA SPACE
128K BYTES OF CONTIGUOUS MEMORY
US. Patent
Nov. 14, 2000
Sheet 10 0f 39
6,148,389
FIG. 22 PING BUFFER
2150\ REGION LIST (i) REGION POINTER 0
DMA TRANSFER TABLE
'
(LINKED LIST)
' REGION POINTER M
REGION LIST 0
REGION LIsT I
sGATIER LOCKED
REGIONS 2)“) > REGION 0
3
2120
/ 7 REGION M
REGION CAN NOT
PONG BUFFER REGION LIST (j)
DICEED 128K BYTES'
REGION LIST 3 .
REGION POINTER 0
:
7 REGION 0
~
-
j
'
\
2130
REGION LIST L
REGION POINTER N
2160/
DMA TRANSFER TABLE
REGION N
2I4O
US. Patent
Nov. 14, 2000
Sheet 11 0f 39
6,148,389
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US. Patent
Nov. 14, 2000
Sheet 12 0f 39
6,148,389
FIG. 24 REGION LIST RECORD NEXT LIST OFFSET
PREVIOUS LIST OFFSET
REGION COUNT
REGION 0
REGION RECORD 0 P NTER 3 —BlT
0'
(2
i OFFSET
S)
VALID DATA
‘f
LENGTH (BYTES)
LET-“H REGION N
REGION RECORD N
VALID DATA
T
POINTER (32-BITS)
LENGTH
LENGTH (BYTES)
i
I<—32-BIIs-——>|
0) REGION RECORD 0 — POINTER (32-BITS)
31
12 11
O OFFSET ——-—>
<——————-—-—— POINTER ———————>
b) REGION LIST STRUCTURE
US. Patent
Nov. 14, 2000
Sheet 13 0f 39
6,148,389
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U.S. Patent
Nov. 14, 2000
Sheet 14 0f 39
6,148,389
FIG. 2 6 COMMANO BUFFER
(CIRCULAR BUFFER) HEAD POINTER 16-BIT
TAIL POINTER 16-BIT COMMAND‘ REC WRITTEN BY HOST
l
COMMANO REC O
256 BYTEs
COMMANO REC I
T
COMMANO PARAMETERS ‘
OLOEsT COMMANO
TAIL POINTER
(MANIPULATEO BY DSP)
\ NOTIFICATION REC HEAD POINTER
NEWEST COMMANO
WRITTEN BY DSP
(MANIPUIATEO BY HOST)
(RETURN PARAMETERS) COMMANO REC 8
MANIPULATEO BY HOST
W EvENT BUFFER
(CIRCULAR BUFFER) HEAD POINTER 16-BIT
l
TAIL POINTER 16-BIT
256 BYTES
EVENT REC 0
EVENT REC WRITTEN
1‘
MM REC 1
BY DSP EvENT
TAIL POINTER
PARAMETERS
=
(MANIPULATEO BY HOST)
(IF ANY)
OLDEST EvENT NEWEST EvENT
‘
HEAD POINTER
(MANIPUIATEO BY DSP) COMMUNICATION BUFFER
V N R E E EC 8
US. Patent
Nov. 14, 2000
Sheet 15 0f 39
6,148,389
A
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US. Patent
Nov. 14, 2000
Sheet 17 0f 39
6,148,389
F] G. 29 DRAM
INTEGRATED
GRAPHICS
' CPU COMPLEX
PC] BUS
BIOS
LCD
CONTROLLER
M
A
v
V
'
DISPLAY
TT
L
T
,
I
l/O
PCMClA
COMBO
CONTROLLER
SERIAL BUS WIRELESS
XD BUS
9
LAN
KEYBOARD
MOUSE
DSP
CONTROLLER
DSP/IDE
I HDD
I FDD
OPTION 1
SP PP
I
sLOTT SLOT2 OPTION 2
US. Patent
Nov. 14, 2000
PC‘ 8 5
FIG.
U
BIOS
Sheet 18 of 39
30
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