Transcript
3.1-5GHz ultra-wideband architecture and low-power design methodology Atit Tamtrakarn and Takayasu Sakurai Sakurai laboratory, Institute of Industrial Science, the University of Tokyo
Recently, ubiquitous electronics becomes a hot topic of interest among electronics consumer companies and researchers. Many circuits and applications trend to be shrunk for portable purpose, then circuit can only drain energy from limited sources. Moreover, wired-communication among each device is getting more difficult due to plenty of chips in the ubiquitous electronics environment. Thus, low-power wireless communication circuit design techniques become important and necessary [1]. Ultra-wideband (UWB) is a wireless communication scheme which is mainly composed of digital blocks. Power consumption seems to be lower than other analog-based transceiver. This paper presents a new architecture and low-power design methodology for UWB RF transceiver to achieve ubiquitous electronics goal.
no need of impedance matching in these gain stages, there is no need to use configuration of common gate like LNA. Low input impedance of common gate structure will reduce the total output impedance which means reducing of the total gain. So, common source topology is used as amplifier in these gain stages to maximize the total gain. The third block is pulse detector which is only a dynamic sense amplifier; in figure 2b. Incoming pulse can be detected in time-domain by applying correct timing clock which is generated by high-level synchronization protocol. Power is mainly drained by LNA and five gain stages which are more than 90 percent of total power consumption. Since the transconductance of LNA is fixed to 20mA/V, the current consumption is also fixed. Therefore, the key to low-power design solution is to minimize current consumption in each common source gain stage.
2. A new architecture of 3.1-5GHz UWB system
4. Summary
The conventional UWB communication scheme occupies bandwidth from 3.1-10.6GHz. According to Hartley-Shannon’s law [2], ultra high communication speed up to 750Mbps is possible in noise flooded (SNR=0.1) system, because of ultra wide bandwidth of 7.5GHz. Anyway, some applications need only medium speed, but low-power consumption. Bandwidth of 7.5GHz is too wide and consumes too much power. This paper suggests reducing bandwidth to suit with applications need because excess bandwidth causes unnecessary power consumption. A new architecture of 3.1-5GHz UWB transceiver is proposed here in figure 1. The architecture is bi-phase pulse-based communication scheme. Pulse detector is used, instead of correlator in the conventional architecture [3], to alleviate the difficulty of pulse template generator.
The proposed architecture and low-power design methodology is verified by MATLAB and Spice simulation. The speed of 500 Mbps can be achieved. The current drain from 1.5V supply voltage is only 4.5mA which is six times lower than conventional narrow-band Bluetooth transceiver.
1. Introduction
5. References [1] T.Sakurai, “Perspectives of Power-Aware Electronics (invited plenary),” ISSCC, pp.26-29, February 2003. [2] A.Tamtrakarn, T.Sakurai, “Medium-loss considerations for designing an ultra-wideband transceiver,” IEICE Society conference 2004, September 2004. [3] T.Terada, S.Yoshizumi, Y.Sanada, and T.Kuroda, “Transceiver circuits for pulse-based ultra-wideband,” ISCAS, pp.349-352, 2004.
3. Low-power circuit design methodology This section explains low-power circuit design techniques of proposed UWB architecture. For the transmitter side, a simple inverter is used as power amplifier. The configuration of an inverter acts like a class AB power amplifier which operates in a very small period of rising or falling input edge. There are four blocks in the receiver side. The low noise amplifier (LNA) is used to match impedance with antenna and provide some gains to minimize noise figure of the whole system. Wideband matching is very difficult for the conventional common source LNA. Hence, common gate LNA configuration is used as shown in figure 2a. One disadvantage of this topology is the transconductance of input transistor is fixed to the constant value of 20mA/V to match with 50-ohm impedance of antenna. The gain stages are composed of five amplifiers which provide enough gain to amplify incoming pulses. Since there is
Figure 1 A new UWB architecture
Figure 2 Circuit diagram of LNA and pulse detector
