Transcript
3D-INTEGRATED CIRCUITS: A FOCUS ON SIGNAL INTEGRITY AND ELECTROMAGNETIC COMPATIBILITY
Etienne SICARD INSA/DGEI University of Toulouse 31077 Toulouse - France
[email protected] www.ic-emc.org 1
TOULOUSE - FRANCE
Founded in -120 B.C (heavy history)
Airbus A380 (heavy airplane)
Cassoulet (heavy food)
Best place to study in France (2011 ranking) (heavy responsibility)
Rugby (heavy efforts) 2
1
SUMMARY
I.
EMC ISSUES
II.
EVOLUTION OF ICS AND CONSEQUENCE ON EMC
III.
3D IC TECHNOLOGY
IV.
MEASUREMENT OF 3D-IC EMISSION AND SUSCEPTIBILITY
V.
MODELS FOR 3D-EMC SIMULATION
VI.
DESIGN GUIDELINES FOR IMPROVED EMC
3
I. EMC ISSUES
4
2
GENERAL EMC ISSUES – ALL DOMAINS
http://www.interferencetechnology.com > markets > news
5
October 12 5
INDUSTRIAL PRESSURE
SUSCEPTIBILITY Carbon airplane
EMISSION Equipements
Personal entrainments
Mobile phone
Boards
Radar Components
Safety systems
Control Systems
6
3
EMC AT IC LEVEL WHEN EMC OF ICS STARTED? • Until mid 90’s, IC designers had no consideration about EMC problems in their design.. • Starting 1996, automotive customers started to select ICs on EMC criteria • Starting 2005, mobile industry required EMC in System in package • Starting 2015, massive 3D integration will require careful EMC design • “Urgent Need to Integrate EMC and Product Safety into Engineering Curriculum of Technical Universities” 7
7
October 12
3D-IC DRIVING FORCES We are Here
THE GIANT SCALE MOBILE PHONE INDUSTRY
Average bandwidth Boundaries
Bandwidth (bit/s)
3G+ (1 Billion)
100M
3G (1 Billion)
10M
2G (4.5 Billion users)
1M 100k 10k
1998
LTE-A 40 M
HSUPA 4M
4G (0.1 Billion)
UMTS 120 k
GPRS 64k
GSM 14k
1996
HSDPA 1.0 M
LTE 20 M
2000
2002
2004
2006
2008
2010
2012
2014
Year 8
4
3D-IC DRIVING FORCES
4G REQUIRES 4 CAMERAS, 10+ PROCESSORS, GB MEMORY • Texas Instruments OMAP 5430 example • 3D Ics are used for memories and camera modules
• • • • •
2008 : “Why 3D?” 2010 “”How 3D? 2012 : “When 3D?” … 20xx : “Why 2D?” 9
EMC IN 3D-ICS
HOW TO ENSURE EM COMPATIBILITY OF THIS ..?
Georgia-Tech vision of SoC
From Georgia Tech 3D system packaging research http://www.prc.gatech.edu.
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October 12
10
5
EMC MARGIN
MIXING EMISSION AND IMMUNITY LEVELS Emission and immunity levels (dB)
Immunity 50
Interference risk
40
Emission
30
Security margin
20
Small margin
10
Immunity
0 -10
Emission
-20
FREESCALE « 3G phone in a package » using RCP technology
-30 -40 1
10
100
1000
Frequency (MHz) 11
EMC MARGIN
LINK BETWEEN MARGIN AND APPLICATIONS Why a margin
Acceptable noise level
Ioff/Ion MOS 32-nm
Immunity vs. ageing (LTOL)
Security Process variations
PhD A. C. Ndoye, INSA, 2010
Measurement error Margin depends on application Ageing Environment
Domain
Life time
Margin
Aeronautics
30 years
40 dB
Automotive
15 years
20 dB
Mobile phone
1 year
0 dB
Required noise level
12
6
LOW EMISSION = DIFFERENTIATOR
EMC IS CRITERION FOR SELECTING IC SUPPLIERS Supplier A
dBµV
FM
GSM
RF
100
Not EMC compliant A
80
Customer's specified limit
60
B
40
Supplier B
20
EMC compliant
0 10
100
1000 13
SUSCEPTIBILITY ISSUES
UNINTENTIONAL ELECTROMAGNETIC SOURCES Power
HF
VHF
UHF
SHF
xHF
THF
• Fields radiated by electronic devices • Continuous waves & pulsed waves
Weather Radar
1GW
Radars 1MW Thunderstorm impact 1KW
TV UHF
TV VHF 2-4G BS
1W
4G 2G 3G
1mW
Frequency 3 MHz
30 MHz
25m
2.5m
300 MHz 0.25m
3 GHz 25mm
30 GHz
300 GHz
2.5mm
0.25mm
λλ/4 (ideal antenna)
14
7
II. EVOLUTION OF IC TECHNOLOGY AND CONSEQUENCE ON EMC
15
HIGHER COMPLEXITY
10 GIGA-DEVICE ICS
Technology
130nm
90nm
100M
250M
200 4
2006
32nm
22nm
5nm
500M
2G
7G
150 G
2008
2010
45nm
Complexity
Packaging
Embedded blocks
Core+ DSP 1 Mb Mem
Core DSPs 10 Mb Mem
Dual core Dual DSP RF Graphic Process. 100 Mb Mem Sensors
2012
Quad Core Quad DSP 3D Image Proc Crypto processor Reconf FPGA, Multi RF 1 Gb Memories Multi-sensors
2020 ?
16
8
HIGHER PARASITIC EMISSION High K Metal Gate to increase field effect
INCREASED SWITCHING DEVICE PERFORMANCES
Tri-Gate for increasing drive current and reducing leakage
Strain to increase mobility
Current drive (mA/µm) 2.0
1.5 Gate material
1.0 Strain
0.5 Intrinsic performances
0.0 130 nm
90 nm
65 nm
45 nm
32 nm
22 nm
17 nm
Technology node 17
HIGHER PARASITIC EMISSION
WHY TECHNOLOGY PROGRESSES INCREASE EMISSION • The current amplitude is a little reduced • The switching is faster
Volt Old process New process Time
Current
Vss
Old process di/dt New process
Vdd
∆V = L
∆i ∆t
Time The noise is increased 18
9
INCREASED SUSCEPTIBILITY DECREASED NOISE MARGIN IN ICS Supply (V)
500 mV margin
100 mV margin
5.0
3.3
I/O supply
2.5
Core supply
1.8 1.2 1.0
0.5µ
0.35µ
0.18µ
130n
Technology
90n
65n
45n
32n
22n
17n
Adapted from ITRS roadmap for semiconductors, 2011
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October 12
19
3D-IC EMC CHALLENGES BASIC EMC ISSUES IN 3D-ICS
J. Kim; IEEE EMC Society Distinguished Lecturer Seminar: Signal Integrity of TSV-Based 3D IC
20
October 12
20
10
III. 3D-IC TECHNOLOGY
21
3D-IC DRIVING FORCES
MEMORIES AND IMAGERS
3D-IC DRIVING FORCES
From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev.
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11
3D-IC BENEFITS
3D TECHNOLOGY Enables the integration of ics fabricated in different technologies : Cmos, CCD, SOI, sensors, MEMS
0.18µm SOI 0.35 µm SOI Sensor
B. Aull, et. al., “Laser Radar Imager Based on 3D Integration of GeigerMode Avalanche Photodiodes” IEEE SSCC 2006.
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4µm vias Bosch process
C. Bower, et. al., “High Density Vertical Interconnects for 3D Integration of Silicon ICs,” 56th ECTC, San Diego, 2006.
October 12
23
3D-IC TECHNOLOGY Process accessible by CMC, CMP and MOSIS for academics, SME and industries
TERRAZON PROCESS WITH DBI & FLIP CHIPS
Direct bond interconnect
From CMP annual users meeting, “3D-IC Integration”, January 20th 2011, PARIS
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October 12
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12
3D-IC EXAMPLE
Development of 3D Integrated Circuits for HEP, R. Yarema, 2006
3D IC Pixel Electronics, the Next Challenge, R. Yarema, 2008
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25
October 12
3D-IC EFFICIENCY
IMPROVED ELECTRONIC EFFICIENCY • 3D reduces interconnect length > inductance effects • 3D simplifies multiple supply voltage distribution • 3D reduces package pin count • More uniform, high density power delivery
J. Lu, “Monolithic 3D Power Delivery Using Dc-Dc Converter”, 3D Architecture Conference, October, 2006, Burlingame, CA.
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October 12
26
13
3D-IC BENEFITS
DIE BONDING VS THROUGH SILICON VIA
Z0 ≈
L ≈ 200Ω c
Z0 ≈ 27
l ≈ 50Ω C
EMC-3D Consortium Overview and CoO Model, Paul Siblerud, www.emc3d.org 27 October 12
SIGNAL INTEGRITY IN 3D-ICS
A SIGNIFICANT DECREASE OF OVER/UNDERSHOOTS
HDI PCB
2D
3D
Buffer
3-stage
1-stage
Pad Load
3-5 pF
1 pF
Interconnect capa
5-20 pF
0.1-5 pF
Interconnect inductance
5-30 nH
0.1-2 nH
Current drive
10-100 mA
1-10 mA
28
Stacked die bonding
3D TSV
October 12
28
14
SIGNAL INTEGRITY IN 3D-ICS
A SIGNIFICANT REDUCTION IN I/O COMPLEXITY •
Most Electrostatic Discharge, overstress protections can be removed
Solder ball
ESD protection
Voltage translation and level shifers
29
October 12
29
POWER EFFICIENCY 3D-ICS
A BETTER POWER EFFICIENCY • Shorter wires decrease the average parasitic inductance and resistance and decrease the number of repeaters needed for long wires. • Capacitance is reduced if the dies are thinned (350 > 10-100 µm) • The wire efficiency is improved by 10-100 % • Power dissipation may be reduced by a factor of 2-10
T. Topol « Three-dimensional integrated circuits », Ibm Journal Research, 2006
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Lili Zhou, "Implementing a 2-Gbs 1024-bit ½-rate Low-Density Parity-Check Code Decoder in 3D-Ics « , ICCD 2007 October 12
30
15
3D-IC INTERFACING
NO I/O STANDARDIZATION BETWEEN INTERFACES • Cost-effective high-volume manufacturing will be difficult to achieve unless manufacturing standards are developed • Identify and create new standards in 3DICs.
Through silicon via size Interposer and die thickness Microbump dimensions Electrical behavior of I/Os
• No I/O standardization at present • IBIS could play an important role for standard interfacing
From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev. From ITRS Roadmap
From http://www.semi.org/node/37306
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October 12
31
IV. MEASUREMENT OF 3D-IC EMISSION & SUSCEPTIBILITY
32
16
3D-IC MEASUREMENT METHODS
IEC – International Electro-Technical Commission - www.iec.ch
WG 2 : Digital integrated circuits Members
SC 47A : integrated circuits
International Electrotechnical Commission
Secretary : Japan
169 technical committee
Work Group WG 2 : Digital integrated circuits
TC 4 : hydraulic turbines TC 20 : electric cables
USA
Germany
Japan
France
South Korea
Belgium
Poland
Italy
England
Netherlands
WG 4 : Interface integrated circuits
SC 46A : coaxial cables WG 7 : Advanced hybrid integrated circuits
SC 47A : integrated circuits
WG 9 : Test procedures and measurement methods for EMC of ICs
WG 9 : Test procedures and measurement methods for EMC of ICs
. . .
Worldwide expert meetings, defending national industrial approaches
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Members USA
Germany
Japan
France
South Korea
Belgium
Poland
Italy
England
Netherlands
33
October 12
3D-IC MEASUREMENT METHODS
STANDARD EMC TEST BOARD – 2D/3D DOES NOT MAKE DIFFERENCE Via row Metallization
100 mm
Connections of IC by 0.25mm vias
Ground plane under IC
DUT Additional holes
Connection layer 1 to 4 by 0.8mm vias
Decoupling of supply on this part of ground plane
Top layer – DUT layer
Tinned
Layer 1 – Ground Layer 2 – Power supply Layer 3 – Signal Layer 4 – Ground and/or signal
Bottom layer – Additional component
34
October 12
34
17
3D-IC MEASUREMENT METHODS
STANDARD IC EMISSION MEASUREMENT METHODS - IEC 61 967 IEC 61967-2 (TEM : 1 GHz)
IEC 61967-3/6 (Near-field Scan, 5 GHz)
IEC 61967-4 (1/150 Ω, 1 GHz)
IEC 61967-8 (Mini-stripline)
IEC 61967-7 (Mode Stirred Chamber : 18 GHz)
Ext : IEC 61967-2 (GTEM 18 GHz)
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3D-IC Measurement Methods
IEC 61 967 – 2 “TEM/GTEM CELL” -8 “IC-STRIPLINE”
Upper IC may play the role of shielding
Upper IC is closer to septum
45 mm for TEM, 6.7 mm to Stripline
6,7 mm IC-Stripline cross-section
TEM/GTEM cross-section
TEM/GTEM cross-section
45 mm
Low SSN on top
High SSN on top 36
October 12
36
18
3D-IC MEASUREMENT METHODS
IEC 61 967 – 3/6 “NEAR-FIELD SCAN”
Combining laser and high-precision NFS may lead to precise 3D investigations
But lower die stack shielded by upper dies
Faster 3D scan: may use « cubeprobe » (isotropic measurement of Hx, Hz, Hz) for Hmax measurement
D. Baudry, PhD report, ESIGELEC, Univ Rouen, 2005 37
37
October 12
3D-IC MEASUREMENT METHODS
IEC 61 967 – 4 “1/150 Ω METHOD”
Each die would have a built-in 1 Ω probing for IC emission characterization Integrated Circuit Sub-component Silicon Die
PDN package
Passive Distribution Network
PDN
IA Internal activity
PDN Embedded passives
IB Σ,Π
Immunity behavioral
Other silicon die
Other sub-component
1 Ω die 1
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October 12
1 Ω die 2
1 Ω die 3
38
19
3D-IC MEASUREMENT METHODS
INTERNATIONAL STANDARDS FOR IC SUSCEPTIBILITY MEASUREMENTS IEC 62132-3 (Bulk Current Injection : 1 GHz)
IEC 62132-4 (Direct Power Inj 1GHz)
IEC 62132-2 (TEM/GTEM)
IEC 62132-5 (WBFC 1 GHz)
IEC 62132-6 (LIHA : 10 GHz)
IEC 62132-8 Mini Stripline
39
October 12
39
October 12
40
3D-IC MEASUREMENT METHODS
3D-RELEVANT IMMUNITY MEASUREMENT METHODS (RESEARCH) Skate-probe
On-chip sampling
Analog JTAG
DPI+NFS
40
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3D-IC MEASUREMENT METHODS
IEC 62 132 – 3 “BCI METHOD”
BCI is 5 Kg, 20 cm diameter
3D-IC is 3g, 25 mm square
3D-IC connected to a bus (CAN, LIN..) or sensors ?
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41
October 12
3D-IC MEASUREMENT METHODS
IEC 62 132 – 4 “DPI METHOD”
http://ecubes.epfl.ch
Each die would have built-in injection probes for IC immunity characterization Integrated Circuit Sub-component Silicon Die
PDN package
Passive Distribution Network
PDN
IA Internal activity
PDN Embedded passives
IB Σ,Π
Immunity behavioral
Other silicon die
Other sub-component
to die 1
42
October 12
to die 2
to die 3
42
21
3D-IC MEASUREMENT METHODS
IEC 62 132 – 4 “DPI METHOD”
Extension of injection to 10 GHz « xDPI » concept
DPI Capa (10-100 pF)
TSV to IC
RFI
DC Polarization and Isolation resistance (or embedded L)
DC
PCB Board level
Interposer level 100 µm
1 mm 43
October 12
43
3D-IC MEASUREMENT METHODS
IEC 62 132 – 2 “TEM/GTEM METHOD”, - 8 “MINI-STRIP LINE”
Mini strip-line efficient for injection (3%)
Canonical field Strip line cross-section
6.7 mm
EMC test board F. Klotz, « IC-Stripline, new method for emission and immunity », EMC Compo 2009 44
October 12
44
22
3D-IC MEASUREMENT METHODS
SKATE PROBE PRINCIPLES Investigate “what-if 3D” by manual positioning in X,Y,Z Avoid the cost of 3D prototypes Ensure EMC prior to 3D-IC design
Characterization of the aggressor NF emission
3G PA
3G Transceiver
RF Stage
Processor
Memory
Numerical part
3G LNA 2G PAs
Power management
2G Transceiver
The aggressor SkateProbe design
SkateProbe validation
Measurement of the coupling between the SkateProbe and the victim
An Innovative Methodology for Evaluating Multi-Chip EMC in Advanced 3G Mobile Platforms, S. Akue Boulingui, IEEE EMC Symp Austin, 2009
Victim component
45
October 12
45
October 12
46
3D-IC MEASUREMENT METHODS SKATE PROBE – CASE STUDY Aggressor : 3G Power amplifier
Victim : 3G transceiver
46
23
3D-IC MEASUREMENT METHODS
SKATE PROBE – CASE STUDY 3D positioning of the aggressor above the victim SNR characterization with/without disturbances
11 mm
Power meter
14 mm
50 Ω load -6 dB
SNR reference curve
PA_SkateProbe Transceiver
-5,5 (dB) SNRSNR (dB)
Coupler Power amplifier
SkateProbe signal
-4,5
SNR target
With disturbance
-6,5
-7,5
Desired signal
USB conexion
-8,5 2110
2120
2130
2140
2150
2160
2170
Frequency (MHz)
47
October 12
47
3D-IC MEASUREMENT METHODS
ON-CHIP SAMPLING Simple Sample/Hold analog cell to probe voltages & currents Sampling command
Sensor S/H cell
Attenuator
+
Output amplifier
_ High impedance probe
Sampled data
Signal to measure
S. Ben Dhia, “On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations”, IEEE Trans. Instr. Meas, 2012
Enrique LAMOUREUX, PhD 2006, INSA Toulouse, France
48
October 12
48
24
3D-IC MEASUREMENT METHODS
ON-CHIP SAMPLING Setup with DPI Clock and Data trig the IC under test
High frequency
Switching
Low frequency
Switching
Switching
49
49
October 12
3D-IC MEASUREMENT METHODS
40
EMI transfer function (dB V/W)
ON-CHIP SAMPLING Extraction of the transfer function of the IC, strongly dependant on F On-chip sensing bandwidth linked to technology 2 GHz 0.25µm, 20 GHz 22 nm
30
Simulation Measurement
20 10 0
-10 -20 -30 -40 -50
1,E+06
1,E+07
1,E+08
1,E+09
Frequency (Hz)
S. Ben Dhia, “On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations”, IEEE Trans. Instr. Meas, 2012
50
October 12
50
25
3D IC Measurement Methods
ANALOG JTAG Usable with digital JTAG boundary scan Adds analog testability – both controllability and observability Eliminates large area needed for analog test points
Agrawal, “IEEE 1149.4 JTAG Analog Test Access Port and Standard”, VLSI Test Lecture 2001
51
October 12
51
October 12
52
3D IC MEASUREMENT METHODS
COMBINED DPI AND NFS Idea: inject in direct power injection and measure in Near-field scan Tool for observing the 3D-IC from outside May help investigating the coupling paths and build accurate models
A. Alaeldine “Analysis of the Propagation of EM Disturbances Inside Integrated Circuits Using DPI and NFS”, IEEE EMC Austin 2009
DPI off
DPI on
52
26
V. MODELS FOR EMC SIMULATION
53
EMC-AWARE DESIGN CYCLE
EMC VALIDATED BEFORE FABRICATION
DESIGN
Tools Training
Architectural Design
Design Guidelines Design Entry Design Architect EMC Simulations Compliance ?
FABRICATION
NO
GO
EMC compliant
54
27
IEC STANDARD MODEL APPROACH
IEC 62 433 – EMISSION (ICEM) AND IMMUNITY (ICIM) MODELS Conducted mode models in industrial use 1. ICEM-CE - Conducted RF emission
2. ICEM-RE - Radiated RF emission
www.iec.ch
4. ICIM-CI - Conducted RF immunity
4. ICIM-RI - Radiated RF immunity
55
GENERIC FLOW
EMC SIMULATION FLOW AT IC LEVEL The DUT is isolated on a simple EMC board to minimize modeling effort
Test bench Model
Test board Model
Package Model
EMC Model for the circuit
Core – I/O Model
Simulated Emission spectrum
Electrical Simulation 56
28
EMISSION CASE STUDY
INFINEON TRICORE™ - TEM CELL MODEL Capacitance coupling to the TEM cell Conversion to Win-SPICE Probe Model Test board Model
Analog Time-Domain Simulation
6.6ns (150MHz))
1.0A 0.5A
Fourier Transform
0A
Core current model
Package Model
dB vs Freq (log) conversion
Core Model
57
EMISSION CASE STUDY
INFINEON TRICORE™ - TEM CELL EMISSION Infineon TriCore™ measurement/simulation comparisons Radiated noise in GTEM cell (dBµV)
Predictive model
Measure
Correct envelop
Reasonable match
Simulation 15 dB above measurement starting 700 MHz
Manual fit leads to 5 dB max difference
58
29
DOWN-SCALING TO MULTI-DIES
EMISSION MODEL OF MULTI-DIE 2D/3D ICS One-die to multi-die model
Integrated Circuit (ICEM, ICIM)
Integrated Circuit (ICEM, ICIM) Sub-component
Sub-component
Silicon Die/ Intellectual property
PDN package
Passive Distribution Network
PDN
IA Internal activity
PDN Embedded passives
IB Σ,Π
Immunity behavioral
Silicon die Other silicon die
Other sub-component
59
59
3D-IC MODEL
THROUGH SILICON VIA MODEL Low loss upto 30 GHz
• TSV diameter : 55 µm • TSV SiO2 thickness : 0.5 µm
J. Kim; IEEE EMC Society Distinguished Lecturer Seminar: Signal Integrity of TSV-Based 3D IC
60
October 12
60
30
3D-IC MODEL
THROUGH SILICON VIA MODEL Large capacitance for large & long TSVs
Resistance and Capacitance values in mΩ and fF M. B. Healy, “A Study of Stacking Limit and Scaling in 3D ICs: An Interconnect Perspective”, 2009 Electronic Components and Technology Conference
61
October 12
61
3D-IC MODEL
THROUGH SILICON VIA MODEL • •
Tall 3D Ics lead to significant L. Crosstalk should also be considered
M. B. Healy, “A Study of Stacking Limit and Scaling in 3D ICs: An Interconnect Perspective”, 2009 Electronic Components and Technology Conference
62
PAK et al.: Pdn impedance modeling and analysis of 3D TSV IC, IEEE Trans on components, packaging, and 62 manuf. tech, Feb 2011
31
3D-IC DELAY MODELING
DELAY VS. INTER-DIE OPTIONS •
Stacking strategy may reduced delay by 80%
F2F
J. Roulard, Electrical Characterization and Impact on Signal Integrity of New Basic Interconnection Elements inside 3D Integrated Circuits, 2011 Electronic Components and Technology Conference
F2B
63
63
October 12
3D-IC EMC PERFORMANCES
EMISSION PREDUCTION
mem µC Package
• • •
Long bonding act as antennas l/4 eq. 5-15 GHz Important conducted, radiated noise
• • • •
Mem acts as a shielding Very fast µC/mem exchanges Still important antenna Medium emission (conducted/radiated)
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October 12
• • • •
Shielding of mem, µC No antenna effect TSV may act as a load and slow down mem/µc exchanges Low emission
64
32
3D-IC MODEL
EMISSION PREDICION •
3D-TSV technology may reduce emission by 30 dB vs PCB, and 15 dB vs die stack with wire bonding
Radiated emission (dBµV)
-30 dB
Frequency E. Sicard, Wu Jianfei www.ic-emc.org “3D-IC Case study” 65
3D-IC POWER INTEGRITY
Maximum power noise (mV) with varied settings
POWER INTEGRITY MODELING Power delivery by specific TSVs
Young-Joon Lee, Co-design of Reliable Signal and Power Interconnects in 3D Stacked Ics, 2009
66
October 12
66
33
3D-IC POWER INTEGRITY
POWER INTEGRITY MODELING Core placement strategy has a direct impact on voltage drops
Voltage drop as a function of time.
The dynamic noise as a function of TSV dimension in µm (40 x 40 TSV)
M. B. Healy, “A Study of Stacking Limit and Scaling in 3D ICs: An Interconnect Perspective”, 2009 Electronic Components and Technology Conference
67
October 1267
IEC STANDARD MODEL APPROACH IEC 62433-4 – “ICIM CONDUCED IMMUNITY” Based on ICEM, add non-linearities
IB
ICIM – immunity model Package
RF disturbance
Coupling path Monitoring of the failure
External pins
IC PDN
Internal Behaviour IB
Package PDN
detection
Silicon die PDN = Passive Distribution Network
PDN Package
Close to ICEMCE
Close to ICEM Add Diodes (camp, back-toback, ESD, EOS)
New!
68
34
IMMUNITY SIMULATION
S12X CASE STUDY – DPI ON AN INPUT
• • • • •
16 bit micro-controller Direct power injection Input buffer aggression Sinusoidal mode Simulation criterion: Logical change of input buffer From A. Boyer’s PhD, INSA, 2007
69
VI. DESIGN RULES FOR IMPROVED EMC
70
35
DESIGN RULES
GUIDELINE 1 : REDUCE THE INDUCTANCE
VDD
Why: because inductance is a major source of resonance Where is the inductance: in each conductor, worst is far from ground
IC IC
VDD VSS
L=1 nH/mm
VSS
71
DESIGN RULES
GUIDELINE 2 : PLACE VDD/VSS CLOSE TO STRONG DI/DT Tools required to forecast strong di/dt effects
Multiple VDD, VSS
72
36
DESIGN RULES
GUIDELINE 3 : PLACE VDD-VSS CLOSE • •
to reduce current loops that provoke magnetic field to increase decoupling capacitance that reduces fluctuations Added contributions
Canceled contributions Canceled (-20 dB)
EM wave
current Added Lead
Lead Die 73
DESIGN RULES
GUIDELINE 4 : USE ONE VDD/VSS FOR 10 I/OS • •
BGA examples
To reduce current loops To reduced LC effects
Correct
Fail 3D-TSV examples
9 I/O ports J. S. Pak “PDN Impedance Modeling and Analysis of 3D TSV IC », IEEE Transactions on components, packaging, and manuf. Tech. vol. 1, no. 2, Feb. 2011
Both correct
74
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DESIGN RULES
GUIDELINE 4 : USE ONE VDD/VSS FOR 10 I/OS FPGA CASE STUDY
Poor design:x 5 mode switching noise
© Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
75
DESIGN RULES
GUIDELINE 5 : PLACE ON-CHIP DECOUPLING CLOSE TO STRONG DI/DT • • •
1nF added close to the core More than 15 dB noise reduction Selected areas: • Logic Core • Charge pump (FLASH) • Fast I/Os (DDRx)
B.Vrignon CESAME test-chip IEEE Trans EMC 2006
10/22/2012
Graduate Student Meeting on Electronic Engineering - Tarragona
76 76
38
DESIGN RULES
GUIDELINE 5 : PLACE ON-CHIP DECOUPLING CLOSE TO STRONG DI/DT Filler-cap at the output buffer area Pad
High speed port
Protection circuit
VDD Protection circuit VSS
Core
High speed port
Filler-cap 77
DESIGN RULES
GUIDELINE 6 : ADD JIITTER ON THE CLOCK
-8 dB
© B. Vrignon, Freescale SAS
78
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DESIGN RULES
GUIDELINE 7 : ADD RC FILTERING TO ISOLATE NOISE RC filtering works both Susceptibility level for emission and immunity
RC Code
Isolated Core Ali ALAELDINE , PhD Eseo France
Normal Core
Frequency (MHz)
79
FUTURE
INNOVATIVE EMC … Not? … and Why
« Zero » emission designs
cancel all fields
negligeable external di/dt
De-synchronized parts
RFI, ESD, EOS, EFT supply
Detector
« Zero » susceptibility designs
Clamp, filter
Protect, shield by design, materials
Defensive core
Critical decision
Critical sensor
Reduce frequency Reduced VDD Smart capa management Redundancy
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CONCLUSION
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CONCLUSION
•
Higher complexity and frequencies, technology scale down make EMC more and more challenging
•
EMC is still investigated late in the design flow
•
Mature standard measurement methods dedicated to ICs
•
New standards for EMC modeling at IC level
• • • •
Good prediction of emission and susceptibility up to 2 GHz for 2D-ICs 3D-ICs speed up signal propagation, consumes less power Many 3D-IC technologies co-exist, no standard New EMC Challenges in 3D due to die-die proximity, protection simplification Signal Integrity closely linked to via technologies PDN & Power Integrity linked to 3D choices Standard and new measurement methods available EMC impacted by positioning, designs, filtering and assembly options 3D-EMC still in infancy stage, a huge room for innovation
• • • • •
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REFERENCES
Books
Workshops Standards www.iec.ch
www.springeronline.com Tools
www.emccompo.org EMC Compo in Dec 13 Nara Japan
• IEC 61967, 2001, Integrated Circuits emissions • IEC 62132, 2003, integrated circuits immunity • IEC 62433, 2006, Integrated Circuit Model • IEC 62215, 2009 Transcient immunity
Melbourne, Australia from 20 – 23 May 2013 www.apemc13.org www.ic-emc.org
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Merci beaucoup pour votre attention Thank you very much for listing • • • • • •
The audience The IEEE Solid State Circuits Society, Switzerland The IEEE Electron Device Society, Switzerland The IEEE Student Branch, EPFL Wladyslaw Grabinski Lucian Barbut
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