Transcript
SRC4194 SBFS025B − JUNE 2004 − REVISED SEPTEMBER 2007
4-Channel, Asynchronous Sample Rate Converter FEATURES D
AUTOMATIC SENSING OF INPUT-TO-OUTPUT SAMPLING RATIO
D
WIDE INPUT-TO-OUTPUT SAMPLING RANGE: 16:1 to 1:16
D
SUPPORTS INPUT AND OUTPUT SAMPLING RATES UP TO 212kHz
D
DYNAMIC RANGE: 144dB (−60dbFS Input,
D D
THD+N: −140dB (0dbFS Input, BW = 20Hz to fs/2)
D
HIGH-PERFORMANCE, LINEAR-PHASE DIGITAL FILTERING WITH BETTER THAN 140dB OF STOP BAND ATTENUATION FLEXIBLE AUDIO SERIAL PORTS: − Master or Slave Mode Operation − Supports I2S, Left-Justified, Right-Justified, and TDM Data Formats − TDM Mode Allows Daisy-Chaining of Up to Four Devices SUPPORTS 24-, 20-, 18-, or 16-BIT INPUT AND OUTPUT DATA: − All Output Data is Dithered from the Internal 28-Bit Data Path
D
SERIAL PERIPHERAL INTERFACE (SPI) PORT SUPPORTS REGISTER READ AND WRITE OPERATIONS IN SOFTWARE MODE
D
BYPASS MODE: − Routes Input Port Data Directly to the Output Port
D
DIRECT DOWNSAMPLING OPTION FOR THE DECIMATION FILTER
D
DIGITAL DE-EMPHASIS FILTER: − User-Selectable for 32kHz, 44.1kHz, and 48kHz Sampling Rates
D D
SOFT MUTE FUNCTION PROGRAMMABLE DIGITAL OUTPUT ATTENUATION (SOFTWARE MODE ONLY): − 256 Steps: 0dB to −127.5dB with 0.5dB Steps
D D
POWER-DOWN MODES
D
AVAILABLE IN A TQFP-64 PACKAGE
SUPPORTS OPERATION FROM A SINGLE +1.8V OR +3.3V POWER SUPPLY
D D D D D
DIGITAL MIXING CONSOLES DIGITAL AUDIO WORKSTATIONS AUDIO DISTRIBUTION SYSTEMS BROADCAST STUDIO EQUIPMENT GENERAL DIGITAL AUDIO PROCESSING
DESCRIPTION
D
FOUR GROUP DELAY OPTIONS FOR THE INTERPOLATION FILTER
INPUT-TO-OUTPUT SAMPLING RATIO READBACK (SOFTWARE MODE ONLY)
APPLICATIONS
BW = 20Hz to fs/2)
D
D
The SRC4194 is a four-channel, asynchronous sample rate converter (ASRC), designed for professional and broadcast audio applications. The SRC4194 combines a wide input-to-output sampling ratio with outstanding dynamic range and ultra low distortion. The input and output serial ports support the most common audio data formats, as well as a time division multiplexed (TDM) format. This allows the SRC4194 to interface to a wide range of audio data converters, digital audio receivers and transmitters, and digital signal processors. The SRC4194 may be operated in Hardware mode as a standalone pin-programmed device, with dedicated control pins for serial port mode, audio data format, soft mute, bypass, and digital filtering functions. Alternatively, the SRC4194 may be operated in Software mode, where a four-wire serial peripheral interface (SPI) port provides access to internal control and status registers. The SRC4194 operates from either a +1.8V core supply or a +3.3V core supply. When operating from +3.3V, the +1.8V required by the core logic is derived from an internal voltage regulator. The SRC4194 also requires a digital I/O supply, which operates from +1.65V to +3.6V. The SRC4194 is available in a TQFP-64 package.
U.S. Patent No. 7,262,716. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2004−2007, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS(1) Core Supply Voltage VDD18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +2.0V VDD33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +4.0V Digital I/O Supply Voltage, VIO . . . . . . . . . . . . . . . . −0.3V to +4.0V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +4.0V Operating Case Temperature Range, TC . . . . . . . . −40°C to +85°C Storage Temperature Range, TSTG . . . . . . . . . . . −65°C to +150°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
ELECTRICAL CHARACTERISTICS All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted. SRC4194 PARAMETER
CONDITIONS
DYNAMIC PERFORMANCE Resolution Input Sampling Frequency, fsIN Output Sampling Frequency, fsOUT INPUT/OUTPUT SAMPLING RATIO Upsampling Downsampling DYNAMIC RANGE(1)
MIN
UNITS
212 212
Bits kHz kHz
1:16 16:1 BW = 20Hz to fsOUT/2, −60dBFS Input fIN = 1kHz, A-Weighted 143 143 143 141 144 144 144 144 143 141
dB dB dB dB dB dB dB dB dB dB
−140 −140 −140 −137 −140 −140 −141 −141 −140 −137 0 0
dB dB dB dB dB dB dB dB dB dB dB degrees
BW = 20Hz to fsOUT/2, 0dBFS Input fIN = 1kHz, Unweighted
44.1kHz:48kHz 48kHz:44.1kHz 48kHz:96kHz 44.1kHz:192kHz 96kHz:48kHz 192kHz:12kHz 192kHz:32kHz 192kHz:48kHz 32kHz:48kHz 12kHz:192kHz Interchannel Gain Mismatch Interchannel Phase Deviation (1) Dynamic performance is measured with an Audio Precision System Two Cascade or Cascade Plus test system. (2) f sMIN = min (fsIN, fsOUT). (3) f sMAX = max (fsIN, fsOUT). (4) Power-supply current for the power-down modes is measured without loading. (5) Dynamic power-supply current measurements are performed with 2mA active loads on the excercized outputs.
2
MAX
24 4 4
44.1kHz:48kHz 48kHz:44.1kHz 48kHz:96kHz 44.1kHz:192kHz 96kHz:48kHz 192kHz:12kHz 192kHz:32kHz 192kHz:48kHz 32kHz:48kHz 12kHz:192kHz TOTAL HARMONIC DISTORTION + NOISE(1)
TYP
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ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted. SRC4194 PARAMETER
CONDITIONS
DIGITAL ATTENUATION Minimum Maximum Step Size Mute Attenuation
DIGITAL DE-EMPHASIS De-Emphasis Error for fs = 32kHz, 44.1kHz, or 48kHz VIH VIL IIH IIL VOH VOL CIN
UNITS dB dB dB dB
0.4535 × fsIN ±0.007 0.5465 × fsIN
Hz dB Hz Hz dB seconds seconds seconds seconds seconds seconds seconds seconds
0.4535× fsOUT ±0.008 0.5465 × fsOUT
Hz dB Hz Hz dB
102.53125/fsIN 102/fsIN 70.53125/fsIN 70/fsIN 54.53125/fsIN 54/fsIN 46.53125/fsIN 46/fsIN
Decimation Filter Enabled Direct Downsampling Enabled
36.46875/fsOUT 0
seconds seconds
De-Emphasis Enabled
0.001
dB
0.7 × VIO 0 0.5 0.5 IO = −4mA IO = +4mA
0.8 × VIO 0
VIO 0.3 × VIO 10 10 VIO 0.2 × VIO
V V µA µA V V pF
50 1/(128 × fsMIN)
MHz ns ns ns
3
128 × fsMIN 20 0.4 × tRCKIP 0.4 × tRCKIP
tRCKIP tRCKIH tRCKIL tRSTL Software Mode Only tLRIS tSIH tSIL tLDIS tLDIH
0.4535 × fsIN 0.5465 × fsIN −144
0.4535× fsOUT 0.5465× fsOUT −143
SWITCHING CHARACTERISTICS Reference Clock Timing RCKI Frequency(2)(3)
(1) (2) (3) (4) (5)
MAX
0 −127.5 0.5 −144
24-Bit Word Length
DIGITAL DECIMATION FILTER CHARACTERISTICS Passband Passband Ripple Transition Band Stop Band Stop Band Attenuation Group Delay Decimation Filter Direct Downsampling
RCKI Period RCKI Pulsewidth High RCKI Pulsewidth Low Reset Timing RST Pulsewidth Low Delay Following RST Rising Edge Input Serial Port Timing LRCKI to BCKI Setup Time BCKI Pulsewidth High BCKI Pulsewidth Low SDIN Data Setup Time SDIN Data Hold Time
TYP
Software Mode Only
DIGITAL INTERPOLATION FILTER CHARACTERISTICS Passband Passband Ripple Transition Band Stop Band Stop Band Attenuation Group Delay (64 sample buffer) Decimation Filter Enabled Group Delay (64 sample buffer) Direct Downsampling Enabled Group Delay (32 sample buffer) Decimation Filter Enabled Group Delay (32 sample buffer) Direct Downsampling Enabled Group Delay (16 sample buffer) Decimation Filter Enabled Group Delay (16 sample buffer) Direct Downsampling Enabled Group Delay (8 sample buffer) Decimation Filter Enabled Group Delay (8 sample buffer) Direct Downsampling Enabled
DIGITAL I/O CHARACTERISTICS High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current High-Level Output Voltage Low-Level Output Voltage Input Capacitance
MIN
500 500
ns µs
10 10 10 10 10
ns ns ns ns ns
Dynamic performance is measured with an Audio Precision System Two Cascade or Cascade Plus test system. fsMIN = min (fsIN, fsOUT). fsMAX = max (fsIN, fsOUT). Power-supply current for the power-down modes is measured without loading. Dynamic power-supply current measurements are performed with 2mA active loads on the excercized outputs.
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ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted. SRC4194 PARAMETER
CONDITIONS
SWITCHING CHARACTERISTICS (continued) Output Serial Port Timing SDOUT Data Delay Time tDOPD SDOUT Data Hold Time tDOH BCKO Pulsewidth High tSOH BCKO Pulsewidth Low tSOL TDM Mode Timing LRCKO Setup Time tLROS LRCKO Hold Time tLROH TDMI Data Setup Time tTDMS TDMI Data Hold Time tTDMH SPI Timing CCLK Frequency CDATA Setup Time tCDS CDATA Hold Time tCDH CS Falling to CCLK Rising tCSCR CCLK Falling to CS Rising tCFCS CCLK Falling to CDOUT Data Valid tCFDO CS Rising to CDOUT High Impedance tCSZ POWER SUPPLIES(4, 5) Operating Voltage VDD18 VDD33 VIO Supply Current IDD, Hard Power-Down IDD, Soft Power-Down IDD, Dynamic IIO, Hard Power-Down IIO, Soft Power-Down IIO, Dynamic Total Power Dissipation PD, Hard Power-Down PD, Soft Power-Down PD, Dynamic Supply Current IDD, Hard Power-Down IDD, Soft Power-Down IDD, Dynamic IIO, Hard Power-Down IIO, Soft Power-Down IIO, Dynamic Total Power Dissipation PD, Hard Power-Down PD, Soft Power-Down PD, Dynamic (1) (2) (3) (4) (5)
4
MIN
TYP
MAX
UNITS
10 2 10 5
ns ns ns ns
10 10 10 10
ns ns ns ns 25
5 5
MHz ns ns ns ns ns ns
+2.0 +3.6 +3.6
V V V
100
µA µA mA µA µA mA
12 8 15 12
REGEN = 0 REGEN = 1
+1.65 +3.0 +1.65
VDD18 = +1.8V, VIO = +1.8V, REGEN = 0 RST = 0, No Clocks PDN Bit = 0, No Clocks fsIN = 96kHz, fsOUT = 192kHz RST = 0, No Clocks PDN Bit = 0, No Clocks fsIN = 96kHz, fsOUT = 192kHz VDD18 = +1.8V, VIO = +1.8V, REGEN = 0 RST = 0, No Clocks PDN Bit = 0, No Clocks fsIN = fsOUT = 192kHz VDD33 = +3.3V, VIO = +3.3V, REGEN = 1 RST = 0, No Clocks PDN Bit = 0, No Clocks fsIN = 96kHz, fsOUT = 192kHz RST = 0, No Clocks PDN Bit = 0, No Clocks fsIN = 96kHz, fsOUT = 192kHz VDD33 = +3.3V, VIO = +3.3V, REGEN = 1 RST = 0, No Clocks PDN Bit = 0, No Clocks fsIN = fsOUT = 192kHz
Dynamic performance is measured with an Audio Precision System Two Cascade or Cascade Plus test system. fsMIN = min (fsIN, fsOUT). fsMAX = max (fsIN, fsOUT). Power-supply current for the power-down modes is measured without loading. Dynamic power-supply current measurements are performed with 2mA active loads on the excercized outputs.
+1.8 +3.3 +3.3
100 80 100 100 6 1
mW µW mW
100
µA mA mA µA µA mA
360 155
6 90 100 100 6 1 21 320
mW mW mW
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PIN CONFIGURATION
BCKOA
LRCKOA
TDMIA
BCKIA
LRCKIA
SDINA
DGND
VIO
SDINB
LRCKIB
BCKIB
TDMIB
LRCKOB
BCKOB
SDOUTB
TQFP
SDOUTA
Top View
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
IFMTA0
1
48 IFMTB0
IFMTA1
2
47 IFMTB1
IFMTA2
3
46 IFMTB2
OFMTA0
4
45 OFMTB0
OFMTA1
5
44 OFMTB1
OWLA0
6
43 OWLB0
OWLA1
7
42 OWLB1
BYPA
8
LGRPA0
41 BYPB
SRC4194
9
40 LGRPB0
LGRPA1 10
39 LGRPB1
DDNA 11
38 DDNB
DEMA0 12
37 DEMB0
DEMA1 13
36 DEMB1 (CDOUT)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
H/S
DGND
VDD33
VDD33
REGEN
VDD18
VDD18
RCKIB
MUTEB
RDYB
RATIOB
33 MODEB2 (CDIN)
RST
MODEA2 16
RCKIA
34 MODEB1 (CCLK)
MUTEA
MODEA1 15
RDYA
35 MODEB0 (CS)
RATIOA
MODEA0 14
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PIN DESCRIPTIONS PIN #
NAME
I/O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24, 25 26 27, 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
IFMTA0 IFMTA1 IFMTA2 OFMTA0 OFMTA1 OWLA0 OWLA1 BYPA LGRPA0 LGRPA1 DDNA DEMA0 DEMA1 MODEA0 MODEA1 MODEA2 RATIOA RDYA MUTEA RCKIA RST H/S DGND VDD33 REGEN VDD18 RCKIB MUTEB RDYB RATIOB MODEB2 or CDIN MODEB1 or CCLK MODEB0 or CS DEMB1 or CDOUT DEMB0 DDNB LGRPB1 LGRPB0 BYPB OWLB1 OWLB0 OFMTB1 OFMTB0 IFMTB2 IFMTB1 IFMTB0 SDOUTB BCKOB LRCKOB TDMIB BCKIB LRCKIB SDINB VIO DGND SDINA LRCKIA BCKIA TDMIA LRCKOA BCKOA SDOUTA
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Input Input Input Input Ground Power Input Power Input Input Output Output Input Input Input I/O Input Input Input Input Input Input Input Input Input Input Input Input Output I/O I/O Input I/O I/O Input Power Ground Input I/O I/O Input I/O I/O Output
(1) Disabled in Software control mode. (2) Disabled in Hardware control mode.
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DESCRIPTION SRC A Audio Input Data Format(1) SRC A Audio Input Data Format(1) SRC A Audio Input Data Format(1) SRC A Audio Output Data Format(1) SRC A Audio Output Data Format(1) SRC A Audio Output Data Word Length(1) SRC A Audio Output Data Word Length(1) SRC A Bypass Mode (Active High) SRC A Low Group Delay Mode(1) SRC A Low Group Delay Mode(1) SRC A Direct Downsampling Mode (Active High)(1) SRC A Digital De-Emphasis Filter Mode(1) SRC A Digital De-Emphasis Filter Mode(1) SRC A Serial Port Mode(1) SRC A Serial Port Mode(1) SRC A Serial Port Mode(1) SRC A Ratio Flag SRC A Ready Flag (Active Low) SRC A Output Soft Mute SRC A Reference Clock Reset and Power-Down (Active Low) Control Mode (0 = Software, 1 = Hardware) Digital Ground Core Supply, +3.3V. Required when REGEN is high. When REGEN is low, VDD33 must be left unconnected. Voltage Regulator Enable (Active High) Core Supply, +1.8V. Required when REGEN is low. When REGEN is high, VDD18 must be left unconnected. SRC B Reference Clock SRC B Output Soft Mute SRC B Ready Flag (Active Low) SRC B Ratio Flag SRC B Serial Port Mode(1) or SPI Port Serial Data Input(2) SRC B Serial Port Mode(1) or SPI Port Data Clock(2) SRC B Serial Port Mode(1) or SPI Port Chip Select (Active Low)(2) SRC B Digital De-Emphasis Filter Mode(1) or SPI Port Serial Data Output(2) SRC B Digital De-Emphasis Filter Mode(1) SRC B Direct Downsampling Mode (Active High)(1) SRC B Low Group Delay Mode(1) SRC B Low Group Delay Mode(1) SRC B Bypass Mode (Active High) SRC B Audio Output Data Word Length(1) SRC B Audio Output Data Word Length(1) SRC B Audio Output Data Format(1) SRC B Audio Output Data Format(1) SRC B Audio Input Data Format(1) SRC B Audio Input Data Format(1) SRC B Audio Input Data Format(1) SRC B Audio Output Data SRC B Audio Output Bit Clock SRC B Audio Output Left/Right or Word Clock SRC B TDM Input Data (TDM Format Only) SRC B Audio Input Bit Clock SRC B Audio Input Left/Right or Word Clock SRC B Audio Input Data Digital I/O Supply, +1.65V to +3.6V Digital Ground SRC A Audio Input Data SRC A Audio Input Left/Right or Word Clock SRC A Audio Input Bit Clock SRC A TDM Input Data (TDM Format Only) SRC A Audio Output Left/Right or Word Clock SRC A Audio Output Bit Clock SRC A Audio Output Data
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TYPICAL CHARACTERISTICS
AMPLITUDE vs FREQUENCY 0 −10 fsIN:fsOUT = 32kHz:32kHz −20 (asynchronous) −30 −40 fIN = 1kHz with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
AMPLITUDE vs FREQUENCY
Amplitude (dBFS)
Amplitude (dBFS)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
10k 16k
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS)
10k
22k
1k
10k 16k
AMPLITUDE vs FREQUENCY −60 −70 fsIN:fsOUT = 32kHz:44.1kHz −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
22k
10k
24k
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS)
100
Frequency (Hz)
Frequency (Hz)
AMPLITUDE vs FREQUENCY 0 −10 fsIN:fsOUT = 32kHz:48kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
fsIN:fsOUT = 32kHz:32kHz (asynchronous) fIN = 1kHz with −60dBFS Amplitude
20
Frequency (Hz)
AMPLITUDE vs FREQUENCY 0 −10 fsIN:fsOUT = 32kHz:44.1kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
−60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
10k
24k
AMPLITUDE vs FREQUENCY −60 −70 fsIN:fsOUT = 32kHz:48kHz −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k Frequency (Hz)
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TYPICAL CHARACTERISTICS (continued)
FFT PLOT 0 −10 fsIN:fsOUT = 44.1kHz:32kHz −20 f = 1kHz with 0dBFS Amplitude −30 IN −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Amplitude (dBFS)
Amplitude (dBFS)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
10k 16k
FFT PLOT −60 −70 fsIN:fsOUT = 44.1kHz:32kHz −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Frequency (Hz)
FFT PLOT
fsIN:fsOUT = 44.1kHz:44.1kHz (asynchronous) fIN = 1kHz with 0dBFS Amplitude
20
100
Amplitude (dBFS)
Amplitude (dBFS)
FFT PLOT 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
1k
10k
22k
8
fsIN:fsOUT = 44.1kHz:44.1kHz (asynchronous) fIN = 1kHz with −60dBFS Amplitude
100
1k
10k
22k
10k
24k
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS)
Frequency (Hz)
−60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
20
Frequency (Hz)
FFT PLOT 0 −10 fsIN:fsOUT = 44.1kHz:48kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k 16k
Frequency (Hz)
10k
24k
FFT PLOT −60 −70 fsIN:fsOUT = 44.1kHz:48kHz −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k Frequency (Hz)
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TYPICAL CHARACTERISTICS (continued)
FFT PLOT 0 −10 fsIN:fsOUT = 44.1kHz:88.2kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Amplitude (dBFS)
Amplitude (dBFS)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
10k
44k
FFT PLOT −60 f :f = 44.1kHz:88.2kHz −70 sIN sOUT −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
FFT PLOT 0 −10 fsIN:fsOUT = 44.1kHz:96kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
48k
FFT PLOT −60 −70 fsIN:fsOUT = 44.1kHz:96kHz −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS) 100
1k Frequency (Hz)
10k
48k
FFT PLOT
fsIN:fsOUT = 44.1kHz:192kHz f IN = 1kHz with 0dBFS Amplitude
20
44k
Frequency (Hz)
FFT PLOT 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
10k
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS)
Frequency (Hz)
10k
96k
−60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
fsIN:fsOUT = 44.1kHz:192kHz f IN = 1kHz with −60dBFS Amplitude
20
100
1k
10k
96k
Frequency (Hz)
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TYPICAL CHARACTERISTICS (continued)
FFT PLOT 0 −10 fsIN:fsOUT = 48kHz:32kHz −20 f = 1kHz with 0dBFS Amplitude −30 IN −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Amplitude (dBFS)
Amplitude (dBFS)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
10k 16k
FFT PLOT −60 f :f = 48kHz:32kHz −70 sIN sOUT −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
FFT PLOT 0 f :f = 48kHz:44.1kHz −10 sIN sOUT −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
22k
FFT PLOT −60 fsIN:fsOUT = 48kHz:44.1kHz −70 f = 1kHz −80 IN with −60dBFS Amplitude −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Frequency (Hz)
100
Amplitude (dBFS)
Amplitude (dBFS) 1k
Frequency (Hz)
10
22k
10k
24k
FFT PLOT
fsIN:fsOUT = 48kHz:48kHz (asynchronous) fIN = 1kHz with 0dBFS Amplitude
20
10k
Frequency (Hz)
FFT PLOT 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
10k 16k
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS)
Frequency (Hz)
10k
24k
−60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
fsIN:fsOUT = 48kHz:48kHz (asynchronous) fIN = 1kHz with −60dBFS Amplitude
20
100
1k Frequency (Hz)
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TYPICAL CHARACTERISTICS (continued)
FFT PLOT 0 −10 fsIN:fsOUT = 48kHz:96kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Amplitude (dBFS)
Amplitude (dBFS)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
10k
48k
FFT PLOT −60 f :f = 48kHz:96kHz −70 sIN sOUT −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Frequency (Hz)
f sIN:fsOUT = 48kHz:192kHz f IN = 1kHz with 0dBFS Amplitude
20
100
1k
10k
96k
Frequency (Hz)
f sIN :fsOUT = 48kHz:192kHz f IN = 1kHz with −60dBFS Amplitude
100
1k
10k
96k
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS)
−60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20
Frequency (Hz)
FFT PLOT 0 −10 fsIN:fsOUT = 96kHz:44.1kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
48k
FFT PLOT
Amplitude (dBFS)
Amplitude (dBFS)
FFT PLOT 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
10k
Frequency (Hz)
10k
22k
FFT PLOT −60 f :f = 96kHz:44.1kHz −70 sIN sOUT f = 1kHz −80 IN with −60dBFS Amplitude −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
22k
Frequency (Hz)
11
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TYPICAL CHARACTERISTICS (continued)
FFT PLOT 0 −10 fsIN:fsOUT = 96kHz:48kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Amplitude (dBFS)
Amplitude (dBFS)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
10k
24k
FFT PLOT −60 f :f = 96kHz:48kHz −70 sIN sOUT −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Frequency (Hz)
fsIN:fsOUT = 96kHz:96kHz (asynchronous) fIN = 1kHz with 0dBFS Amplitude
20
100
1k
10k
−60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
48k
fsIN:fsOUT = 96kHz:96kHz (asynchronous) fIN = 1kHz with −60dBFS Amplitude
20
100
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS) 100
1k Frequency (Hz)
12
10k
48k
FFT PLOT
f sIN:fsOUT = 96kHz:192kHz f IN = 1kHz with 0dBFS Amplitude
20
1k Frequency (Hz)
FFT PLOT 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
24k
FFT PLOT
Amplitude (dBFS)
Amplitude (dBFS)
FFT PLOT 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
10k
Frequency (Hz)
10k
96k
−60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
f sIN :fsOUT = 96kHz:192kHz f IN = 1kHz with −60dBFS Amplitude
20
100
1k Frequency (Hz)
10k
96k
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TYPICAL CHARACTERISTICS (continued)
FFT PLOT 0 −10 fsIN:fsOUT = 192kHz:44.1kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Amplitude (dBFS)
Amplitude (dBFS)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
10k
22k
FFT PLOT 0 −10 fsIN:fsOUT = 192kHz:48kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
24k
Frequency (Hz)
22k
FFT PLOT −60 −70 fsIN:fsOUT = 192kHz:48kHz −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
24k
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS)
Frequency (Hz)
FFT PLOT 0 −10 fsIN:fsOUT = 192kHz:96kHz −20 f = 1kHz −30 IN −40 with 0dBFS Amplitude −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS)
Frequency (Hz)
FFT PLOT −60 fsIN:fsOUT = 192kHz:44.1kHz −70 f = 1kHz −80 IN with −60dBFS Amplitude −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
48k
FFT PLOT −60 −70 fsIN:fsOUT = 192kHz:96kHz −80 fIN = 1kHz −90 with −60dBFS Amplitude −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
48k
Frequency (Hz)
13
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TYPICAL CHARACTERISTICS (continued)
FFT PLOT 0 −10 fsIN:fsOUT = 44.1kHz:48kHz −20 f = 20kHz with 0dBFS Amplitude −30 IN −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Amplitude (dBFS)
Amplitude (dBFS)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
10k
24k
FFT PLOT 0 −10 fsIN:fsOUT = 48kHz:44.1kHz −20 f = 20kHz with 0dBFS Amplitude −30 IN −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
FFT PLOT 0 −10 fsIN:fsOUT = 48kHz:48kHz (asynchronous) −20 f = 20kHz with 0dBFS Amplitude −30 IN −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
24k
FFT PLOT 0 −10 fsIN:fsOUT = 48kHz:96kHz −20 f = 20kHz with 0dBFS Amplitude −30 IN −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
Frequency (Hz)
14
22k
10k
48k
Frequency (Hz)
FFT PLOT
Amplitude (dBFS)
Amplitude (dBFS)
Frequency (Hz)
FFT PLOT 0 −10 fsIN:fsOUT = 96kHz:48kHz −20 f = 20kHz with 0dBFS Amplitude −30 IN −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 20 100 1k
10k
Frequency (Hz)
Amplitude (dBFS)
Amplitude (dBFS)
Frequency (Hz)
10k
24k
0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200
fsIN:f sOUT = 192kHz:192kHz (asynchronous) fIN = 80kHz with 0dBFS Amplitude
20
100
1k Frequency (Hz)
10k
96k
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TYPICAL CHARACTERISTICS (continued)
THD+N vs INPUT AMPLITUDE −120 −122 f sIN:f sOUT = 44.1kHz:48kHz −124 −126 f IN = 1kHz −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 −140 −120 −100 −80 −60 −40
THD+N (dB)
THD+N (dB)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
−20
0
THD+N vs INPUT AMPLITUDE −120 −122 f sIN:f sOUT = 48kHz:48kHz (asynchronous) −124 f = 1kHz −126 IN −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 −140 −120 −100 −80 −60 −40
−20
0
Input Amplitude (dBFS)
0
THD+N vs INPUT AMPLITUDE −120 −122 f sIN:f sOUT = 48kHz:96kHz −124 f = 1kHz −126 IN −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 −140 −120 −100 −80 −60 −40
−20
0
−20
0
Input Amplitude (dBFS)
THD+N (dB)
THD+N (dB)
Input Amplitude (dBFS)
THD+N vs INPUT AMPLITUDE −120 −122 f sIN:f sOUT = 96kHz:48kHz −124 f = 1kHz −126 IN −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 −140 −120 −100 −80 −60 −40
−20
Input Amplitude (dBFS)
THD+N (dB)
THD+N (dB)
Input Amplitude (dBFS)
THD+N vs INPUT AMPLITUDE −120 −122 f sIN:f sOUT = 48kHz:44.1kHz −124 f = 1kHz −126 IN −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 −140 −120 −100 −80 −60 −40
−20
0
THD+N vs INPUT AMPLITUDE −120 −122 f sIN:f sOUT = 96kHz:96kHz (asynchronous) −124 f = 1kHz −126 IN −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 −140 −120 −100 −80 −60 −40 Input Amplitude (dBFS)
15
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TYPICAL CHARACTERISTICS (continued)
THD+N vs INPUT AMPLITUDE −120 −122 fsIN:fsOUT = 192kHz:192kHz (asynchronous) −124 f = 1kHz −126 IN −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 −140 −120 −100 −80 −60 −40
THD+N (dB)
THD+N (dB)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
−20
0
THD+N vs INPUT FREQUENCY −120 −122 fsIN:fsOUT = 48kHz:44.1kHz −124 Input Amplitude = 0dBFS −126 −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 20 100 1k
10k
20k
Input Frequency (Hz)
16
20k
THD+N vs INPUT FREQUENCY −120 −122 fsIN:fsOUT = 48kHz:48kHz (asynchronous) −124 Input Amplitude = 0dBFS −126 −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 20 100 1k
10k
20k
10k
20k
Input Frequency (Hz)
THD+N (dB)
THD+N (dB)
Input Frequency (Hz)
THD+N vs INPUT FREQUENCY −120 −122 fsIN:fsOUT = 48kHz:96kHz −124 Input Amplitude = 0dBFS −126 −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 20 100 1k
10k
Input Frequency (Hz)
THD+N (dB)
THD+N (dB)
Input Amplitude (dBFS)
THD+N vs INPUT FREQUENCY −120 −122 fsIN:fsOUT = 44.1kHz:48kHz −124 Input Amplitude = 0dBFS −126 −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 20 100 1k
10k
20k
THD+N vs INPUT FREQUENCY −120 −122 fsIN:fsOUT = 96kHz:48kHz −124 Input Amplitude = 0dBFS −126 −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 20 100 1k Input Frequency (Hz)
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TYPICAL CHARACTERISTICS (continued)
THD+N vs INPUT FREQUENCY −120 −122 fsIN:fsOUT = 96kHz:96kHz (asynchronous) −124 Input Amplitude = 0dBFS −126 −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 20 100 1k 10k
THD+N (dB)
THD+N (dB)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
40k
LINEARITY 0 −10 fsIN:fsOUT = 32kHz:32kHz (asynchronous) −20 fIN = 200Hz −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −150 −130 −110 −90 −70 −50
−30
−10 0
Input Amplitude (dBFS)
LINEARITY 0 −10 fsIN:fsOUT = 48kHz:48kHz (asynchronous) −20 fIN = 200Hz −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −150 −130 −110 −90 −70 −50
−30
−10 0
LINEARITY 0 −10 fsIN:fsOUT = 192kHz:192kHz (asynchronous) −20 fIN = 200Hz −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −150 −130 −110 −90 −70 −50 −30
−10 0
Input Amplitude (dBFS)
Output Amplitude (dBFS)
Output Amplitude (dBFS)
Input Amplitude (dBFS)
LINEARITY 0 −10 fsIN:fsOUT = 96kHz:96kHz (asynchronous) −20 fIN = 200Hz −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −150 −130 −110 −90 −70 −50
80k
Input Frequency (Hz)
Output Amplitude (dBFS)
Output Amplitude (dBFS)
Input Frequency (Hz)
THD+N vs INPUT FREQUENCY −120 −122 fsIN:fsOUT = 192kHz:192kHz (asynchronous) −124 Input Amplitude = 0dBFS −126 −128 BW = 10Hz to fsOUT/2 −130 −132 −134 −136 −138 −140 −142 −144 −146 −148 −150 −152 −154 −156 −158 −160 20 100 1k 10k
−30
−10 0
Input Amplitude (dBFS)
17
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TYPICAL CHARACTERISTICS (continued)
FREQUENCY RESPONSE 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 fsIN:fsOUT = 192kHz:32kHz −140 Input Amplitude = 0dBFS −150 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
Output Amplitude (dBFS)
Output Amplitude (dBFS)
All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
FREQUENCY RESPONSE 0 −10 fsIN:fsOUT = 192kHz:48kHz −20 Input Amplitude = 0dBFS −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 0 5 10 15 20 25 30 35
FREQUENCY RESPONSE 0 −10 f sIN:f sOUT = 192kHz:96kHz −20 Input Amplitude = 0dBFS −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 0 5 10 15 20 25 30 35 40 45
PASS BAND RIPPLE fsIN:fsOUT = 32kHz:32kHz (asynchronous) −0.005 −0.010 −0.015 −0.020 −0.025 −0.030 50
55
60
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Input Frequency (kHz)
PASS BAND RIPPLE
PASS BAND RIPPLE
0
0
fsIN:fsOUT = 96kHz:96kHz (asynchronous)
fsIN:fsOUT = 48kHz:48kHz (asynchronous) −0.005
Output Amplitude (dBFS)
Output Amplitude (dBFS)
45 50
0
Input Frequency (kHz)
−0.010 −0.015 −0.020 −0.025 −0.030
−0.005 −0.010 −0.015 −0.020 −0.025 −0.030
0
2
4
6
8
10
12
14
Input Frequency (kHz)
18
40
Input Frequency (kHz)
Output Amplitude (dBFS)
Output Amplitude (dBFS)
Input Frequency (kHz)
16
18
20
22
0
5
10
15
20
25
30
Input Frequency (kHz)
35
40 45
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TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VDD33 = +3.3V, VIO = +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
PASS BAND RIPPLE
Output Amplitude (dBFS)
0
fsIN:fsOUT = 192kHz:192kHz (asynchronous)
−0.005 −0.010 −0.015 −0.020 −0.025 −0.030 0
10
20
30
40
50
60
70
80
90
Input Frequency (kHz)
19
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PRODUCT OVERVIEW The SRC4194 is a four-channel, asynchronous sample rate converter (ASRC), implemented as two stereo sections, referred to as SRC A and SRC B. Operation at input and output sampling frequencies up to 212kHz is supported, with a continuous input/output sampling ratio range of 16:1 to 1:16. Excellent dynamic range and THD+N are achieved by employing high-performance, linear-phase digital filtering with better than 140dB of image rejection. The digital filters provide settings for lower latency processing, including low group delay options for the interpolation filter and a direct downsampling option for the decimation filter. Digital de-emphasis filtering is included, supporting 32kHz, 44.1kHz, and 48kHz sampling frequencies. The audio input and output ports support standard audio data formats, as well as a time division multiplexed (TDM) format. Word lengths of 24-, 20-, 18-, and 16-bits are supported. Input and output ports may operate in Slave mode, deriving their word and bit clocks from external input and output devices. Alternatively, one port may operate in Master mode while the other remains in Slave mode. In Master mode, the LRCK and BCK clocks are derived from the reference clock inputs, either RCKIA or RCKIB. The flexible configuration options for the input and output ports allow connections to a variety of audio data converters, digital audio interface devices, and digital signal processors. LRCKIA BCKIA SDINA
Input Serial Port
Digital De−Emphasis and Interpolation Filters
A bypass mode is included, which allows audio data to be passed directly from the input port to the output port, bypassing the ASRC function. The bypass option is useful for passing through compressed or encoded audio data, as well as non-audio data (that is, control or status information). A soft mute function is available for the SRC4194 in both Hardware and Software modes. Digital output attenuation is available only in Software mode. Both soft mute and digital attenuation functions provide artifact-free operation. The mute attenuation is typically −144dB, while the digital attenuation function is adjustable from 0dB to −127.5dB in 0.5dB steps. The SRC4194 includes a four-wire SPI port, which is used to access on-chip control and status registers in Software mode. The SPI port facilitates interfacing to microprocessors or digital signal processors that support synchronous serial peripherals. In Hardware mode, dedicated control pins are provided for the majority of the SRC4194 functions. These pins can be hard-wired or driven by logic or host control.
FUNCTIONAL BLOCK DIAGRAM Figure 1 shows a functional block diagram of the SRC4194. The SRC4194 is segmented into two stereo SRC sections, referred to as SRC A and SRC B. Each section can operate independently from the other. Each section has individual sets of configuration pins in Hardware mode, and separate banks of control and status registers in Software mode. Digital Decimation Filter
Re−Sampler
fsIN
Rate Estimator
Output Serial Port
LRCKOA BCKOA SDOUTA TDMIA
fsOUT RDYA RATIOA
RCKIA IFMTA0
LGRPA0
LGRPB0
IFMTA1
LGRPA1 DDNA
LGRPB1 DDNB
DEMA0
DEMB0
DEMA1
DEMB1 (CDOUT)
OWLA0
MODEA0 MODEA1
MODEB0 (CS) MODEB1 (CCLK)
OWLA1
MODEA2
MODEB2 (CDIN)
IFMTA2 OFMTA0 OFMTA1
Control SRC A
BYPA
LRCKIB BCKIB SDINB
MUTEA
Input Serial Port
SPI Port and Reset
MUTEB
Digital De−Emphasis and Interpolation Filters
Digital Decimation Filter
Re−Sampler
fsIN
Rate Estimator
fsOUT RDYB RATIOB
RCKIB
Figure 1. Functional Block Diagram 20
Control SRC B
Output Serial Port
IFMTB0 IFMTB1 IFMTB2 OFMTB0 OFMTB1 OWLB0 OWLB1 BYPB H/S RST LRCKOB BCKOB SDOUTB TDMIB VIO DGND VDD18 (2) VDD33 (2) DGND REGEN
"#$%# www.ti.com SBFS025B − JUNE 2004 − REVISED SEPTEMBER 2007
Operation for SRC A and SRC B is identical. Audio data is received at the input serial port, clocked by either the audio source device in Slave mode, or by the SRC4194 in Master mode. The output port data is clocked by either the audio output device in Slave mode, or by the SRC4194 in Master mode. The input data is passed through interpolation filters that upsample the data, which is then passed on to the re-sampler. The rate estimator compares the input and output sampling frequencies by comparing LRCKI, LRCKO, and a reference clock. The results of the rate estimation are utilized to configure the re-sampler coefficients and data pointers. The output of the re-sampler is passed on to either the decimation filter or direct downsampler function. The decimation filter performs downsampling and anti-alias filtering functions, and is required when the output sampling frequency is equal to or lower than the input sampling frequency. The direct downsampler function does not provide any filtering, and may be used in cases when the output sampling frequency is greater than the input sampling frequency. The advantage of the direct downsampling function is a significant reduction in the group delay associated with the decimation function, allowing lower latency processing.
REFERENCE CLOCK The SRC4194 includes two reference clock inputs, one each for SRC A and SRC B. The reference clocks are applied at the RCKIA (pin 20) and RCKIB (pin 29) inputs, respectively. The reference clock is required for the rate estimator function, as well as for the input or output serial ports when configured in Master mode. Figure 2 illustrates the reference clock connections and requirements for the SRC4194. When either the input or output port is configured in Master mode, the reference clock may operate at 128fs, 256fs, or 512fs, where fs is the desired sampling rate for the Master mode port. When both the input and output port are configured in Slave mode, the
reference clock does not have to be a multiple of the input or output sampling rates. The maximum reference clock input frequency is 50MHz for RCKIA and RCKIB.
SRC4194 RCKI1
RCKI2 29
20
From External Clock Source(s) 50MHz Max tRCKIP RCKI tRCKIH
tRCKIL
tRCKIP > 20ns min tRCKIH > 0.4 tRCKIP tRCKIL > 0.4 tRCKIP
Figure 2. Reference Clock Input Connections and Timing Requirements
RESET AND POWER-DOWN OPERATION The SRC4194 may be reset using the RST input (pin 21). There is no internal power on reset, so the user should force a reset sequence after power up in order to initialize the device. In order to force a reset, the reference clock inputs must be active, with external clock sources supplying a valid reference clock signal (refer to Figure 2). The user must assert RST low for a minimum of 500ns and then bring RST high again to force a reset. The reset function affects both SRC A and SRC B. Figure 3 shows the reset timing for the SRC4194. In Software mode, there is a 500ms delay after the RST rising edge due to internal logic requirements. The customer should wait a minimum 500ms after the RST rising edge before attempting to write to the SPI port of the SRC4194 in Software mode.
RCKIA RCKIB
RST tRSTL > 500ns
Figure 3. Reset Pulsewidth Requirement
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The SRC4194 also supports two power-down modes. The entire SRC4194 may be powered down by forcing and holding the RST input low. This is referred to as a Hard Power-Down, and the SRC4194 consumes the least amount of power in this mode. In Software mode, there is an additional Soft Power-Down available, utilizing the PDN bit in Control Register 1. Soft Power-Down is enabled when the PDN bit is set to 0. Since SRC A and SRC B have their own separate register banks, they may be set to Soft Power-Down mode individually. During Soft Power-Down, the SPI port and control registers remain active for write and read access. The internal voltage regulator also remains active if the REGEN pin is forced high and +3.3V is applied at the VDD33 pin. Soft Power-Down mode consumes more power than the Hard Power-Down mode. Refer to the Electrical Characteristics tables in this data sheet for supply current and power dissipation specifications for both modes. Finally, there is one very important item to remember when using Software mode. The default state of the PDN bit is 0, meaning that the SRC4194 will default to the Soft Power-Down state for both SRC A and SRC B after power up or reset. The user must set the PDN bit to 1 for both the SRC A and SRC B control register banks in order to enable normal operation for both SRC sections.
AUDIO SERIAL PORT MODES The SRC4194 supports seven serial port modes for the SRC A and SRC B sections, which are shown in Table 1. In Hardware mode, the audio port mode is selected using the MODEA0 (pin 14), MODEA1 (pin 15), and MODEA2 (pin 16) inputs for SRC A, while the MODEB0 (pin 35), MODEB1 (pin 34), and MODEB2 (pin 33) inputs are used for SRC B. In Software mode, the audio serial port modes are selected using the MODE[2:0] bits in Control Register 1 for the SRC A and SRC B register banks. The default setting for Software mode is both input and output ports set to Slave mode. In Slave mode, the port LRCK and BCK clocks are configured as inputs, and receive their clocks from an external audio device. In Master mode, the LRCK and BCK clocks are configured as outputs, being derived from
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the reference clock input for the corresponding SRC section, either RCKIA or RCKIB. Only one port can be set to Master mode at any given time, as indicated in Table 1.
Table 1. Setting the Serial Port Modes (x = A or B) MODEx2
MODEx1
MODEx0
SERIAL PORT MODE
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Both Input and Output Ports are Slave mode Output Port is Master Mode with RCKIx = 128fS Output Port is Master Mode with RCKIx = 512fS Output Port is Master Mode with RCKIx = 256fS Both Input and Output Ports are Slave mode Input Port is Master Mode with RCKIx = 128fS Input Port is Master Mode with RCKIx = 512fS Input Port is Master Mode with RCKIx = 256fS
INPUT PORT OPERATION The audio input port is a three-wire synchronous serial interface that may operate in either Slave or Master mode. The SDINA (pin 58) and SDINB (pin 55) are the serial audio data inputs for SRC A and SRC B, respectively. Audio data is input at these pins in one of three standard audio data formats: Philips I2S, Left-Justified, or Right-Justified. The audio data word length may be up to 24-bits for I2S and Left-Justified formats, while the Right-Justified format supports 16-, 18-, 20-, or 24-bit data. The audio data is always Binary Two’s Complement with the MSB first. Refer to Figure 4 for the input data formats and Figure 5 for the critical timing parameters, which are also listed in the Electrical Characteristics table. The bit clock is either an input or output at BCKIA (pin 60) and BCKIB (pin 53). In Slave mode, the bit clock is configured as an input pin, and may operate at rates from 32fs to 128fs,with a minimum of one clock cycle per data bit. In Master mode, bit clock operates at a fixed rate of 64fs. The left/right word clock, LRCKIA (pin 59) and LRCKIB (pin 54), may be configured as an input or output pin. In Slave mode, left/right clock is an input pin, while in Master mode the left/right clock is an output pin. In either case, the clock rate is equal to fs, the input sampling frequency. The LRCKI duty cycle is fixed to 50% for Master mode operation.
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Right Channel
Left Channel LRCKI
BCKI
SDIN
MSB
LSB
MSB
LSB
(a) Left−Justified Data Format
LRCKI
BCKI
SDIN
MSB
LSB
MSB
LSB
(b) Right−Justified Data Format
LRCKI
BCKI
SDIN
MSB
LSB
MSB
LSB
(c) I2S Data Format 1/fS
Figure 4. Input Data Formats input port data format for SRC A. IFMTB0 (pin 48), IFMTB1 (pin 47), and IFMTB2 (pin 46) are utilized to set the input port data format for SRC B.
LRCKI tLRIS
tSIH
Table 2. Input Port Data Format Selection (x = A or B)
BCKI tLDIS
tSIL
SDIN tLDIH
Figure 5. Input Port Timing Table 2 illustrates the data format selection for the input port. For Hardware mode, the IFMTA0 (pin 1), IFMTA1 (pin 2), and IFMTA2 (pin 3) inputs are utilized to set the
IFMTx2
IFMTx1
IFMTx0
INPUT PORT DATA FORMAT
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
24-Bit Left-Justified 24-Bit I2S Unused Unused 16-Bit Right-Justified 18-Bit Right-Justified 20-Bit Right-Justified 24-Bit Right-Justified
In Software mode, the IFMT[2:0] bits in Control Register 3 are used to select the data format for the SRC A and SRC B register banks. The default format is 24-bit Left-Justified.
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OUTPUT PORT OPERATION The audio output port is a four-wire synchronous serial interface that may operate in either Slave or Master mode. SDOUTA (pin 64) and SDOUTB (pin 49) are the serial audio data outputs for SRC A and SRC B, respectively. Audio data is output at these pins in one of four data formats: Philips I2S, Left-Justified, Right-Justified, or TDM. The audio data word length may be 16-, 18-, 20-, or 24-bits. For all word lengths, the data is triangular PDF dithered from the internal 28-bit data path. The data formats (with the exception of TDM mode) are shown in Figure 7, while critical timing parameters are shown in Figure 6 and listed in the Electrical Characteristics table. The TDM format and timing are shown in Figure 15 and Figure 16, respectively, while examples of standard TDM configurations are shown in Figure 17 and Figure 18.
data bit. The exception is the TDM mode, where the BCKO must operate at N × 64fs, where N is equal to the number of SRC sections cascaded on the TDM bus. In Master mode, the bit clock operates at a fixed rate of 64fs for all data formats except TDM, where BCKO operates at the reference clock frequency. Additional information regarding TDM mode operation is included in the Applications Information section of this data sheet.
LRCKO tSOH BCKO tSOL
tDOPD SDOUT
The bit clock is either input or output at BCKOA (pin 63) and BCKOB (pin 50). In Slave mode, the bit clock is configured as an input pin, and may operate at rates from 32fs to 128fs, with a minimum of one clock cycle for each
tDOH
Figure 6. Output Port Timing
Right Channel
Left Channel LRCKO
BCKO
SDOUT
MSB
LSB
MSB
LSB
(a) Left−Justified Data Format
LRCKO
BCKO
SDOUT
MSB
LSB
MSB
LSB
(b) Right−Justified Data Format
LRCKO
BCKO
SDOUT
MSB
LSB
MSB
(c) I2S Data Format 1/fS
Figure 7. Output Data Formats
24
LSB
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The left/right word clock, LRCKOA (pin 62) and LRCKOB (pin 51), may be configured as an input or output pin. In Slave mode, the left/right clock is an input pin, while in Master mode it is an output pin. In either case, the clock rate is equal to fs, the output sampling frequency. The clock duty cycle is fixed to 50% for I2S, Left-Justified, and Right-Justified formats in Master mode. The pulse width is fixed to 32-bit clock cycles for the TDM format in Master mode. Table 3 illustrates data format selection for the output port. In Hardware mode, the OFMTA0 (pin 4), OFMTA1 (pin 5), OWLA0 (pin 6), and OWLA1 (pin 7) inputs are utilized to set the output port data format and word length for SRC A. The OFMTB0 (pin 45), OFMTB1 (pin 44), OWLB0 (pin 43), and OWLB1 (pin 42) inputs are utilized to set the output port data format and word length for SRC B.
Table 3. Output Port Data Format/Word Length Selection (x = A or B) OFMTx1
OFMTx0
OUTPUT PORT DATA FORMAT
0 0 1 1
0 1 0 1
Left-Justified I2S TDM Right-Justified
OWLx1
OWLx0
OUTPUT PORT DATA WORD LENGTH
0 0 1 1
0 1 0 1
24 Bits 20 Bits 18 Bits 16 Bits
In Software mode, the OFMT[1:0] and OWL[1:0] bits in Control Register 3 are used to select the data format and word length for the SRC A and SRC B register banks. The default format is Left-Justified data with a default word length of 24-bits.
BYPASS MODE The SRC4194 includes a bypass function for both SRC A and SRC B, which routes the input port data directly to the output port, bypassing the sample rate conversion block. Bypass mode may be invoked by forcing BYPA (pin 8) or BYPB (pin 41) high in either Hardware or Software mode. In Software mode, the bypass function may also be accessed using the BYPASS bit in Control Register 1 for the SRC A and SRC B register banks. For normal SRC operation, the bypass pins and control bits should be set to 0. No dithering is applied to the output data in Bypass mode, and the digital attenuation, de-emphasis, and soft mute functions are also unavailable. Bypass mode is useful for passing through compressed or encoded audio data, as well as non-audio data (that is, control or status information).
INTERPOLATION FILTER GROUP DELAY OPTIONS The SRC4194 provides four group delay options for the digital interpolation filter, as shown in Table 4. These options allow the user to tailor the group delay for a given application by selecting the number of input samples buffered prior to the re-sampling function.
Table 4. Low Group Delay Configuration (x = A or B) LGRPx1
LGRPx0
BUFFER SIZE
0 0 1 1
0 1 0 1
64 Samples 32 Samples 16 Samples 8 Samples
In Hardware mode, the LGRPA0 (pin 9) and LGRPA1 (pin 10) inputs are used to select the group delay for SRC A, while LGRPB0 (pin 40) and LGRPB1 (pin 39) inputs are used for SRC B. In Software mode, the LGRP[1:0] bits in Control Register 2 are used for the SRC A and SRC B register banks. The 64 sample buffer option is selected by default in Software mode.
DIRECT DOWNSAMPLING OPTION The SRC4194 decimation function allows the selection of a direct downsampling option, as shown in Table 5. Unlike the decimation filter, the direct downsampler does not provide anti-alias filtering. This makes the direct downsampler suitable for applications where the output sample rate is higher than the input sample rate. The advantage of the direct downsampler is that there is no group delay associated with the decimation function.
Table 5. Decimation Function Configuration (x = A or B) DDNx
DECIMATION FUNCTION
0 1
Decimation Filter Enabled Direct Downsampler Enabled
In Hardware mode, the DDNA (pin 11) input is used to select the direct downsampler for SRC A, while the DDNB (pin 38) input is used for SRC B. In Software mode, the DDN bit in Control Register 2 is used to select the direct downsampler for the SRC A and SRC B register banks. The decimation filter is selected by default, with direct downsampling disabled.
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DIGITAL DE-EMPHASIS FILTER The SRC4194 includes digital de-emphasis filtering following the input serial ports. The de-emphasis filter processes audio data that has been pre-emphasized using the 50/15µs transfer function, commonly used in consumer and professional audio systems. Pre-emphasis is utilized to increase the amplitude of the higher frequency components within the audio band. The de-emphasis filter normalizes the frequency response over the audio band. The SRC4194 supports three sampling frequencies for the de-emphasis filter: 32kHz, 44.1kHz, and 48kHz. The de-emphasis filter can also be disabled. Table 6 shows the configuration table for the de-emphasis filter options.
Table 6. Digital De-Emphasis Filter Configuration (x = A or B) DEMx1
DEMx0
DE-EMPHASIS FILTER FUNCTION
0 0 1 1
0 1 0 1
Disabled 48kHz Input Sample Rate 44.1kHz Input Sample Rate 32kHz Input Sample Rate
In Hardware mode, the DEMA0 (pin 12) and DEMA1 (pin 13) inputs are used to select the de-emphasis filter for SRC A, while DEMB0 (pin 37) and DEMB1 (pin 36) inputs are used for SRC B. In Software mode, the DEM[1:0] bits in Control Register 2 are used to select the de-emphasis filter in both the SRC A and SRC B register banks. De-emphasis filtering is disabled by default in Software mode.
The TRACK bit in Control Register 1 is used to select Independent or Tracking attenuation modes. When TRACK = 0, the Left and Right channels are controlled independently. When TRACK = 1, the attenuation setting for the Left channel is also used for the Right channel, providing a tracking function. The digital attenuation mode is set to Independent by default.
READY OUTPUT The SRC4194 includes active low ready outputs for both SRC A and SRC B. The outputs are designated RDYA (pin 18) and RDYB (pin 31). The ready output is provided from the rate estimator block, with a low output state indicating that the input-to-output sampling frequency ratio has been determined and that the coefficients and address pointers for the re-sampling block have been updated. The ready signal may be used as a flag output for an external indicator or host.
RATIO OUTPUT The SRC4194 includes a sampling ratio flag output for both SRC A and SRC B. The outputs are designated RATIOA (pin 17) and RATIOB (pin 32). When the ratio output is low, it indicates that the output sampling frequency is lower than the input sampling frequency. When ratio output is high, it indicates that the output sampling frequency is higher than the input sampling frequency. The ratio output can be used as a flag output for either an external indicator or host.
SAMPLING RATIO READBACK (Software Mode Only)
SOFT MUTE FUNCTION The soft mute function of the SRC4194 may be invoked by forcing the MUTEA (pin 19) or MUTEB (pin 30) inputs high. In Software mode, the mute function may also be accessed using the MUTE bit in Control Register 1 for either the SRC A and SRC B register banks. The soft mute function slowly attenuates the output signal level down to an all zeros output. For normal output, the soft mute function should be disabled by forcing the control pin or bit low. The soft mute function is disabled by default in Software mode.
DIGITAL ATTENUATION (Software Mode Only) The SRC4194 includes independent digital attenuation for the Left and Right audio channels in Software mode. The attenuation ranges from 0dB (unity gain) to −127.5dB in 0.5dB steps. The attenuation settings are programmed using Control Register 4 and Control Register 5 for either the SRC A and SRC B register banks. The attenuation setting is programmed to 0dB (unity gain) by default. 26
In Software mode, Control Registers 6 and 7 in either the SRC A and SRC B register banks function as status registers, which contain the integer and fractional part of the input-to-output sampling ratio, or fsIN:fsOUT. Given that fsOUT or fsIN is known, the unknown sampling rate can be computed using the contents of Registers 6 and 7. This function may be useful for controlling end application display or control processes. Refer to the Control Register Definition section of this datasheet for additional information regarding Registers 6 and 7.
SERIAL PERIPHERAL INTERFACE (SPI) PORT (Software Mode Only) The SPI port is a four-wire synchronous serial interface used to access the on-chip control registers of the SRC4194. The interface is comprised of a serial data clock input, CCLK (pin 34); a serial data input, CDIN (pin 33); a serial data output, CDOUT (pin 36); and an active low chip-select input, CS (pin 35). The CDOUT pin is a tri-state output and is forced to a high impedance state when the CS input is forced high.
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As shown in Figure 8, a write or read operation starts by bringing the CS input low. Bytes 0, 1, and 2 are then written to write or read a single register. Byte 2 is not needed for reading registers, so the CDIN pin can be forced low after Byte 0 for a read operation. Bringing the CS input high after the third byte will write or read a single register address. However, if CS remains low after writing or reading the first control or status byte, the port will automatically increment the address by 1, allowing successive addresses to be written or read sequentially. The address is automatically incremented by 1 after each byte is written or read, as long as the CS input remains low. This is referred to as Auto-Increment operation, and is always enabled for the SPI port.
Figure 8 illustrates the protocol for register write and read operations via the SPI port. Figure 9 shows the critical timing parameters for the SPI port interface, which are listed in the Electrical Characteristics table. Byte 0 indicates the register bank, register address, and read/write status for the operation. The functions contained within this byte are clearly shown in Figure 8. It should be noted that either one or both of the SRC A and SRC B register banks may be written to in the same operation, but only one bank can be selected at any time for a read operation. Byte 1 is a don’t care byte. This byte is included in the protocol in order to maintain compatibility with current and future Texas Instruments’ digital audio interface products, including the DIT4096, DIT4192, and SRC4193. Bytes 0 and 1 are followed by register data bytes. CS
Keep CS = 0 to enable the auto−increment mode.
Set CS = 1 here to write/read one register location. Header Byte 0
CDIN
Register Data Byte 1
Byte 2
Byte 3
Byte N Register Data
Hi−Z
CDOUT
Hi−Z
Data for A[2:0]
Data for A[2:0] + 1
Data for A[2:0] + N
CCLK Byte Definition: MSB Byte 0:
RWB
LSB 0
0
SB
SA
Register Bank Select
A2
A1
A0
Register Address
Set to 0. Set to 0 for Write; set to 1 for Read.
Byte 1: Don’t Care Byte 2 through Byte N: Register Data
SB
SA
Write Access
Read Access
0 0 1 1
0 1 0 1
Disabled SRC A SRC B SRC A and B
Disabled SRC A SRC B SRC B
Figure 8. SPI Protocol for the SRC4194 tCFCS CSB tCSCR
tCDS
CCLK tCDH CDIN
CDOUT
Hi−Z
Hi−Z tCFDO
tCSZ
Figure 9. SPI Port Timing 27
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CONTROL REGISTER MAP (Software Mode Only) The control register map for the SRC4194 is shown in Table 7. There are two identical register banks, one for SRC A and one for SRC B, each conforming to the register map shown in Table 7. Register 0 is reserved for factory use and defaults to all zeros upon reset. The user should avoid writing to or reading this register, as unexpected operation may result if Register 0 is programmed to an arbitrary value. Register 1 through Register 5 contain control bits, which are programmed to configure specific internal functions. Register 1 through Register 5 are available for write or read access. Register 6 and Register 7 contain the integer and fractional parts of the fsIN:fsOUT sampling ratio and are read only status registers.
Table 7. Control Register Map for Either the SRC A or SRC B Register Banks
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REGISTER ADDRESS (HEX)
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
0 1 2 3 4 5 6 7
0 PDN 0 OWL1 AL7 AR7 SRI4 SRF7
0 TRACK 0 OWL0 AL6 AR6 SRI3 SRF6
0 0 0 OFMT1 AL5 AR5 SRI2 SRF5
0 MUTE DEM1 OFMT0 AL4 AR4 SRI1 SRF4
0 BYPASS DEM0 0 AL3 AR3 SRI0 SRF3
0 MODE2 DDN IFMT2 AL2 AR2 SRF10 SRF2
0 MODE1 LGRP1 IFMT1 AL1 AR1 SRF9 SRF1
0 MODE0 LGRP0 IFMT0 AL0 AR0 SRF8 SRF0
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CONTROL REGISTER DEFINITIONS (Software Mode Only) This section contains descriptions for each control and status register available in Software mode. Reset defaults are also shown for each register bit.
Register 1. System Control Register D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
PDN
TRACK
0
MUTE
BYPASS
MODE2
MODE1
MODE0
MODE[2:0]
Audio Serial Port Mode These bits are used to select the Slave or Master mode status of the input and output serial ports.
BYPASS
MODE2
MODE1
MODE0
AUDIO SERIAL PORT MODE
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Both Serial Ports are in Slave Mode (default) Output Serial Port is Master with RCKI = 128fs Output Serial Port is Master with RCKI = 512fs Output Serial Port is Master with RCKI = 256fs Both Serial Ports are in Slave Mode Input Serial Port is Master with RCKI = 128fs Input Serial Port is Master with RCKI = 512fs Input Serial Port is Master with RCKI = 256fs
Bypass Mode This bit is logically OR’d with the bypass input (BYPA or BYPB) for the corresponding SRC section.
MUTE
BYPASS
FUNCTION
0 1
Bypass Mode disabled with normal ASRC operation. (default) Bypass Mode enabled with data routed directly from the input port to the output port, bypassing the ARSC function.
Output Soft Mute This bit is logically OR’d with the MUTE input (MUTEA or MUTEB) for the corresponding SRC section.
TRACK
MUTE
OUTPUT MUTE FUNCTION
0 1
Soft mute disabled. (default) Soft mute enabled with output data attenuated to all 0s.
Digital Attenuation Tracking TRACK
ATTENUATION TRACKING
0
Tracking Off: Attenuation for the Left and Right channels is controlled independently by Control Register 4 and Control Register 5. (default) Tracking On: Left channel attenuation setting is used for both channels.
1
PDN
Power-Down Setting this bit to 0 will force the corresponding SRC section into Soft Power-Down mode. All other register settings are preserved and the SPI port remains active. Setting this bit to 1 will power up the corresponding SRC section using the current register settings. This bit defaults to 0 on power-up or reset. It must be programmed to 1 by the user in order to enable normal operation for the corresponding SRC section.
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Register 2. Digital Filter Control Register D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
0
0
0
DEM1
DEM0
DDN
LGRP1
LGRP0
LGRP0
Interpolation Filter Group Delay
LGRP1
These bits are used to select the number of input samples to be stored in the data buffer before the re-sampler starts to process the data. This has a direct impact on the group delay or latency of the interpolation filter.
DDN
LGRP1
LGRP0
GROUP DELAY
0 0 1 1
0 1 0 1
64 Samples (default) 32 Samples 16 Samples 8 Samples
Decimation Filtering/Direct Downsampling The DDN bit is used to enable or disable the direct downsampling function of the decimation block. DDN
DECIMATION FILTER OPERATION
0
Decimation filter enabled. (default) (Must be used when fsOUT is less than or equal to fsIN.)
1
Direct downsampling enabled without filtering. (May be enabled when fsOUT is greater than fsIN.)
DEM0
Digital De-Emphasis Filtering
DEM1
These bits are used to configure the digital de-emphasis filter function.
30
DEM1
DEM0
DE-EMPHASIS FILTER
0 0 1 1
0 1 0 1
Disabled (default) 48kHz Input Sampling Rate 44.1kHz Input Sampling Rate 32kHz Input Sampling Rate
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Register 3. Audio Data Format Register D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
OWL1
OWL0
OFMT1
OFMT0
0
IFMT2
IFMT1
IFMT0
IFMT[2:0]
Input Serial Port Data Format These bits are utilized to select the audio data format for the input serial port.
OFMT[1:0]
IFMT2
IFMT1
IFMT0
INPUT FORMAT
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
24-Bit, Left-Justified (default) 24-Bit, I2S Reserved Reserved Right-Justified, 16-Bit Data Right-Justified, 18-Bit Data Right-Justified, 20-Bit Data Right-Justified, 24-Bit Data
Output Port Data Format These bits are utilized to select the audio data format for the output serial port.
OWL[1:0]
OFMT1
OFMT0
OUTPUT FORMAT
0 0 1 1
0 1 0 1
Left-Justified (default) I2S TDM Right-Justified
Output Port Data Word Length OWL1
OWL0
OUTPUT WORD LENGTH
0 0 1 1
0 1 0 1
24-Bits (default) 20-Bits 18-Bits 16-Bits
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Register 4. Digital Output Attenuation Register—Left Channel D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
This register is utilized to program the digital output attenuation for the Left output channel of the corresponding SRC section. Register defaults to 00h, or 0dB (unity gain). Output Attenuation (dB) = −N × 0.5, where N = AL[7:0]DEC
Register 5. Digital Output Attenuation Register—Right Channel D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
This register is utilized to program the digital output attenuation for the Right output channel of the corresponding SRC section. When the TRACK bit in Control Register 1 is set to 1, the Left Channel attenuation setting will also be used to set the Right Channel attenuation. Register defaults to 00h, or 0dB (unity gain). Output Attenuation (dB) = −N × 0.5, where N = AR[7:0]DEC
Register 6. Sampling Ratio (read only) D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
SRI4
SRI3
SRI2
SRI1
SRI0
SRF10
SRF9
SRF8
Register 7. Sampling Ratio (read only) D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
SRF7
SRF6
SRF5
SRF4
SRF3
SRF2
SRF1
SRF0
The contents of Register 6 and Register 7 indicate the input-to-output sampling ratio, and can be used to determine either the input or output sampling rates when one of the two rates is known. Bits SRI[4:0] comprise the integer portion of the input-to-output sampling ratio. Bits SRF[10:0] comprise the fractional portion of the input-to-output sampling ratio. The contents of Register 6 and Register 7 are updated when Register 6 is read. Register 6 must always be read first in order to obtain the latest ratio data for both registers.
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Figure 12 illustrates the power-supply options for the SRC4194. When utilizing +3.3V for the core supply, the REGEN input (pin 26) must be driven high in order to enable the on-chip linear voltage regulator. The VDD33 pins are supplied with +3.3V and the VDD18 pins are left unconnected.
APPLICATIONS INFORMATION This section provides practical applications information for hardware and systems engineers who will be designing the SRC4194 into their end equipment.
TYPICAL CONNECTIONS
When utilizing +1.8V for the core supply, the REGEN input (pin 26) must be driven low in order to disable the on-chip linear voltage regulator. The VDD18 pins are supplied with +1.8V and the VDD33 pins are left unconnected.
Figure 10 and Figure 11 illustrate typical connection diagrams for Hardware and Software modes, respectively. In Hardware mode, dedicated pins are controlled using external logic circuitry, hardwiring pins high or low, or by using the general-purpose I/O pins of a microprocessor or DSP. In Software mode, the SRC4194 is controlled via the 4-wire SPI port and optional GPIO from either a microprocessor or DSP.
Recommended power-supply bypass capacitor values are shown in Figure 10 through Figure 12. Ceramic capacitors (X7R chip type) are recommended for the 0.1µF capacitors, while the 10µF capacitors may be tantalum or multi-layer X7R ceramic chip type, or through-hole or surface-mount aluminum electrolytic capacitors. SRC4194
Digital Audio I/O (DIR, DIT, DSP)
64 63 62 61 60 59 58 57 56
10µF
0.1µF
+
VIO Supply
Control Logic, µP, or Hardwired I/O
From Reference Clock Source From System or External Reset
Refer to Figure 12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
SDOUTA BCKOA LRCKOA TDMIA BCKIA LRCKIA SDINA
SDOUTB BCKOB LRCKOB TDMIB BCKIB LRCKIB SDINB
DGND VIO
IFMTB0 IFMTB1 IFMTB2 OFMTB0 OFMTB1 OWLB0 OWLB1 BYPB LGRPB0 LGRPB1 DDNB DEMB0 DEMB1 MODEB0 MODEB1 MODEB2 RATIOB RDYB MUTEB
IFMTA0 IFMTA1 IFMTA2 OFMTA0 OFMTA1 OWLA0 OWLA1 BYPA LGRPA0 LGRPA1 DDNA DEMA0 DEMA1 MODEA0 MODEA1 MODEA2 RATIOA RDYA MUTEA RCKIA
RCKIB VDD18 VDD18
49 50 51 52 53 54 55 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
Digital Audio I/O (DIR, DIT, DSP)
Control Logic, µP, or Hardwired I/O
From Reference Source Clock
Refer to Figure 12
RST H/S DGND VDD33 VDD33 REGEN
Figure 10. Typical Pin Connections for Hardware Mode Operation 33
"#$%# www.ti.com SBFS025B − JUNE 2004 − REVISED SEPTEMBER 2007
SRC4194 64 63 62 61 60 59 58
Digital Audio I/O (DIR, DIT, DSP)
57 56 10µF
+
0.1µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
VIO Supply
To/From Host Processor
20
From Reference Clock Source
21 22
From System or External Reset or Host Processor
23 24 25 26
Refer to Figure 12
SDOUTA BCKOA LRCKOA TDMIA BCKIA LRCKIA SDINA
SDOUTB BCKOB LRCKOB TDMIB BCKIB LRCKIB SDINB
DGND VIO
IFMTB0 IFMTB1 IFMTB2 OFMTB0 OFMTB1 OWLB0 OWLB1 BYPB LGRPB0 LGRPB1 DDNB DEMB0 CDOUT CS CCLK CDIN RATIOB RDYB MUTEB
IFMTA0 IFMTA1 IFMTA2 OFMTA0 OFMTA1 OWLA0 OWLA1 BYPA LGRPA0 LGRPA1 DDNA DEMA0 DEMA1 MODEA0 MODEA1 MODEA2 RATIOA RDYA MUTEA RCKIA
RCKIB VDD18 VDD18
49 50 51 52 53 54 55 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
Digital Audio I/O (DIR, DIT, DSP)
Host Processor with SPI Port and GPIO
From Reference Source Clock
28 27 Refer to Figure 12
RST H/S DGND VDD33 VDD33 REGEN
Figure 11. Typical Pin Connections for Software Mode Operation +3.3V 10µF +
SRC4194 VDD33 VDD33
DGND
VDD18 VDD18
REGEN
24 25
Install jumper JMP1 and associated bypass capacitors only if +3.3V will be used as the core voltage.
0.1µF
23 10µF + 27 28
26
0.1µF Install jumper JMP2 and associated bypass capacitors only if +1.8V will be used as the core voltage. +1.8V Drive Low when using a +1.8V core supply at the VDD18 pins. Drive High when using a +3.3V core supply at the VDD33 pin in order to enable the on−chip +1.8V linear voltage regulator.
Figure 12. Core Power-Supply Connection Options 34
"#$%# www.ti.com SBFS025B − JUNE 2004 − REVISED SEPTEMBER 2007
INTERFACING TO DIGITAL AUDIO RECEIVERS AND TRANSMITTERS The SRC4194 input and output ports are designed to interface to a variety of audio devices, including receivers and transmitters commonly used for AES/EBU, S/PDIF, and CP1201 communications. Texas Instruments manufactures the DIR1703 digital audio interface receiver and DIT4096/4192 digital audio transmitters to address these applications. Figure 13 illustrates interfacing the DIR1703 to the SRC4194 input port. The DIR1703 operates from a single +3.3V supply, which requires that the VIO supply (pin 56) for the SRC4194 to be set to +3.3V for interface compatibility. DIR1703 RS−422 Receiver AES3, S/PDIF Input
RCV
LRCKO DIN
SRC4194
Figure 14 shows the interface between the SRC4194 output port and the DIT4096 or DIT4192 audio serial port. Once again, the VIO supplies for both the SRC4194 and DIT4096/4192 are set to +3.3V for interface compatibility.
SRC4194
DIT4096, DIT4192
LRCKO
SYNC
TX+
BCKO
SCLK
TX−
SDOUT
AES3, S/PDIF OUTPUT
SDATA
RCKI
MCLK
REF Clock Generator DIT Clock Generator
LRCKI
BCKO
BCKI
DATA
SDIN
SCKO
Clock Select RCLI
Assumes VIO = +3.3V for SRC4194 and DIT4096, DIT4192.
Figure 14. Interfacing the SRC4194 to the DIT4096/4192 Digital Audio Interface Receiver Clock Generator Clock Select Assumes VIO = +3.3V for SRC4194.
Figure 13. Interfacing the SRC4194 to the DIR1703 Digital Audio Interface Receiver
Like the SRC4194 output ports, the DIT4096 and DIT4192 audio serial ports may be configured as a Master or Slave. In cases where the SRC4194 output port is set to Master mode and the DIT4096/4192 is configured as the Slave, it is recommended to use the reference clock source for the corresponding section of the SRC4194 as the master clock source for the DIT4096/4192. This will ensure that the transmitter audio serial port clocks, SYNC and SCLK, are synchronized to the master clock source.
35
"#$%# www.ti.com SBFS025B − JUNE 2004 − REVISED SEPTEMBER 2007
TDM APPLICATIONS The SRC4194 supports a TDM output mode, which allows multiple devices to be daisy-chained together to create a serial frame. Each device occupies one sub-frame within a frame, and each sub-frame carries two channels (Left followed by Right). Each sub-frame is 64 bits long, with 32 bits allotted for each channel. The audio data for each channel is left-justified within the allotted 32 bits. Figure 16 illustrates the TDM frame format, while Figure 15 shows TDM input timing parameters, which are listed in the Electrical Characteristics table of this data sheet.
daisy-chain. For Master mode, the output BCKO frequency is fixed to the reference clock input frequency. The number of devices that can be daisy-chained in TDM mode is dependent upon the output sampling frequency and the bit clock frequency, leading to the following numerical relationship. Number of Daisy-Chained SRC Sections = (fBCKO/fs)/64 Where: fBCKO = Output Port Bit Clock (BCKO), 27MHz maximum fs = Output Port Sampling (or LRCKO) Frequency, 212kHz maximum.
tLROS LRCKO
This relationship holds true for both Slave and Master modes.
tLROH BCKO tTDMS TDMI tTDMH
Figure 15. Input Timing for TDM Mode The frame rate is equal to the output sampling frequency, fs. The BCKO frequency for the TDM interface is N × 64fs, where N is the number of SRC sections included in the
Figure 17 and Figure 18 show typical connection schemes for TDM mode. Although the TMS320C671x DSP family is shown as the audio processing engine in these figures, other TI digital signal processors with a multi-channel buffered serial port (McBSP) may also function with this arrangement. Interfacing to processors from other manufacturers is also possible. Refer to the timing diagrams in this data sheet, along with the equivalent serial port timing diagrams shown in the DSP data sheet to determine compatibility.
LRCKO BCKO SDOUT Left
Right Sub−Frame 1
Left
Right Sub−Frame 2
Left
Right Sub−Frame N
One Frame = 1/fs N = Number of Daisy−Chained Devices One Sub−Frame contains 64 bits, with 32 bits per channel. For each channel, the audio data is Left−Justified, MSB−first format, with the word length determined by the OWL[1:0] pins/bits.
Figure 16. TDM Frame Format
36
"#$%# www.ti.com SBFS025B − JUNE 2004 − REVISED SEPTEMBER 2007
SRC4194 SRC2 Section Slave #2
SRC4194 Slave #N TDMI
SDOUT
DRn
LRCKO
LRCKO
FSRn
BCKO
BCKO
BCKO
RCKI
RCKI
RCKI
SDOUT
TDMI
TMS320C671x McBSP
LRCKO
SDOUT
TDMI
SRC4194 SRC1 Section Slave #1
n = 0 or 1
CLKRn CLKIN or CLKSn
Clock Generator
Figure 17. TDM Interface where All Devices are Slaves
SRC4194 SRC1 Section Master TDMI
SDOUT
SRC4194 SRC2 Section Slave TDMI
SDOUT
TMS320C671x McBSP
SRC4194 Slave #1 TDMI
SDOUT
DRn FSRn
LRCKO
LRCKO
LRCKO
BCKO
BCKO
BCKO
RCKI
RCKI
RCKI
n = 0 or 1
CLKRn CLKIN or CLKSn
Clock Generator
Figure 18. TDM Interface where One Device is Master to Multiple Slaves
37
Revision History DATE
REV
PAGE
9/07
B
1
SECTION Front Page
DESCRIPTION Added U.S. patent number.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PACKAGE OPTION ADDENDUM www.ti.com
5-Sep-2007
PACKAGING INFORMATION Orderable Device
Status (1)
Package Type
Package Drawing
Pins Package Eco Plan (2) Qty
SRC4194IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
SRC4194IPAGG4
ACTIVE
TQFP
PAG
64
160
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
SRC4194IPAGR
ACTIVE
TQFP
PAG
64
1500 Green (RoHS & no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
SRC4194IPAGRG4
ACTIVE
TQFP
PAG
64
1500 Green (RoHS & no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
SRC4194IPAGT
ACTIVE
TQFP
PAG
64
250
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
SRC4194IPAGTG4
ACTIVE
TQFP
PAG
64
250
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins Type Drawing
SPQ
Reel Reel Diameter Width (mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1 (mm)
W Pin1 (mm) Quadrant
SRC4194IPAGR
TQFP
PAG
64
1500
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
SRC4194IPAGT
TQFP
PAG
64
250
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SRC4194IPAGR
TQFP
PAG
64
1500
346.0
346.0
41.0
SRC4194IPAGT
TQFP
PAG
64
250
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK 0,27 0,17
0,50 48
0,08 M
33
49
32
64
17 0,13 NOM 1
16 7,50 TYP Gage Plane
10,20 SQ 9,80 12,20 SQ 11,80
0,25 0,05 MIN
1,05 0,95
0°– 7° 0,75 0,45
Seating Plane 0,08
1,20 MAX
4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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