40 μa Micropower Instrumentation Amplifier In Wlcsp Package Ad8235

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40 μA Micropower Instrumentation Amplifier in WLCSP Package AD8235 FEATURES CONNECTION DIAGRAM ESD PROTECTION ESD PROTECTION ESD PROTECTION 210kΩ 52.5kΩ 52.5kΩ –VS A1 D1 210kΩ OP AMP A NC B2 NC D2 ESD PROTECTION OP AMP B ESD PROTECTION ESD PROTECTION A3 D3 B1 VOUT 08211-001 AD8235 +IN –IN Figure 1. PIN CONFIGURATION BALL A1 INDICATOR 1 2 3 +VS SDN –IN VOUT NC RG A B GENERAL DESCRIPTION REF The AD8235 is the smallest and lowest power instrumentation amplifier in the industry. It is available in a 1.5 mm × 2.2 mm wafer level chip scale package (WLCSP). The AD8235 draws a maximum quiescent current of 40 μA. In addition, it draws a maximum 500 nA of current during shutdown mode, making it an excellent instrumentation amplifier for battery powered, portable applications. RG C –VS NC +IN D TOP VIEW (BALL SIDE DOWN) Not to Scale NC = NO CONNECT Figure 2. 11-Ball WLCSP (CB-11-1) 5.0 INPUT COMMON-MODE VOLTAGE (V) It is specified over the extended industrial temperature range of −40°C to 125°C. +VS A2 SDN REF C1 Medical instrumentation Low-side current sense Portable electronics The AD8235 is an excellent choice for signal conditioning. Its low input bias current of 50 pA and high CMRR of 110 dB (G = 100) offer tremendous value for its size and low power. RG C3 APPLICATIONS The AD8235 can operate on supply voltages as low as 1.8 V. The input stage allows for wide rail-to-rail input voltage range without the crossover distortion, common in other designs. The rail-torail output enables easy interfacing to ADCs. RG RG B3 08211-004 Low power 40 μA maximum supply current 6 nA shutdown current Low input currents 50 pA input bias current 25 pA input offset current High Common Mode Rejection Ratio (CMRR) 110 dB CMRR , G = 100 Space saving WLCSP package Zero input crossover distortion Versatile Rail-to-rail input and output Shutdown Gain set with single resistor (G = 5 to 200) AD8236: μSOIC package version of AD8235 4.5 G=5 VS = 5V VREF = 2.5V 4.0 3.5 3.0 2.5 2.0 1.5 G=5 VS = 1.8V VREF = 0.9V 1.0 0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5 5.0 5.5 08211-002 0.5 Figure 3. Wide Common-Mode Voltage Range vs. Output Voltage Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD8235 TABLE OF CONTENTS Features .............................................................................................. 1 Shutdown Feature....................................................................... 15 Applications ....................................................................................... 1 Layout Recommendations ........................................................ 15 General Description ......................................................................... 1 Reference Terminal .................................................................... 16 Connection Diagram ....................................................................... 1 Power Supply Regulation and Bypassing ................................ 16 Pin Configuration ............................................................................. 1 Input Bias Current Return Path ............................................... 17 Revision History ............................................................................... 2 Input Protection ......................................................................... 17 Specifications..................................................................................... 3 RF Interference ........................................................................... 17 Absolute Maximum Ratings............................................................ 7 Common-Mode Input Voltage Range ..................................... 18 Thermal Resistance ...................................................................... 7 Applications Information .............................................................. 19 Pin Configuration and Function Descriptions ............................. 8 AC-Coupled Instrumentation Amplifier ................................ 19 Typical Performance Characteristics ............................................. 9 Low Power Heart Rate Monitor ............................................... 19 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 20 Basic Operation .......................................................................... 14 Ordering Guide .......................................................................... 20 Gain Selection ............................................................................. 14 REVISION HISTORY 8/09—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD8235 SPECIFICATIONS +VS = 5 V, −VS = 0 V (GND), VREF = 2.5 V, TA = 25°C, G = 5, RLOAD = 100 kΩ to GND, SDN pin tied to +VS, unless otherwise noted. Table 1. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC G=5 G = 10 G = 100 G = 200 NOISE Voltage Noise Spectral Density, RTI RTI, 0.1 Hz to 10 Hz G=5 G = 200 Current Noise VOLTAGE OFFSET Input Offset, VOS Average Temperature Coefficient (TC) Offset RTI vs. Supply (PSR) G=5 G = 10 G = 100 G = 200 INPUT CURRENT Input Bias Current Overtemperature Input Offset Current Overtemperature DYNAMIC RESPONSE Small Signal Bandwidth, −3 dB G=5 G = 10 G = 100 G = 200 Settling Time 0.01% G=5 G = 10 G = 100 G = 200 Slew Rate G = 5 to 100 Test Conditions VS = ±2.5 V, VREF = 0 V VCM = −1.8 V to +1.8 V Min Typ 90 90 100 100 94 100 110 110 dB dB dB dB 76 nV/√Hz 4 4 15 μV p-p μV p-p fA/√Hz f = 1 kHz, G = 5 Max 2.5 −40°C to +125°C VS = 1.8 V to 5 V 100 110 110 110 Unit 0.7 mV μV/°C 120 126 130 130 dB dB dB dB 1 −40°C to +85°C −40°C to +125°C 0.5 −40°C to +85°C −40°C to +125°C 50 100 600 25 50 130 pA pA pA pA pA pA 23 9 0.8 0.4 kHz kHz kHz kHz 444 456 992 1816 μs μs μs μs 9 mV/μs VOUT = 4 V step Rev. 0 | Page 3 of 20 AD8235 Parameter GAIN Gain Range Gain Error G=5 G = 10 G = 100 G = 200 Nonlinearity G=5 G = 10 G = 100 G = 200 Gain vs. Temperature G=5 G > 10 INPUT Differential Impedance Common-Mode Impedance Input Voltage Range OUTPUT Output Voltage High, VOH Output Voltage Low, VOL Short-Circuit Limit, ISC REFERENCE INPUT RIN IIN Voltage Range Gain to Output SHUTDOWN OPERATION Shutdown current Test Conditions Min G = 5 + 420 kΩ/RG VS = ±2.5 V, VREF = 0 V, VOUT = −2 V to +2 V 5 Typ Max Unit 200 1 V/V 0.005 0.03 0.06 0.15 0.05 0.2 0.2 0.3 % % % % 2 1.2 0.5 0.5 10 10 10 10 ppm ppm ppm ppm 0.35 1.5 −50 ppm/°C ppm/°C +VS GΩ||pF GΩ||pF V RL = 10 kΩ or 100 kΩ −40°C to +125°C 440||1.6 110||6.2 −40°C to +125°C 0 RL = 100 kΩ −40°C to +125°C RL = 10 kΩ −40°C to +125°C RL = 100 kΩ −40°C to +125°C RL = 10 kΩ −40°C to +125°C 4.98 4.98 4.9 4.9 4.99 4.95 2 10 ±55 −IN, +IN = 0 V 210 20 −VS +VS 1 6 −40°C to +125°C SDN PIN INPUT VOLTAGE RANGE VOH VOL POWER SUPPLY Operating Range Quiescent Current Overtemperature TEMPERATURE RANGE For Specified Performance 1 5 5 25 30 −40°C to +125°C −40°C to +125°C +VS − 0.5 −VS 1.8 30 −40°C to +125°C −40 Although the specifications of the AD8235 list only low to midrange gains, gains can be set beyond 200. Rev. 0 | Page 4 of 20 V V V V mV mV mV mV mA kΩ nA V V/V 500 1.5 nA μA +VS −VS + 0.5 V V 5.5 40 50 V μA μA +125 °C AD8235 +VS = 1.8 V, −VS = 0 V (GND), VREF = 0.9 V, TA = 25°C, G = 5, RLOAD = 100 kΩ to GND, SDN pin tied to +VS, unless otherwise noted. Table 2. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC G=5 G = 10 G = 100 G = 200 NOISE Voltage Noise Spectral Density, RTI RTI, 0.1 Hz to 10 Hz G=5 G = 200 Current Noise VOLTAGE OFFSET Input Offset, VOS Average Temperature Coefficient (TC) Offset RTI vs. Supply (PSR) G=5 G = 10 G = 100 G = 200 INPUT CURRENT Input Bias Current Overtemperature Input Offset Current Overtemperature DYNAMIC RESPONSE Small Signal Bandwidth, –3 dB G=5 G = 10 G = 100 G = 200 Settling Time 0.01% G=5 G = 10 G = 100 G = 200 Slew Rate G = 5 to 100 Test Conditions VS = ±0.9 V, VREF = 0 V VCM = −0.6 V to +0.6 V Min Typ 90 90 100 100 94 100 110 110 dB dB dB dB 76 nV/√Hz 4 4 15 μV p-p μV p-p fA/√Hz f = 1 kHz, G = 5 Max 2.5 −40°C to +125°C VS = 1.8 V to 5 V 100 110 110 110 Unit 0.7 mV μV/°C 120 126 130 130 dB dB dB dB 1 −40°C to +85°C −40°C to +125°C 0.5 −40°C to +85°C −40°C to +125°C 50 100 600 25 50 130 pA pA pA pA pA pA 23 9 0.8 0.4 kHz kHz kHz kHz 143 178 1000 1864 μs μs μs μs 11 mV/μs VOUT = 1.4 V step Rev. 0 | Page 5 of 20 AD8235 Parameter GAIN Gain Range Gain Error G=5 G = 10 G = 100 G = 200 Nonlinearity G=5 G = 10 G = 100 G = 200 Gain vs. Temperature G=5 G > 10 INPUT Differential Impedance Common-Mode Impedance Input Voltage Range OUTPUT Output Voltage High, VOH Output Voltage Low, VOL Short-Circuit Limit, ISC REFERENCE INPUT RIN IIN Voltage Range Gain to Output SHUTDOWN OPERATION Shutdown Current Test Conditions Min G = 5 + 420 kΩ/RG VS = ±0.9 V, VREF = 0 V, VOUT = −0.6 V to +0.6 V 5 1 Max Unit 200 1 V/V 0.005 0.03 0.06 0.15 0.05 0.2 0.2 0.3 % % % % 1 1 0.5 0.4 10 10 10 10 ppm ppm ppm ppm 0.35 1.5 −50 ppm/°C ppm/°C +VS GΩ||pF GΩ||pF V RL = 10 kΩ or 100 kΩ −40°C to +125°C 440||1.6 110||6.2 −40°C to +125°C 0 RL = 100 kΩ −40°C to +125°C RL = 10 kΩ −40°C to +125°C RL = 100 kΩ −40°C to +125°C RL = 10 kΩ −40°C to +125°C 1.78 1.78 1.65 1.65 1.79 1.75 2 12 5 5 25 25 ±6 −IN, +IN = 0 V 210 20 −VS +VS 1 6 −40°C to +125°C −40°C to +125°C Although the specifications of the AD8235 list only low to midrange gains, gains can be set beyond 200. Rev. 0 | Page 6 of 20 V V V V mV mV mV mV mA kΩ nA V V/V 500 1.5 nA μA +VS − 0.5 −VS +VS −VS + 0.5 V V −40 +125 °C −40°C to +125°C SDN PIN INPUT VOLTAGE RANGE VOH VOL TEMPERATURE RANGE For Specified Performance Typ AD8235 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Supply Voltage Output Short-Circuit Current Input Voltage (Common Mode) Differential Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature ESD Human Body Model Charge Device Model Machine Model Rating 6V 55 mA ±VS ±VS −65°C to +125°C −40°C to +125°C 125°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This was measured using a standard 4-layer board, unless otherwise specified. Table 4. Thermal Resistance Package Type 11-Ball WLCSP CB-11-1 PCB 1S0P 1 2S2P 2 1.5 kV 0.5 kV 200 V 1 Power (W) 0.25 1.25 0.25 1.25 θJA (°C/W) 139.1 130 69.5 68.3 Simulated thermal numbers per JESD51-9: 1-layer PCB (1S0P), low effective thermal conductivity test board. 2 4-layer PCB (2S2P), high effective thermal conductivity test board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 7 of 20 AD8235 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 1 2 3 +VS SDN –IN VOUT NC RG A B REF RG –VS NC +IN D 08211-004 C TOP VIEW (BALL SIDE DOWN) Not to Scale NC = NO CONNECT Figure 4. Pin Configuration (Top View Looking Through Package) Table 5. Pin Function Descriptions Pin No. A1 B1 C1 D1 A2 B2, D2 A3 B3, C3 D3 Mnemonic +VS VOUT REF −VS SDN NC −IN RG +IN Description Positive Power Supply Terminal. Output Terminal. Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output. Negative Power Supply Terminal. Shutdown Pin. Tie to −VS for shutdown. Tie to +VS for normal operation. No Connect. Leave both pins floating. Should not connect to any potential. Negative Input Terminal (True Differential Input). Gain Setting Terminals. Place resistor across the RG pins. Positive Input Terminal (True Differential Input). Rev. 0 | Page 8 of 20 AD8235 TYPICAL PERFORMANCE CHARACTERISTICS G = 5, +VS = 5 V, VREF = 2.5 V, RL = 100 kΩ tied to GND, TA = 25°C, SDN pin connected to +VS, unless otherwise noted 2400 GAIN = 5 NUMBER OF UNITS 2100 1800 1500 1200 900 0 –40 08211-105 300 –30 –20 –10 0 10 CMRR (µV/V) 20 5µV/DIV 1s/DIV 08211-008 600 40 30 Figure 8. 0.1 Hz to 10 Hz RTI Voltage Noise Figure 5. CMRR Distribution 400 GAIN = 200 NUMBER OF UNITS 350 300 250 200 150 0 –3000 08211-005 50 –2000 –1000 0 VOSI (µV) 1000 2000 1s/DIV 5µV/DIV 08211-009 100 3000 Figure 9. 0.1 Hz to 10 Hz RTI Voltage Noise Figure 6. Typical Distribution of Input Offset Voltage 140 1k 120 GAIN = 200 GAIN = 100 PSRR (dB) GAIN = 5 GAIN = 200 BANDWIDTH LIMITED INTERNAL CLIPPING 80 60 40 20 10 1 10 100 FREQUENCY (Hz) 1k 10k 0 Figure 7. Voltage Noise Spectral Density vs. Frequency GAIN = 10 GAIN = 5 0.1 1 10 100 1k FREQUNCY (Hz) 10k Figure 10. Positive PSRR vs. Frequency, RTI, VS = ±0.9 V, ±2.5 V, VREF = 0 V Rev. 0 | Page 9 of 20 100k 08211-010 100 08211-007 NOISE (nV/√Hz) 100 AD8235 120 10 GAIN = 100 100 GAIN = 200 CMRR (µV/V) PSRR (dB) 5 GAIN = 10 80 GAIN = 5 60 0 40 –5 1 10 100 1k 10k 100k FREQUENCY (Hz) –10 –40 Figure 11. Negative PSRR vs. Frequency, RTI, VS = ±0.9 V, ±2.5 V, VREF = 0 V 50 100 120 GAIN = 100 30 60 GAIN (dB) GAIN = 200 GAIN = 100 40 GAIN = 10 20 10 GAIN = 5 0 –10 GAIN = 10 –20 20 –30 GAIN = 5 10 100 1k 10k 100k FREQUENCY (Hz) –40 08211-012 1 10 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. CMRR vs. Frequency, RTI Figure 15. Gain vs. Frequency, VS = 1.8 V, 5 V 6 100 5 80 4 VOUT (V p-p) 120 60 100 08211-015 CMRR (dB) 80 GAIN = 200 40 80 GAIN = 200 GAIN = 100 40 3 2 20 1 GAIN = 5 GAIN = 10 1 10 100 1k 10k 100k FREQUENCY (Hz) 08211-013 CMRR (dB) 20 40 60 TEMPERATURE (°C) 60 100 0 0.1 0 Figure 14. Change in CMRR vs. Temperature, G = 5, Normalized at 25°C 120 0 0.1 –20 Figure 13. CMRR vs. Frequency, 1 kΩ Source Imbalance, RTI 0 1 10 100 1k FREQUENCY (Hz) 10k Figure 16. Maximum Output Voltage vs. Frequency Rev. 0 | Page 10 of 20 100k 08211-016 0.1 08211-011 0 08211-014 20 AD8235 RLOAD = 100kΩ TIED TO GND RLOAD = 10kΩ TIED TO GND 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE (V) 3.5 4.0 4.5 3.5 3.0 2.5 2.0 1.5 1.0 0 –0.5 08211-017 1.0 (4.98V, 4.737V) (0.01V, 4.24V) 4.0 (4.98V, 0.767V) (0.01V, 0.27V) 0.5 VS = 5V 0.5 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT VOLTAGE (V) 08211-020 INPUT COMMON-MODE VOLTAGE (V) NONLINEARITY (5ppm/DIV) 5.0 Figure 20. Input Common-Mode Voltage Range vs. Output Voltage, G = 5, VS = 5 V, VREF = 2.5 V Figure 17. Gain Nonlinearity, G = 5 TWO CURVES REPRESENTED: RLOAD = 10kΩ AND 100kΩ TIED TO GND 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE (V) 3.5 4.0 4.5 3.5 3.0 2.5 2.0 1.5 1.0 0 –0.5 08211-018 1.0 (4.994V, 4.75V) (0.01V, 4.25V) 4.0 (4.994V, 0.076V) (0.01V, 0.026V) 0.5 VS = 5V 0.5 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT VOLTAGE (V) Figure 18. Gain Nonlinearity, G = 10 08211-021 INPUT COMMON-MODE VOLTAGE (V) NONLINEARITY (2ppm/DIV) 5.0 Figure 21. Input Common-Mode Voltage Range vs. Output Voltage, G = 200, VS = 5 V, VREF = 2.5 V TWO CURVES REPRESENTED: RLOAD = 10kΩ AND 100kΩ TIED TO GND VS = 5V 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE (V) 3.5 4.0 4.5 (1.78V, 1.704V) (0.0069V, 1.52V) 1.4 1.2 1.0 0.8 0.6 0.4 (1.78V, 0.274V) (0.0069V, 0.09V) 0.2 0 –0.2 08211-019 0.5 1.6 0 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT VOLTAGE (V) 1.4 1.6 1.8 2.0 08211-022 INPUT COMMON-MODE VOLTAGE (V) NONLINEARITY (2ppm/DIV) 1.8 Figure 22. Input Common-Mode Voltage Range vs. Output Voltage, G = 5, VS = 1.8 V, VREF = 0.9 V Figure 19. Gain Nonlinearity, G = 200 Rev. 0 | Page 11 of 20 AD8235 1.8 INPUT COMMON-MODE VOLTAGE (V) 1.6 (1.75V, 1.705V) (0.03V, 1.533V) 1.4 1.2 2V/DIV 1.0 0.8 444μs TO 0.01% 0.6 0.4 (1.75V, 0.275V) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT VOLTAGE (V) 1ms/DIV Figure 23. Input Common-Mode Voltage Range vs. Output Voltage, G = 200, VS = 1.8 V, VREF = 0.9 V 08211-026 0 –0.2 08211-023 (0.03V, 0.103V) 0.2 Figure 26. Large Signal Pulse Response and Settling Time, VS = ±2.5 V, VREF = 0 V, RLOAD = 10 kΩ to VREF +VS –0.002 –0.003 +125°C +85°C –40°C +25°C 700mV/DIV OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGE –0.001 143.2μs TO 0.01% +0.003 +0.002 +125°C +85°C +25°C –40°C 2.3 2.8 3.3 3.8 4.3 SUPPLY VOLTAGE (V) 4.8 1ms/DIV Figure 24. Output Voltage Swing vs. Supply Voltage, VS = ±0.9 V, ±2.5 V, VREF = 0 V, RLOAD = 100 kΩ Tied to −VS 0 8211-027 –VS 1.8 08211-024 +0.001 Figure 27. Large Signal Pulse Response and Settling Time, VS = ±0.9 V, VREF = 0 V, RLOAD = 10 kΩ to VREF +VS +25°C +85°C +125°C –0.2 20mV/DIV –0.3 –40°C +0.003 +0.002 +125°C +85°C +25°C –40°C –VS 1k 10k RLOAD (Ω) 100k Figure 25. Output Voltage Swing vs. Load Resistance, VS = ±0.9 V, ±2.5 V, VREF = 0 V, RLOAD = 100 kΩ Tied to −VS 100µs/DIV Figure 28. Small Signal Pulse Response, G = 5, VS = ±2.5 V, VREF = 0 V, RLOAD = 100 kΩ to VREF, CL = 100 pF Rev. 0 | Page 12 of 20 08211-028 +0.001 08211-025 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGE –0.1 AD8235 500 20mV/DIV SETTLING TIME (µs) 400 300 200 0 1 0 2 3 08211-032 100µs/DIV 08211-029 100 4 OUTPUT VOLTAGE STEP SIZE (V) Figure 32. Settling Time vs. Output Voltage Step Size, VS = ±2.5 V, VREF = 0 V, RLOAD = 10 kΩ Tied to VREF Figure 29. Small Signal Pulse Response, G = 5, CL = 100 pF, VS = ±0.9 V, VREF = 0 V, RLOAD = 100 kΩ to VREF 40 38 20mV/DIV SUPPLY CURRENT (µA) 36 1.8V 34 32 30 5V 28 26 24 20 –40 Figure 30. Small Signal Pulse Response, G = 200, CL = 100 pF, VS = 2.5 V, VREF = 0 V, RLOAD = 100 kΩ to VREF –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 08211-033 1ms/DIV 08211-030 22 Figure 33. Total Supply Current vs. Temperature 600 20mV/DIV SUPPLY CURRENT (nA) 500 400 300 VS = 5V 200 100 VS = 1.8V –100 –40 –25 Figure 31. Small Signal Pulse Response, G = 200, CL = 100 pF, VS = 0.9 V, VREF = 0 V, RLOAD = 100 kΩ to VREF –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 34. Total Supply Current During Shutdown vs. Temperature Rev. 0 | Page 13 of 20 0 8211-043 1ms/DIV 08211-031 0 AD8235 THEORY OF OPERATION B3 RG ESD PROTECTION REF C1 ESD PROTECTION 210kΩ RG C3 +VS –VS A1 D1 ESD PROTECTION 52.5kΩ A2 SDN B1 VOUT 210kΩ OP AMP A NC B2 NC D2 52.5kΩ RG ESD PROTECTION OP AMP B ESD PROTECTION ESD PROTECTION A3 D3 –IN +IN 08211-034 AD8235 Figure 35. Simplified Schematic BASIC OPERATION The AD8235 amplifies the difference between its positive input (+IN) and its negative input (−IN). The REF pin allows the user to level-shift the output signal. This is convenient when interfacing to a filter or analog-to-digital converter (ADC). The basic setup is shown in Figure 36. Figure 39 shows an example configuration for operating the AD8235 with dual supplies. The equation for the AD8235 is as follows: VOUT = G × (VINP − VINM) + VREF If no gain setting resistor is installed, the default gain, G, is 5. The Gain Selection section describes how to program the gain, G. 5V SDN VINP GAIN SETTING RESISTOR VINM +IN +VS RG RG –IN 0.1µF AD8235 OUT VOUT REF –VS VREF 08211-035 The AD8235 is a monolithic, two-op amp instrumentation amplifier. It is designed for low power, portable applications where size and low quiescent current are paramount. The AD8235 is offered in a WLCSP package, minimizing layout area. Additional features that make this part optimal for portable applications include a rail-to-rail input and output stage that offers more dynamic range when operating on low voltage batteries. Unlike traditional rail-to-rail input amplifiers that use a complementary differential pair stage and suffer from nonlinearity, the AD8235 uses a novel architecture to internally boost the supply rail, allowing the amplifier to operate rail-torail yet still deliver a low 0.5 ppm of nonlinearity. In addition, the two-op amp instrumentation amplifier architecture offers a wide operational common-mode voltage range. Additional information is provided in the Common-Mode Input Voltage Range section. Precision, laser-trimmed resistors provide the AD8235 with a high CMRR of 90 dB (minimum) at G = 5 and gain accuracy of 0.05% (maximum). Figure 36. Basic Setup GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the AD8235. The gain may be derived by referring to Table 6 or by using the following equation: RG = 420 kΩ G −5 Table 6. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG (kΩ) 422 210 140 105 84.5 28 9.31 4.42 2.15 Calculated Gain 6.0 7.0 8.0 9.0 10.0 20.0 50.1 100.0 200.3 The AD8235 defaults to G = 5 when no gain resistor is used. Gain accuracy is determined by the absolute tolerance of RG. The TC of the external gain resistor increases the gain drift of the instrumentation amplifier. Gain error and gain drift are at a minimum when the gain resistor is not used. Rev. 0 | Page 14 of 20 AD8235 SHUTDOWN FEATURE The AD8235 includes a shutdown pin (SDN) that further enhances the flexibility and ease of use in portable applications where power consumption is critical. A logic level signal can be applied to this pin to switch to shutdown mode, even when the supply is still on. When connecting the SDN pin to +VS or applying a voltage within +VS − 0.5 V, the AD8235 operates in its normal condition and, therefore, draws approximately 40 μA of supply current. When connecting the SDN pin to −VS, or any voltage within −VS + 0.5 V, the AD8235 operates in shutdown mode and, therefore, draws less than 500 nA of supply current, offering considerable power savings. In cases where the AD8235 is operating in shutdown mode, if a voltage potential exists at the REF pin, and there is a load to −VS at the output of the part, some additional current draw is noticeable. In this mode, a path from the REF pin to −VS exists, leading to some additional current draw from the reference. Typically, this current is negligible because the output of the AD8235 is driving a high impedance node, such as the input of an ADC. LAYOUT RECOMMENDATIONS The critical board design parameters, as it pertains to a WLCSP package, are pad opening, pad type, pad finish, and board thickness. Pad Opening Based on the IPC (Institute for Printed Circuits) standard, the pad opening equals the UBM (Under Bump Metallurgy) opening. The typical pad openings for the AD8235 shown in Figure 37 are: • 250 μm (0.5 mm pitch WLCSP) The solder mask opening is 100 μm plus the pad opening (or 350 μm in the case of the AD8235). The trace width should be less than two-thirds of the pad opening. Increasing the trace width can cause reduction in the stand-off height of the solder bump. Therefore, maintaining the proper trace width ratio is important to ensure the reliability of the solder connections. PAD OPENING MASK OPENING 0 8211-044 TRACE WIDTH Figure 37. Pad Opening Pad Type For the actual board fabrication, the following types of pads/land patterns are used for surface mount assembly: • Nonsolder mask defined (NSMD). The metal pad on the PCB (to which the I/O is attached) is smaller than the solder mask opening. • Solder mask defined (SMD). The solder mask opening is smaller than the metal pad. Because the copper etching process has tighter control than the solder mask opening process, NSMD is preferred over SMD. The solder mask opening on NSMD pads is larger than the copper pads, allowing the solder to attach to the sides of the copper pad and improving the reliability of the solder joints. Pad Finish The finish layer on the metal pads has a significant effect on assembly yield and reliability. The typical metal pad finishes used are organic surface preservative (OSP) and electroless nickel immersion gold (ENIG). The thickness of the OSP finish on a metal pad is 0.2 μm to 0.5 μm. This finish evaporates during the reflow soldering process and interfacial reactions occur between the solder and metal pad. The ENIG finish consists of 5 μm of electroless nickel and 0.02 μm to 0.05 μm of gold. During reflow soldering, the gold layer dissolves rapidly, followed by reaction between the nickel and solder. It is extremely important to keep the thickness of gold below 0.05 μm to prevent the formation of brittle intermetallic compounds. Rev. 0 | Page 15 of 20 AD8235 INCORRECT Board Thickness Typical board thicknesses used in the industry range from 0.4 mm to 1.6 mm and are most applicable for the AD8235. The thickness selected depends on the required robustness of the populated system assembly. The thinner board results in smaller shear stress range, creep shear strain range, and creep strain energy density range in the solder joints under the thermal loading. Therefore, the thinner build-up board leads to longer thermal fatigue life of solder joints [John H. Lau and S.W. Ricky Lee]1 The output voltage of the AD8235 is developed with respect to the potential on the reference terminal, REF. To ensure the most accurate output, the trace from the REF pin should either be connected to the AD8235 local ground (see Figure 39) or connected to a voltage that is referenced to the AD8235 local ground (Figure 36). REFERENCE TERMINAL The reference terminal, REF, is at one end of a 210 kΩ resistor (see Figure 35). The output of the instrumentation amplifier is referenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than common. For example, a voltage source can be tied to the REF pin to level-shift the output so that the AD8235 can interface with an ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +VS or −VS by more than 0.5 V. AD8235 AD8235 REF REF V V + OP AMP 08211-036 – Figure 38. Driving the REF Pin POWER SUPPLY REGULATION AND BYPASSING The AD8235 has high power supply rejection ration (PSRR). However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. As in all linear circuits, bypass capacitors must be used to decouple the amplifier. A 0.1 μF capacitor should be placed close to each supply pin. A 10 μF tantalum capacitor can be used farther away from the part (see Figure 39). In most cases, it can be shared by other precision integrated circuits. For best performance, especially in cases where the output is not measured with respect to the REF terminal, source impedance to the REF terminal should be kept low because parasitic resistance can adversely affect CMRR and gain accuracy. Figure 38 demonstrates how an op amp is configured to provide a low source impedance to the REF terminal when a midscale reference voltage is desired. 1 John H. Lau and S.W. Ricky Lee, “Effects of Build-Up Printed Circuit Board Thickness on the Solder Joint Reliability of a Wafer Level Chip Scale Package (WLCSP),” IEEE Transactions on Components and Packaging Technologies, Vol.25, No.1, March 2002, pages 3-14. Rev. 0 | Page 16 of 20 +VS SDN 0.1µF 10µF +IN VOUT AD8235 LOAD REF –IN –VS 0.1µF –VS 10µF 08211-037 Grounding CORRECT Figure 39. Supply Decoupling, REF, and Output Referred to Ground AD8235 +VS +VS AD8235 AD8235 REF REF –VS –VS TRANSFORMER TRANSFORMER +VS +VS C C 1 fHIGH-PASS = 2πRC AD8235 R AD8235 REF REF R –VS AC-COUPLED 08211-038 –VS AC-COUPLED Figure 40. Creating an IBIAS Path INPUT BIAS CURRENT RETURN PATH RF INTERFERENCE The AD8235 input bias current is extremely small at less than 50 pA. Nonetheless, the input bias current must have a return path to common. When the source, such as a transformer, cannot provide a return current path, one should be created (see Figure 40). RF rectification is often a problem in applications where there are large RF signals. The problem appears as a small dc offset voltage. The AD8235, by its nature, has a 3.1 pF gate capacitance, CG, at each input. Matched series resistors form a natural low-pass filter that reduces rectification at high frequency (see Figure 41). The relationship between external, matched series resistors and the internal gate capacitance is expressed as All terminals of the AD8235 are protected against ESD. In addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. Voltages beyond a diode drop of the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, an external resistor should be used in series with each of the inputs to limit current for voltages above +VS. In either scenario, the AD8235 safely handles a continuous 6 mA current at room temperature. For applications where the AD8235 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s, should be used. FilterFreq DIFF = FilterFreq CM = 1 2πRC G 1 2πRC G +VS 0.1µF 10µF SDN R +IN CG AD8235 –VS R VOUT CG –IN –VS 0.1µF REF 10µF –VS Figure 41. RFI Filtering Without External Capacitors Rev. 0 | Page 17 of 20 08211-039 INPUT PROTECTION AD8235 To eliminate high frequency common-mode signals while using smaller source resistors, a low-pass RC network can be placed at the input of the instrumentation amplifier (see Figure 42). The filter limits the input signal bandwidth according to the following relationship: FilterFreq DIFF = FilterFreq CM = 1 2πR(2 C D + C C + C G ) COMMON-MODE INPUT VOLTAGE RANGE The common-mode input voltage range is a function of the input voltages, reference voltage, supplies, and the output of Internal Op Amp A. Figure 35 shows the internal nodes of the AD8235. Figure 20 to Figure 23 show the common-mode voltage ranges for typical supply voltages and gains. If the supply voltages and reference voltage are not represented in Figure 20 to Figure 23, the following methodology can be used to calculate the acceptable common-mode voltage range: 1 2πR(C C + C G ) Mismatched CC capacitors result in mismatched low-pass filters. The imbalance causes the AD8235 to treat what is a commonmode signal as a differential signal. To reduce the effect of mismatched external CC capacitors, select a value of CD greater than 10× CC. This sets the differential filter frequency lower than the common-mode frequency. 1. 2. A= +VS 0.1µF CC R 10µF SDN 1nF +IN 4.02kΩ CD VOUT AD8235 10nF R 3. REF –IN 4.02kΩ V V DIFF ⎞ 52.5 kΩ 5⎛ V DIFF − REF ⎜ VCM − ⎟− 4⎝ 2 ⎠ RG 4 where: VDIFF is defined as the difference in input voltages, VDIFF = VINP − VINM. VCM is defined as the common-mode voltage, VCM = (VINP + VINM)/2. If no gain setting resistor, RG, is installed, set RG to infinity. Keep A within 10 mV of either supply rail. This is valid over the −40°C to +125°C temperature range. 1nF 08211-040 CC Adhere to the input, output, and reference voltage ranges shown in Table 1 and Table 2. Calculate the output of Internal Op Amp A. The following equation calculates this output: −VS + 10 mV < A < +VS – 10 mV Figure 42. RFI Suppression Rev. 0 | Page 18 of 20 AD8235 APPLICATIONS INFORMATION AC-COUPLED INSTRUMENTATION AMPLIFIER LOW POWER HEART RATE MONITOR An integrator can be tied to the AD8235 in feedback to create a high-pass filter, as shown in Figure 43. This circuit can be used to reject dc voltages and offsets. At low frequencies, the impedance of the capacitor, C, is high. Therefore, the gain of the integrator is high. DC voltage at the output of the AD8235 is inverted and gained by the integrator. The inverted signal is injected back into the REF pin, nulling the output. In contrast, at high frequencies, the integrator has low gain because the impedance of C is low. Voltage changes at high frequencies are inverted but at a low gain. The signal is injected into the REF pins, but it is not enough to null the output. At very high frequencies, the capacitor appears as a short. The op amp is at unity gain. High frequency signals are, therefore, allowed to pass. The low power and small size of the AD8235 make it an excellent choice for heart rate monitors. As shown in Figure 44, the AD8235 measures the biopotential signals from the body. It rejects common-mode signals and serves as the primary gain stage set at G = 5. The 4.7 μF capacitor and the 100 kΩ resistor set the −3 dB cutoff of the high-pass filter that follows the instrumentation amplifier. It rejects any differential dc offsets that may develop from the half-cell overpotential of the electrode. When a signal exceeds fHIGH-PASS, the AD8235 outputs the highpass filtered input signal. This circuit was designed and tested using the AD8609, low power, quad op amp. The fourth op amp is configured as a Schmitt trigger to indicate if the right arm or left arm electrodes fall off the body. Used in conjunction with the 953 kΩ resistors at the inputs of the AD8235, the resistors pull the inputs apart when the electrodes fall off the body. The Schmitt trigger sends an active low signal to indicate a leads off condition. A secondary gain stage, set at G = 403, amplifies the ECG signal, which is then sent into a second-order, low-pass, Bessel filter with −3 dB cutoff at 48 Hz. The 324 Ω resistor and 1 μF capacitor serve as an antialiasing filter. The 1 μF capacitor also serves as a charge reservoir for the ADC switched capacitor input stage. +VS 0.1µF SDN +IN fHIGH-PASS = 1 2πRC The reference electrode (right leg) is set tied to ground. Likewise, the shield of the electrode cable is also tied to ground. Some portable heart rate monitors do not have a third electrode. In such cases, the negative input of the AD8235 can be tied to GND. AD8235 R REF –IN C +VS Note that this circuit is shown, solely, to demonstrate the capability of the AD8235. Additional effort must be made to ensure compliance with medical safety guidelines. 0.1µF AD8603 VREF 08211-041 +VS 10µF Figure 43. AC-Coupled Circuit +2.5V –2.5V 1kΩ 20kΩ +2.5V 5kΩ +2.5V 0.1µF AD8609 953kΩ RL LEADS OFF 680nF SDN +2.5V 0.1µF AD8235 LA IN-AMP AD8609 24.9kΩ 4.02kΩ AD8609 100kΩ 953kΩ 1kΩ 0.1µF 402kΩ 220nF 0.1µF 324Ω 1µF 10-BIT ADC MCU + ADC 4.7µF –2.5V –2.5V –2.5V +2.5V AD8609 1kΩ 08211-042 RA LEADS OFF DETECTION INTERRUPT –2.5V Figure 44. Example Low Power Heart Rate Monitor Schematic Rev. 0 | Page 19 of 20 AD8235 OUTLINE DIMENSIONS 0.657 0.602 0.546 1.61 1.57 1.53 0.020 REF SEATING PLANE 0.348 0.328 0.308 3 2 1 A BALL A1 IDENTIFIER 2.08 2.04 2.00 0.330 0.310 0.290 1.50 REF B 0.50 REF C D 0.355 0.330 0.304 0.04 MAX COPLANARITY BOTTOM VIEW (BALL SIDE UP) 1.00 REF 0.280 0.250 0.220 060409-A TOP VIEW (BALL SIDE DOWN) 0.230 0.212 0.192 Figure 45. 11-Ball, Backside-Coated, Wafer Level Chip Scale Package [WLCSP] (CB-11-1) Dimensions shown in millimeters ORDERING GUIDE Model AD8235ACBZ-P7 1 1 Temperature Range −40°C to + 125°C Package Description 11-Ball [WLCSP] Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08211-0-8/09(0) Rev. 0 | Page 20 of 20 Package Option CB-11-1 Branding H20