Transcript
HD74LS76A Dual J-K Flip-Flops (with Preset and Clear) REJ03D0417–0300 Rev.3.00 Jul.22.2005
Features • Ordering Information Part Name
Package Type
HD74LS76AP
DILP-16 pin
Package Code (Previous Code) PRDP0016AE-B (DP-16FV)
Package Abbreviation
Taping Abbreviation (Quantity)
P
—
PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability. HD74LS76ARPEL
EL(2,500 pcs/reel)
SOP-16 pin(JEDEC)
Pin Arrangement
1CK
1
16
1K
1PR
2
15
1Q
1CLR
3
14
1Q
1J
4
13
GND
VCC
5
12
2K
2CK
6
11
2Q
10
2Q
9
2J
2PR
7
2CLR
8
J
CK K PR CLR Q
Q
K CK J CLR
PR
Q
Q
(Top view)
Rev.3.00, Jul.22.2005, page 1 of 6
HD74LS76A
Function Table Inputs
Outputs
Preset L
Clear H
Clock X
J X
K X
Q H
Q L
H L
L L
X X
X X
X X
L H*
H H*
H H
H H
↓ ↓
L H
L L
Q0 H
Q0 L
H H
H H
↓ ↓
L H
H H
L
H Toggle
H H H X X Q0 Q0 H; high level, L; low level, X; irrelevant, ↓; transition from high to low level, Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established. Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓. * This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level.
Block Diagram (1/2)
Q
Q
Clear
Preset K
J
Clock
Absolute Maximum Ratings Item Supply voltage
Symbol VCC
Ratings 7
Unit V
VIN PT
7 400
V mW
Tstg
–65 to +150
°C
Input voltage Power dissipation Storage temperature
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions Item Supply voltage Output current Operating temperature Clock frequency
Symbol VCC
Min 4.75
Typ 5.00
Max 5.25
Unit V
IOH IOL
— —
— —
–400 8
µA mA
Topr fclock
–20 0
25 —
75 30
°C MHz
Pulse width
Clock High Clear Preset Low
tw tw
20 25
— —
— —
ns
Setup time
“H” Data “L” Data
tsu tsu
20↓ 20↓
— —
— —
ns
th
0↓
—
—
ns
Hold time
Rev.3.00, Jul.22.2005, page 2 of 6
HD74LS76A
Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage
Symbol VIH
min. 2.0
typ.* —
max. —
Unit V
VIL
—
—
0.8
V
VOH
2.7
—
—
V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA
VOL
— —
— —
0.5 0.4
V
IOL = 8 mA IOL = 4 mA
— —
— —
20 60
— —
— —
60 80
µA
VCC = 5.25 V, VI = 2.7 V
— —
— —
–0.4 –0.8
— —
— —
–0.8 –0.8
mA
VCC = 5.25 V, VI = 0.4 V
— —
— —
0.1 0.3
— —
— —
0.3 0.4
mA
VCC = 5.25 V, VI = 7 V
IOS
–20
—
–100
mA
VCC = 5.25 V
ICC
—
4
6
mA
VCC = 5.25 V
Output voltage
J, K Clear Preset Clock Input current
J, K Clear Preset Clock J, K Clear Preset Clock
Short-circuit output current Supply current***
IIH
IIL**
II
Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V
Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** IIL should not be measured when preset and clear inputs are low at same time. *** With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded.
Switching Characteristics (VCC = 5 V, Ta = 25°C) Item
Symbol
Maximum clock frequency
fmax tPLH
Propagation delay time
Inputs Clear Preset Clock
tPHL
Outputs
Q, Q
min.
typ.
max.
Unit
30 —
45 15
20
MHz ns
—
15
20
ns
Condition CL = 15 pF, RL = 2 kΩ
Timing Definition tw 3V 1.3 V
1.3 V
1.3 V
Clock tsu
th
tsu
0V
th
3V 1.3 V
1.3 V
1.3 V
J, K
0V "H" Data
Rev.3.00, Jul.22.2005, page 3 of 6
"L" Data
HD74LS76A
Testing Method Test Circuit 1. ƒmax, tPLH, tPHL, (Clock→Q, Q) VCC
Output Q
Input 4.5V RL J P.G.
PR
Q CL
CK
Zout=50Ω
Load circuit 1
Output Q
K Q
CLR
Notes:
Same as Load Circuit 1.
1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H).
2. tPHL, tPLH (Clear, Preset→ Q, Q) VCC
Input
Output Q
P.G. Zout=50Ω
RL PR J
Load circuit 1
Q CL
4.5V Input
CK K CLR
Output Q Q
P.G. Zout=50Ω
Notes:
1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H).
Rev.3.00, Jul.22.2005, page 4 of 6
Same as Load Circuit 1.
HD74LS76A Waveforms 1 tTLH
tTHL tw(L)
90% 90% 1.3 V 1.3 V Clock
3V 1.3 V
10%
1.3 V
10%
0V
tw(H) tPLH
tPHL VOH 1.3 V
Q
1.3 V
tPHL
VOL
tPLH
Q
VOH 1.3 V
1.3 V VOL
Note:
Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax., tTLH = tTHL ≤ 2.5 ns
Waveforms 2 tTHL Clear
tTLH 3V
90% 1.3V 10%
90% 1.3V 10% tw (CLR)
0V tTHL
tTLH
90% 1.3V 10%
Preset
90% 1.3V 10% tw (PR)
3V 0V
tPHL tPLH 1.3V
Q
VOH 1.3V
tPLH
VOL VOH
Q
Note:
1.3V
1.3V tPHL
Crear and preset input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz,
Rev.3.00, Jul.22.2005, page 5 of 6
VOL
HD74LS76A
Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54
RENESAS Code PRDP0016AE-B
Previous Code DP-16FV
MASS[Typ.] 1.05g
D
9
E
16
1
8 b3
0.89
Z
A1
A
Reference Symbol
L
e
Nom
c e1
D
19.2
E
6.3
JEITA Package Code P-SOP16-3.95x9.9-1.27
RENESAS Code PRSP0016DG-A
*1
Previous Code FP-16DNV
7.4
A1
0.51
b
p
0.40
b
3
0.48
0.56
1.30
c
0.19
θ
0°
e
2.29
0.25
0.31
2.54
2.79
15°
1.12
L
2.54
MASS[Typ.] 0.15g
D
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
F
16
20.32
5.06
Z ( Ni/Pd/Au plating )
Max
7.62
1
A
θ
bp
e
Dimension in Millimeters Min
9
c
*2
Index mark
HE
E
bp
Reference Symbol
Terminal cross section ( Ni/Pd/Au plating )
Dimension in Millimeters Min
Nom
Max
D
9.90
10.30
E
3.95
A2 1 Z
8 e
*3
bp
x
A1
0.10
0.14
0.25
0.34
0.40
0.46
0.15
0.20
0.25
6.10
6.20
1.75
A
M L1
bp b1 c
A
c
A1
θ L
y
Detail F
1
θ
0°
HE
5.80
1.27
e x
0.25
y
0.15
Z
0.635 0.40
L L
Rev.3.00, Jul.22.2005, page 6 of 6
8°
1
0.60 1.08
1.27
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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