Transcript
8-Bit, 250 MSPS 3.3 V A/D Converter AD9480 FUNCTIONAL BLOCK DIAGRAM
DNL = ± 0.25 LSB INL = ± 0.26 LSB Single 3.3 V supply operation (3.0 V to 3.6 V) Power dissipation of 590 mW at 250 MSPS 1 V p-p analog input range Internal 1.0 V reference Single-ended or differential analog inputs LVDS outputs (ANSI 644 levels) Power-down mode Clock duty-cycle stabilizer
VREF SENSE
AGND
DrGND
T&H
VIN–
CLK+ CLK–
8-BIT ADC PIPELINE CORE
8
CLOCK MGMT
LVDS
16
D7–D0 (LVDS)
DCO+ DCOLOGIC
APPLICATIONS Digital oscilloscopes Instrumentation and measurement Communications Point-to-point radios Predistortion loops
AVDD
AD9480
REFERENCE
VIN+
DRVDD
PDWN
S1
(LVDS)
LVDSBIAS
04619-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9480 is an 8-bit, monolithic analog-to-digital converter (ADC) optimized for high speed and low power consumption. Small in size and easy to use, the product operates at a 250 MSPS conversion rate, with excellent linearity and dynamic performance over its full operating range.
1.
Superior linearity. A DNL of ±0.25 makes the AD9480 suitable for instrumentation and measurement applications.
2.
Power-down mode. A power-down function may be exercised to bring total consumption down to 15 mW.
3.
LVDS outputs (ANSI-644). LVDS outputs simplify timing and improve noise performance
To minimize system cost and power dissipation, the AD9480 includes an internal reference and track-and-hold circuit. The user only provides a 3.3 V power supply and a differential encode clock. No external reference or driver components are required for many applications. The digital outputs are LVDS (ANSI 644) compatible with an option of twos complement or binary output format. The output data bits are provided in parallel fashion along with an LVDS output clock, which simplifies data capture. Fabricated on an advanced BiCMOS process, the AD9480 is available in a 44-lead surface-mount package (TQFP) specified over the industrial temperature range −40°C to +85°C.
Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
AD9480 TABLE OF CONTENTS DC Specifications ............................................................................. 3
Interleaving Two AD9480s........................................................ 18
Digital Specifications........................................................................ 4
Data Clock Out........................................................................... 18
AC Specifications.............................................................................. 5
Power-Down ............................................................................... 18
Switching Specifications .................................................................. 6
AD9480 Evaluation Board ............................................................ 19
Timing Diagram ........................................................................... 6
Power Connector........................................................................ 19
Absolute Maximum Ratings............................................................ 7
Analog Inputs ............................................................................. 19
Explanation of Test Levels ........................................................... 7
Gain.............................................................................................. 19
ESD Caution.................................................................................. 7
Optional Operational Amplifier .............................................. 19
Pin Configuration and Function Descriptions............................. 8
Clock ............................................................................................ 19
Terminology ...................................................................................... 9
Optional Clock Buffer ............................................................... 19
Typical Performance Characteristics ........................................... 11
Optional XTAL ........................................................................... 19
Equivalent Circuits ......................................................................... 15
Voltage Reference ....................................................................... 20
Application Notes ........................................................................... 16
Data Outputs............................................................................... 20
Clocking the AD9480 ................................................................ 16
Evaluation Board Bill of Materials (BOM) ................................. 21
Analog Inputs.............................................................................. 16
PCB Schematics .............................................................................. 22
Voltage Reference ....................................................................... 17
PCB Layers ...................................................................................... 24
Digital Outputs ........................................................................... 18
Outline Dimensions ....................................................................... 26
Output Coding............................................................................ 18
Ordering Guide .......................................................................... 26
REVISION HISTORY 4/05—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Features.......................................................................... 1 Changes to Table 3............................................................................ 5 Changes to Table 7............................................................................ 8 Changes to Analog Inputs ............................................................. 16 Changes to Figure 30...................................................................... 16 Added Power Down Section ......................................................... 18 Changes to Table 12........................................................................ 21 7/04—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD9480 DC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error1 Differential Nonlinearity (DNL) AD9480BSUZ-250 AD9480ASUZ-250 Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference REFERENCE Internal Reference Voltage Output Current2 IVREF Input Current3 ISENSE Input Current2 ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range (FS = 1) 4 Common-Mode Voltage Input Resistance Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD Power Dissipation5 Power-Down Dissipation IAVDD5 IDRVDD5 Power Supply Rejection Ratio (PSRR)
Temp
Test Level
Min
Full 25°C 25°C
VI I I
−40 −6.0
Full Full Full
VI VI VI
−0.5 −0.85 −0.9
Full Full Full
V V V
Full 25°C 25°C 25°C
VI IV I I
Full Full 25°C Full 25°C 25°C
V VI I VI V V
Full Full 25°C 25°C Full Full 25°C
IV IV V V VI VI V
1
AD9480-250 Typ 8
Max
Unit Bits
+40 +6.0
mV % FS
+0.5 +0.85 +0.9
LSB LSB LSB
Guaranteed
±0.28 ±0.35 ±0.26 30 0.03 ±0.025
0.97
1.7 8.6 8.4
3.0 3.0
1.0
1 1.9 10 10 4 750 3.3 3.3 590 15 145 34 −4.2
µV/°C %FS/°C mV/°C 1.03 1.5 100 10
2.1 10.7 11.2
3.6 3.6
156 38
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and a 1 V p-p differential analog input). Internal reference mode; SENSE = AGND. 3 External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD. 4 In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other. 5 Power dissipation and current measured with rated encode and a dc analog input (outputs static). See Figure 13 for active operation. 2
Rev. A | Page 3 of 28
V mA µA µA V p-p V kΩ kΩ pF MHz V V mW mW mA mA mV/V
AD9480 DIGITAL SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 2. Parameter CLOCK INPUTS (CLK+, CLK−) Differential Input Common-Mode Voltage1 Input Resistance Input Capacitance LOGIC INPUTS (PDWN, S1) 2 PDWN Logic 1 Voltage PDWN Logic 0 Voltage PDWN Logic 1 Input Current PDWN Logic 0 input Current PDWN, S1 Input Resistance PDWN, S1 Input Capacitance DIGITAL OUTPUTS Differential Output Voltage (VOD)3 Output Offset Voltage (VOS) Output Coding
Temp
Test Level
Min
Full Full Full 25°C
IV VI VI V
200 1.4 4.2
Full Full Full Full 25°C 25°C
IV IV VI VI V V
2.0
Full Full Full
VI VI IV
247 1.125
1
The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V. S1 is a multilevel logic input, see Table 8. 3 LVDSBIAS resistor = 3.74 kΩ. 2
Rev. A | Page 4 of 28
AD9480-250 Typ Max
1.5 5.5 4
1.68 6.0
0.8 ±160 10 30 4 454 1.375 Twos complement or binary
Unit mV p-p V kΩ pF V V µA µA kΩ pF mV V
AD9480 AC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, AIN = –1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 3. Parameter SIGNAL-TO-NOISE RATIO (SNR) fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz WORST SECOND OR THIRD HARMONIC DISTORTION fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz WORST OTHER fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR)1 fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fIN1 = 69.3 MHz, fIN2 = 70.3 MHz 1
AD9480-250 Typ Max
Temp
Test Level
Min
25°C 25°C 25°C
V I I
45 45
47 47 46
dB dB dB
25°C 25°C 25°C
V I I
44.8 44.8
46.5 46.5 46.5
dB dB dB
25°C 25°C 25°C
V I I
7.3 7.3
7.6 7.6 7.6
Bits Bits Bits
25°C 25°C 25°C
V I I
−65 −65 −65
−60 −60
dBc dBc dBc
25°C 25°C 25°C
V I I
−70 −70 −70
−63 −63
dBc dBc dBc
25°C 25°C 25°C
V I I
−65 −65 −65
−60 −60
dBc dBc dBc
25°C
V
−68
Nyquist bin energy ignored.
Rev. A | Page 5 of 28
Unit
dBc
AD9480 SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, differential clock input, DCS enabled, unless otherwise noted. Table 4. Parameter CLOCK Maximum Conversion Rate Minimum Conversion Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS Valid Time (tV)1 Propagation Delay (tPD) Rise Time (tR) 20% to 80% Fall Time (tF) 20% to 80% DCO Propagation Delay (tCPD) Data-to-DCO Skew (tPD − tCPD) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) 1
Temp
Test Level
Min
Full Full Full Full
VI VI IV IV
250
Full Full Full Full Full Full 25°C
VI VI V V VI IV VI
25°C 25°C
V V
AD9480-250 Typ Max
Unit MSPS MSPS ns ns
20 1.2 1.2
2 2
1.9 2.8 0.5 0.5 2.7 0.1 8
1.9 0
ns ns ns ns ns ns Cycles
3.8
3.7 0.6
1.5 0.25
ns ps rms
Valid time is approximately equal to minimum tPD. CLOAD equals 5 pF maximum.
TIMING DIAGRAM N–1
tA
N+10
N+11
N N+9 AIN N+1
N+8
8 CYCLES
tEH
tEL
1/fS
CLK+ CLK–
tPD
tV
DATA N–8
OUT
N–7
N
N+1
N+2
tCPD 04619-002
DCO+ DCO–
Figure 2. Timing Diagram
Rev. A | Page 6 of 28
AD9480 ABSOLUTE MAXIMUM RATINGS Thermal impedance (θJA) = 46.4°C/W (4-layer PCB). Table 5. Parameter ELECTRICAL AVDD (With Respect to AGND) DRVDD (With Respect to DRGND) AGND (With Respect to DRGND) Digital I/O (With Respect to DRGND) Analog Inputs (With Respect to AGND) ENVIRONMENTAL Operating Temperature Junction Temperature Case Temperature Storage Temperature
Min Rating
Max Rating
−0.5 V
+4.0 V
−0.5 V
+4.0 V
−0.5 V
+0.5 V
−0.5 V
DRVDD + 0.5 V
−0.5 V
AVDD + 0.5 V
−40°C
85°C 150°C 150°C 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
EXPLANATION OF TEST LEVELS Table 6. Level I II III IV V VI
Descriptions 100% production tested. 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 7 of 28
AD9480
VREF
AGND
AVDD
AGND
VIN–
VIN+
AGND
AVDD
LVDSBIAS
NC
AGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
44 43 42 41 40 39 38 37 36 35 34
CLK+ 1 PIN 1
CLK– 2
33
SENSE
32
AGND
AVDD 3
31
AVDD
AGND 4
30
AGND
29
PDWN
28
S1
D0_C (LSB) 7
27
DRGND
D0_T (LSB) 8
26
D7_T (MSB)
D1_C 9
25
D7_C (MSB)
D1_T 10
24
D6_T
23
D6_C
AD9480
DRVDD 5
TOP VIEW (Not to Scale)
DRGND 6
D2_C 11
04619-003
D5_T
D5_C
D4_T
D4_C
DRVDD
DCO+
DCO–
DRGND
D3_T
D2_T
D3_C
NC = NO CONNECT
12 13 14 15 16 17 18 19 20 21 22
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6
Mnemonic CLK+ CLK− AVDD AGND DRVDD DRGND
Description Input Clock—True Input Clock—Complement 3.3 V Analog Supply Analog Ground 3.3 V Digital Output Supply Digital Ground
Pin No. 23 24 25 26 27 28
Mnemonic D6_C D6_T D7_C D7_T DRGND S1
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
D0_C D0_T D1_C D1_T D2_C D2_T D3_C D3_T DRGND DCO− DCO+ DRVDD D4_C D4_T D5_C D5_T
Data Output Bit 0—Complement (LSB) Data Output Bit 0—True (LSB) Data Output Bit 1—Complement Data Output Bit 1—True Data Output Bit 2—Complement Data Output Bit 2—True Data Output Bit 3—Complement Data Output Bit 3—True Digital Ground Data Clock Output—Complement Data Clock Output—True 3.3 V Digital Output Supply Data Output Bit 4—Complement Data Output Bit 4—True Data Output Bit 5—Complement Data Output Bit 5—True
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
PDWN AGND AVDD AGND SENSE VREF AGND AVDD AGND VIN− VIN+ AGND AVDD LVDSBIAS NC1 AGND
1
Description Data Output Bit 6—Complement Data Output Bit 6—True Data Output Bit 7—Complement (MSB) Data Output Bit 7—True (MSB) Digital Ground Data Format Select and Duty-Cycle Stabilizer Selection (See Table 8) Power-Down Selection (AVDD = Power Down) Analog Ground 3.3 V Analog Supply Analog Ground Reference Mode Selection (See Table 9) Voltage Reference Input/Output Analog Ground 3.3 V Analog Supply Analog Ground Analog Input—Complement Analog Input—True Analog Ground 3.3 V Analog Supply LVDS Output Current Adjust No Connect (Leave Floating) Analog Ground
Pin 43 will self-bias to 1.5 V. It can be left floating (as recommended) or tied to AVDD or ground with no ill effects.
Rev. A | Page 8 of 28
AD9480 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Full-Scale Input Power Expressed in dBm. Computed by ⎛ V 2 FULLSCALE rms ⎜ ⎜ Z INPUT PowerFULLSCALE = 10 log ⎜ 0.001 ⎜ ⎜ ⎝
Aperture Delay The delay between the 50% point of the rising edge of the encode command and the instant the analog input is sampled.
Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in a Logic 1 state to achieve rated performance; pulse width low is the minimum time that the clock pulse should be left in a low state. See the timing implications of changing tEH in the Clocking the AD9480 section. At a given clock rate, these specifications define an acceptable clock duty cycle.
Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit.
Crosstalk Coupling onto one channel being driven by a low level (−40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically, and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180° and taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits The effective number of bits (ENOB) is calculated by the measured SINAD based on (assuming full-scale input) ENOB =
SINAD MEASURED − 1.76 dB 6.02
⎞ ⎟ ⎟ ⎟ ⎟ ⎟ ⎠
Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK− and the time when all output data bits are within valid logic levels. Noise (For Any Range Within the ADC) This value includes both thermal and quantization noise. − SNRdBc − SignaldBFS ⎛ FS Vnoise = Z × .001× 10 ⎜⎜ dBm 10 ⎝
⎞ ⎟⎟ ⎠
where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SNR is the value for the particular input level. Signal is the signal level within the ADC reported in dB below full scale. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Rev. A | Page 9 of 28
AD9480 Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (that is, degrades as signal level is lowered) or dBFS (that is, always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product in dBc.
Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (that is, always relates back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in dBc. Transient Response Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
Rev. A | Page 10 of 28
AD9480 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, FS = 1, unless otherwise noted. 0
0 SNR = 46.2dB H2 = 72.8dBc H3 = 73.2dBc SFDR = 69.8dBc
–20 –30
–40
–40
dB
–30
–50
–50
–60
–60
–70
–70 04619-020
dB
–20
–80 –90 0
20
40
60 MHz
80
100
SNR = 45.9dB H2 = 71.9dBc H3 = 67dBc SFDR = 67dBc
–10
04619-023
–10
–80 –90
120
0
Figure 4. FFT: fS = 250 MSPS, AIN = 10.3 MHz @ −1 dBFS
20
40
60 MHz
80
100
120
Figure 7. FFT: fS = 250 MSPS, AIN = 170 MHz @ −1 dBFS 90
0 SNR = 46.1dB H2 = 71.4dBc H3 = 74.3dBc SFDR = 68.7dBc
–10 –20
85 H3 80 75
–30
dB
dB
70 –40
H2
SFDR
65
–50
60 –60
55
–70
–90 0
20
40
60 MHz
80
100
SNR
45
SINAD
40
120
0
Figure 5. FFT: fS = 250 MSPS, AIN = 70 MHz @ –1 dBFS
04619-024
04619-021
50
–80
50
100
150
200 250 AIN (MHz)
300
350
400
Figure 8. Analog Input Frequency Sweep, AIN = −1 dBFS, FS = 1 V, fS = 250 MSPS
0
80 SNR = 45.9dB H2 = 67dBc H3 = 73.3dBc SFDR = 67dBc
–10 –20
H3 75 H2 70
–30
SFDR dB
dB
65 –40
60
–50
55
–60
04619-022
–80 –90 0
20
40
60 MHz
80
100
120
Figure 6. FFT: fS = 250 MSPS, AIN = 70 MHz @ –1 dBFS, Single-Ended Input
Rev. A | Page 11 of 28
SNR
45
SINAD
40 0
50
100
150
200 250 AIN (MHz)
300
350
Figure 9. Analog Input Frequency Sweep, AIN = −1 dBFS, FS = 0.75 V, fS = 250 MSPS
04619-025
50
–70
400
AD9480 180
75
160
70
140
CURRENT IN mA
65 SFDR
dB
60
55
120 IAVDD 100 80 60
50
SINAD
40 0
50
100 150 200 SAMPLE CLOCK (MHz)
250
20 0 0
300
Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency, AIN = 70 MHz @ −1 dBFS
04619-029
04619-026
45
IDRVDD
40
SNR
50
100
150 200 ENCODE (MSPS)
250
300
Figure 13. IAVDD and IDRVDD vs. Clock Rate, CLOAD = 5 pF AIN = 70 MHz @ –1 dBFS 50
80
49
70 SFDRdBFS
48 DCS ON
60 47 46
dB
dB
50 40
45 44
30
DCS OFF
43
20 04619-027
–50 –40 –30 –20 –10 ANALOG INPUT DRIVE LEVEL (dBFS)
40 20
0
Figure 11. SFDR vs. AIN Input Level; AIN = 70 MHz @ 250 MSPS
40 50 60 70 CLOCK POSITIVE DUTY CYCLE (%)
80
50.0
F1, F2 = –7dBFS 2F2-F1 = –71.1dBc 2F1-F2 = –68dBc
–10
80
Figure 14. SNR, SINAD vs. Clock Pulse Width High, AIN = 70 MHz @ –1 dBFS, 250 MSPS, DCS On/Off
0
SNR
–20 SNR, SINAD dB
47.5
–30 –40 –50 –60
75 SINAD
70
45.0
SFDR 65
42.5
–70 04619-028
dB
30
–80 –90 0
20
40
60 MHz
80
100
120
Figure 12. Two-Tone Intermodulation Distortion (69.3 MHz and 70.3 MHz; fS = 250 MSPS)
40.0 0.5
0.7
0.9 1.1 1.3 1.5 1.7 EXTERNAL VREF VOLTAGE (V)
1.9
50
Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, AIN = 70 MHz @ –1 dBFS, 250 MSPS
Rev. A | Page 12 of 28
SFDR dB
–60
41
04619-031
0 –70
65dB REF LINE
046190-030
42
SFDRdBc 10
AD9480 3
70 FS = 1V EXT REF SFDR
65
1 60 FS = 1V INT REF
dB
0
55 –1 SNR
50 04619-032
–2
–3 –40
–20
0
20 40 TEMPERATURE (°C)
60
45 SINAD 3.0 3.1
80
Figure 16. Full-Scale Gain Error vs. Temperature, AIN = 70.3 MHz @ −0.5 dBFS, 250 MSPS, FS = 1
04619-035
GAIN ERROR (%)
2
3.2
3.3 AVDD (V)
3.4
3.5
3.6
Figure 19. SNR, SINAD, and SFDR vs. Supply Voltage, AIN = 70.3 MHz @ −1 dBFS, 250 MSPS 0.5
75 SFDR 1V INT REF
0.4 70
0.3 65
0.2 0.1
dB
LSB
60
55
0 –0.1 –0.2
50 SINAD 1V INT REF 04619-033
40 –40
–20
0
20 40 TEMPERATURE (°C)
60
04619-036
–0.3
45
–0.4 –0.5
80
0
50
100
150
200
250
CODE
Figure 17. SINAD, SFDR vs. Temperature, AIN = 70 MHz @ −1 dBFS, 250 MSPS
Figure 20. Typical DNL Plot, AIN = 10.3 MHz @ –0.5 dBFS, 250 MSPS
0.10
0.50
0.05
LSB
0
0
–0.05
–0.25
–0.15 2.7
2.8
2.9
3.0
3.1 3.2 AVDD (V)
3.3
3.4
3.5
3.6
04619-037
–0.10 04619-034
CHANGE IN VREF (%)
0.25
–0.50 0
50
100
150
200
250
CODE
Figure 18. VREF Sensitivity to AVDD
Figure 21. Typical INL Plot, AIN = 10.3 MHz @ −0.5 dBFS, 250 MSPS
Rev. A | Page 13 of 28
AD9480 0.30
900 800
0.25
1.3 VOS
700
1.2
600
1.1
500
1.0
0.10 0.05 0 –0.05 –0.10 –40
–20
0
20 40 TEMPERATURE (°C)
60
80
400
0.9 VOD
300
0.8
200
0.7
100
0.6
0
0.5 0
2
4
6
8
10
12
14
RSET (kΩ)
Figure 23. LVDS Output Swing, Common-Mode Voltage vs. RSET, Placed at LVDSBIAS
Figure 22. Propagation Delay Adder vs. Temperature
Rev. A | Page 14 of 28
04619-039
VDIF (mV)
0.15
VOS (V)
0.20
04619-038
DELAY SENSITIVITY (nS)
1.4
AD9480 EQUIVALENT CIRCUITS AVDD
AVDD
16.7kΩ
16.7kΩ
150Ω
150Ω VIN–
VIN+ 1.2pF
25kΩ
PDWN
1.2pF
30kΩ 04619-007
04619-004
25kΩ
Figure 24. Analog Inputs Figure 27. Power-Down Input DRVDD
AVDD
DRVDD
12kΩ
12kΩ
K
1.2V CLK+
CLK– 150Ω
150Ω
ILVDSOUT
10kΩ
3.7kΩ
04619-005
10kΩ
04619-008
LVDSBIAS
Figure 28. LVDSBIAS Input
Figure 25. Clock Inputs DRVDD
VDD
30kΩ
V+
V–
DX–
DX+
V–
V+
04619-009
04619-006
S1
Figure 26. S1 Input Figure 29. LVDS Data, DCO Outputs
Rev. A | Page 15 of 28
AD9480 APPLICATION NOTES
Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Considerable care has been taken in the design of the CLOCK input of the AD9480, and the user is advised to give commensurate thought to the clock source. The AD9480 has an internal clock duty-cycle stabilization circuit that locks to the rising edge of CLOCK and optimizes timing internally for sample rates between 100 MSPS and 250 MSPS. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter on the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty-cycle control loop does not function for clock rates less than 70 MHz nominally. The loop is associated with a time constant that needs to be considered in applications where the clock rate can change dynamically, requiring a wait time of 5 µs after a dynamic clock frequency increase before valid data is available. The clock duty-cycle stabilizer can be disabled at Pin 28 (S1). The clock inputs are internally biased to 1.5 V (nominal) and support either differential or single-ended signals. For best dynamic performance, a differential signal is recommended. An MC100LVEL16 performs well in the circuit to drive the clock inputs (ac coupling is optional). If the clock buffer is greater than 2 inches from the ADC, a standard LVPECL termination may be required instead of the simple pull-down termination, as shown in Figure 30.
The analog input to the AD9480 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN− should match. Optimal performance is obtained when the analog inputs are driven differentially. SNR and SINAD performance can degrade if the analog input is driven with a single-ended signal; however, performance can be adequate for some applications (see Figure 6). The analog inputs self-bias to approximately 1.9 V; this common-mode voltage can be externally overdriven by approximately ±300 mV if required. A wideband transformer, such as the Mini-Circuits® ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Note that the filter and center-tap capacitor on the secondary side is optional and dependent on application requirements. An RC filter at the secondary side helps reduce any wideband noise aliased by the ADC. (R, C OPTIONAL) VIN+ 49.9Ω
10pF
AD9480
33Ω
VIN– AGND
0.1µF
Figure 31. Driving the ADC with an RF Transformer
For dc-coupled applications, the AD8138/AD8139 or AD8351 can serve as a convenient ADC driver, depending on requirements. Figure 32 shows an example with the AD8138. The AD9480 PCB has an optional AD8351 on board, as shown in Figure 41 and Figure 42. The AD8351 typically yields better performance for frequencies greater than 30 MHz to 40 MHz.
49.9Ω 499Ω
AD9480
VIN+
AD8138
1.3kΩ
CLK+
20pF 33Ω
523Ω
PECL GATE
0.1µF
CLK–
2kΩ
AVDD
33Ω
499Ω
0.1µF
AVDD
33Ω
AD9480 VIN–
499Ω
510Ω
04619-010
0.1µF 510Ω
Figure 32. Driving the ADC with the AD8138
Figure 30. Clocking the AD9480
Table 8. S1 Voltage Levels S1 Voltage 0.9 × AVDD −> AVDD 2/3 AVDD ± (0.1 × AVDD) 1/3 AVDD ± (0.1 × AVDD) AGND −> (0.1 × AVDD)
Data Format Offset binary Offset binary Twos complement Twos complement
Rev. A | Page 16 of 28
Duty-Cycle Stabilizer Disabled Enabled Enabled Disabled
AGND
04619-012
CLOCKING THE AD9480
ANALOG INPUTS
04619-011
The AD9480 uses a 1.5-bit per stage architecture. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 8-bit core. For ease of use, the part includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are LVDS (ANSI 644 compatible).
AD9480 The AD9480 can be easily configured for different full-scale ranges. See the Voltage Reference section for more information. Optimal performance is achieved with a 1 V p-p analog input. SENSE = GND
VIN+
500mV 2.0V
Fixed Reference The internal reference can be configured for a differential span of 1 V p-p (see Figure 37). It is recommended to place a 0.1 µF capacitor as close as possible to the VREF pin; a 10 µF capacitor is also required (see the PCB layout for guidance). If the internal reference of the AD9480 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 37 depicts how the internal reference voltage is affected by loading.
2.0V
1.0085 1.0080
VIN–
1.0075
DIGITALOUT = ALL 0s
VOLTAGE REFERENCE A stable and accurate 1.0 V reference is built into the AD9480. Users can choose this internal reference or provide an external reference for greater accuracy and flexibility. Figure 35 shows the typical reference variation with temperature. Table 9 summarizes the available reference configurations.
1.0065 1.0060 1.0055 1.0050 1.0045 04619-049
Figure 33. Analog Input Full Scale
1.0070 VREF (V)
04619-013
DIGITALOUT = ALL 1s
1.0040 1.0035 –40
–20
0
20 40 TEMPERATURE (°C)
60
80
Figure 35. Typical Reference Variation with Temperature
VIN+ VIN–
VREF 10µF
0.1µF
ADC CORE
04619-016
SENSE
Figure 36. Internal Fixed Reference (1 V p-p) VREF 0.1µF 7kΩ
SELECT LOGIC
SENSE
0.5V 04619-014
7kΩ
–0.1
–0.2
–0.3
–0.4 04619-017
+
% CHANGE IN VREF VOLTAGE
10µF
0
Figure 34. Internal Reference Equivalent Circuit –0.5 0
0.5
1.0
1.5 IREF (mA)
2.0
2.5
3.0
Figure 37. Internal VREF vs. Load Current
Table 9. Reference Configurations SENSE Voltage AVDD 0.5 V (Self-Biased) AGND to 0.2 V
Resulting VREF N/A (External Reference Input) 0.5 × (1 + R1/R2) V 1.0 V
Reference External Programmable Internal Fixed
Rev. A | Page 17 of 28
Differential Span 1 × External Reference Voltage 1 × VREF (0.75 V p-p to 1.5 V p-p) 1 V p-p
AD9480 External Reference An external reference can be used for greater accuracy and temperature stability when required. The gain of the AD9480 can also be varied using this configuration. A voltage output DAC can be used to set VREF, providing for a means to digitally adjust the full-scale voltage. VREF can be externally set to voltages from 0.75 V to 1.5 V; optimum performance is typically obtained at VREF = 1 V. (See the Typical Performance Characteristics section.) MAY REQUIRE RC FILTER EXTERNAL REFERENCE OR DAC INPUT
VREF
AVDD 04619-018
SENSE
Figure 38. External Reference
Programmable Reference The programmable reference can be used to set a differential input span anywhere between 0.75 V p-p and 1.5 V p-p by using an external resistor divider. The sense pin will self-bias to 0.5 V, and the resulting VREF is equal to 0.5 × (1 + R1/R2). It is recommended to keep the sum of R1 + R2 ≥ 10 kΩ to limit VREF loading (for VREF = 1.5 V, set R1 equal to 7 kΩ and R2 equal to 3.5 kΩ).
VREF 0.1µF
R1
SENSE R2
04619-019
10µF
trace length 3 inches to 4 inches maximum and the differential output trace lengths as equal as possible.
OUTPUT CODING Table 10. Code 255 255 254 • • 129 128 127 • • 2 1 0 0
(VIN+) − (VIN−) >+0.512 V +0.512 V +0.508 V • • +0.004 V +0.0 V –0.004 V • • −0.504 V −0.508 V −0.512 V <−0.512 V
Offset Binary 1111 1111 1111 1111 1111 1110 • • 1000 0001 1000 0000 0111 1111 • • 0000 0010 0000 0001 0000 0000 0000 0000
Twos Complement 0111 1111 0111 1111 0111 1110 • • 0000 0001 0000 0000 1111 1111 • • 1000 0010 1000 0001 1000 0000 1000 0000
INTERLEAVING TWO AD9480s Instrumentation applications may prefer to interleave or pingpong two AD9480s to achieve twice the sample rate, or 500 MSPS. In these applications, it is important to match the gain and offset of the two ADCs. Varying the reference voltage allows the gain of the ADCs to be adjusted; external dc offset compensation can be used to reduce offset mismatch between two ADCs. The sampling phase offset between the two ADCs is extremely important as well and requires very low skew between clock signals driving the ADCs (<2 ps clock skew for a 100 MHz analog input frequency).
DATA CLOCK OUT
Figure 39. Programmable Reference
DIGITAL OUTPUTS LVDS outputs are available when a 3.7 kΩ RSET resistor is placed at Pin 42 (LVDSBIAS) to ground. The RSET resistor current (~1.2 V/RSET) is ratioed on-chip, setting the output current at each output equal to a nominal 3.5 mA with an RSET of 3.74 kΩ. Varying the RSET current also linearly changes the LVDS output current, resulting in a variable output swing for a fixed termination resistance. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor as close to the receiver as possible. Keep the
An LVDS data clock is available at DCO+ and DCO−. These clocks can facilitate latching off-chip, providing a low skew clocking solution. The on-chip delay of the DCO clocks tracks with the on-chip delay of the data bits (under similar loading), such that the variation between TPD and TCPD is minimized. It is recommended to keep the trace lengths on the data and DCO pins matched and to 3 inches to 4 inches maximum. The output and DCO outputs should be designed for a differential characteristic impedance of 100 Ω and terminated differentially at the receiver with 100 Ω.
POWER-DOWN The chip can be placed in a low power state by driving the PDWN pin to logic high. Typical power-down dissipation is 15 mW. The data outputs and DCO outputs are high impedance in power-down state. The time it takes to go into power-down from assertion of PDWN is one cycle; recovery from powerdown is accomplished in three cycles.
Rev. A | Page 18 of 28
AD9480 AD9480 EVALUATION BOARD The AD9480 evaluation board offers an easy way to test the device. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC and a data-ready signal. The digital outputs and output clocks are available at a 40-pin connector, P10. The board has several modes of operation and is shipped in the following configuration: • Offset binary • Internal voltage reference
POWER CONNECTOR
Table 11. Power Connector
2
The clock input is terminated to ground through 50 Ω at SMA Connector J1. The input is ac-coupled to a high speed differential receiver (LVEL16) that provides the required low jitter and fast edge rates needed for best performance. J1 input should be >0.5 V p-p. Power to the LVEL16 is set to VCTRL (default) or AVDD by jumper placement at the device.
Comments Analog supply for ADC ~ 150 mA Output supply for ADC ~ 40 mA Supply for support clock circuitry ~ 50 mA Optional supply for op amp and ADR510 reference
AVDD, DRVDD, and VCTRL are the minimum required power connections. LVEL16 clock buffer can be powered from AVDD or VCTRL LVEL16 buffer jumper.
ANALOG INPUTS The evaluation board accepts a 700 mV p-p analog input signal centered at ground at SMB Connector J3. This signal is terminated to ground through 50 Ω by R22. The input can be alternatively terminated at the T1 transformer secondary by R21 and R28. T1 is a wideband RF transformer that provides the single-ended-to-differential conversion, allows the ADC to be driven differentially, and minimizes even-order harmonics. An optional transformer, T4, can be placed, if desired (remove T1, as shown in Figure 41 and Figure 42).
The PCB has been designed to accommodate the SNLVDS1 line driver. The SNLVDS1 is used as a high speed LVDS-level optional encode clock. To use this clock, remove C2, C5, and C6. Place a 0.1 µF capacitor on C34, C35, and C26. Place a 10 Ω resistor on R48, a 100 Ω resistor on R6, and a 0 Ω resistor on R49 and R53. For best results using the LVDS line driver, J1 input should be >2.5 V p-p.
OPTIONAL XTAL The PCB has been designed to accommodate an optional crystal oscillator that can serve as a convenient clock source. The footprint can accept both through-hole and surface-mount devices, including Vectron XO-400 and Vectron VCC6 family oscillators.
OUT+
VCC
The analog signal can be low-pass filtered by R31, C8, and R29, C9 at the ADC input.
OUT–
GAIN
GND
Full scale is set by the sense jumper. This jumper applies a bias to the SENSE pin to vary the full-scale range; the default position is SENSE = ground, setting the full scale to 1 V p-p.
VCC
04619-040
1
CLOCK
OPTIONAL CLOCK BUFFER
Power is supplied to the board via two detachable 4-pin power strips. Terminal AVDD1 3.3 V DRVDD1 3.3 V VCTRL1, 2 3.3 V Op Amp, External Reference
with a 1.2 kΩ resistor and R42 with a 100 Ω resistor. Populate R52 with a 10 kΩ resistor.
Figure 40. XTAL Footprint
OPTIONAL OPERATIONAL AMPLIFIER The PCB has been designed to accommodate an optional AD8351 op amp, which can serve as a convenient solution for dc-coupled applications. To use the AD8351 op amp, remove R29, R31, and C3. Populate R40, R43, and R47 with 25 Ω resistors, and populate C24, C28, C29, C30, C31, and C32 with 0.1 µF capacitors. Populate R38, R39, and R51 with a 10 Ω resistor, and R44 and R45 with a 1 kΩ resistor. Populate R41
To use either crystal, populate C26 and C27 with 0.1 µF capacitors. Populate R49 and R53 with 0 Ω resistors. Place 1 kΩ resistors on R54, R55, R56, and R57 and remove C6 and C5. If the Vectron VCC6 family crystal is being used, populate R48 with a 10 Ω resistor. If using the XO-400 crystal, place Jumper E21 or Jumper E22 to Jumper E23.
Rev. A | Page 19 of 28
AD9480 VOLTAGE REFERENCE
DATA OUTPUTS
The AD9480 has an internal 1 V reference mode. The ADC uses the internal 1 V reference as the default when SENSE is set to ground. An optional on-board external 1.0 V reference (ADR510) can be used by setting the SENSE jumper to AVDD, by placing a jumper on E20 to E3, and by placing a 0 Ω resistor on R36. When using an external programmable reference (R20, R30), the SENSE jumper must be removed.
The off-chip drivers provide LVDS-compatible output levels with an LVDS RSET resistor of 3.74 kΩ. The ADC digital outputs can be terminated on the board by 100 Ω resistors at the connector if receiving logic does not have the required termination resistance. (The on-chip LVDS output drivers require a far-end, 100 Ω differential termination.)
Rev. A | Page 20 of 28
AD9480 EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. No. 1
Quantity 23
2 3 4 5 6 7 8
1 4 2 2 2 2 10
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
6 1 3 3 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 7
29
12
30
18
31
1
Reference Designator C1 to C6, C10 to C12, C17 to C23, C26 to C28, C31 to C33, C35 C13 C7, C14 to C16 J1, J3 P12, P13 P12, P13 R22, R27 R2 to R5, R7 to R10, R15, R42 (All not placed) R1, R44, R45, R50, R58, R59 R41 R40, R43, R47 R38, R39, R51 R25, R26 R23, R24 R32, R34 R29, R31 R33, R52 R63 T1 U13 U2 U14 U15 U1 U12 U11 T2 C8, C9, C24, C25, C29, C30, and C34 (All not placed) R6, R20, R21, R28, R30, R36, R46, R48, R49, and R55 to R57 (All not placed) E5 to E8, E17, E35, E73 to E84 P10
Device Capacitors
Package 0402
Value 0.1 µF
Capacitor Capacitors SMAs 4-pin power connector posts 4-pin power detachable connectors Resistors Resistors
Tantalum (3528) Tantalum (6032)
10 µF 10 µF
Z5.531.3425.0 25.602.5453.0 0603 0603
Wieland Wieland 50 Ω 100 Ω
Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistor Transformer AD8351 SN65LVDS1 ADR510 VCC6PECL6 XO-400 AD9480 MC100LVEL16D ETC1-1-13 Capacitors
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 CD542 MSOP-10 SN65LVDS1 DBV SOT-23 VCC6-QAB-250M000 Dip4(14) TQFP-44 S08NB 1-1 TX 0402
1000 Ω 1200 Ω 25 Ω 10 Ω 82 Ω 510 Ω 130 Ω 0Ω 10 kΩ 3.74 kΩ Mini-Circuits T1-1WT
Not placed Not placed
Resistors
0603
User-determined
40-pin right angle
Digi-Key S2131-20-ND
Not placed Not placed Not placed Not placed
Jumpers Output Data Connector
Rev. A | Page 21 of 28
CM
Rev. A | Page 22 of 28
Figure 41. PCB Schematic (1 of 2)
GND
VCTRL
AVDD
R27 R23 50Ω 510Ω
C11 0.1µF
CLKINPUT
GND
4
5
6
C10 0.1µF
CM
3
4
E8
2
5
AMPIN
GND
J1
CLK
ANALOG INPUT
R22 50 J3
GND
GND
1
6
3
3
2
8
C11 0.1µF
R21 X
C4 0.1µF GND
5
6
U11
CLKN Q VBB VEE
100LVEL16
R VCC 7 CLK Q
1
R24 4 510Ω
E11
E10
T1+
R28 X
GND
GND
R63 GND 3.7kΩ AVDD GND
GND AVDD GND
GND
R25 130Ω
R32 82Ω C5 0.1µF
C6 0.1µF
E17
E17
44
43
42
41
40
39
38
37
36
35
34
R6 X
GND AVDD GND PWDN S1 33 32 31 30 29 28 27 26 25 24 23
VREF AGND AVDD AGND VIN– VIN+ AGND AVDD LVDSBIAS NC AGND
1
CLK+
U12
FOR OP AMP CONFIGURATION REMOVE RESISTORS R29, R31, AND C3
C9 X
C12 0.1µF GND
R34 82Ω VCTRL
GND
R26 130Ω
E7
AMPOUT
GND
E17
R30 XX
R20 XX
C13 + 10µF
VCTRL GND
R29 00
GND
R31 00
C8 X
C10 0.1µF
AMPOUT
GND
T1– 2 CM
1
E9
T1–
CM
T1+
E1
E16
FOR ON BOARD EXT. REF JUMPER E13 TO 14 AND E20 TO E3 PLACE R36 0Ω AND R33 10kΩ
AD9480
D4C DRVDD DCO+ DCO– DRGND D3T D3C D2T
P7
E35
P6
2
3
4
5 6
CLK–
C33 0.1µF
7
8
GND
DRVDD
GND
CLKN
CLK P16
P14
D–
D+
AVDD AVDD GND VCTRL
P17
P15
PADS FOR SHORTING EL16,
9 10 11
12
13
14
15
16
17
19 18
D5T 22 21 D5C D4T 20
GND VAMP GND DRVDD GND AVDD GND
TIN1
VCTRL
R36 1kΩ OPTIONAL
E2
E15
GND
VCTRL
04619-041
GND
C1 0.1µF
GND
VCTRL
E14
4
R36 X
E13
3
3
U14
ADR510
TRIM/NC 2
GND
V+ V– 1
OPTIONAL TRANSFORMER
E3
1 2
4
E20
R33 10kΩ
3
VAMP
EXTVREF
GND
POWER CONN.
2
CLK+ CLK– AVDD AGND DRVDD DRGND D0C D0T D1C D1T D2C
1
AVDD GND DRVDD GND
P1 P2 P3 P4 P1 P2 P3 P4 SENSE AGND AVDD AGND PWDN S1 DRGND D7T D7C D6T D6C
P13 P12 PTMICRO4 PTMICRO4
D0C
D0T
D1C
D1T
D2C
D2T
D3C
D3T
DR–
DR+
D4C
D4T
D5C
D5T
D6C
D6T
D7C
D7T
E4 E70 E12 E32
GND GND GND GND GND GND GND GND
E77 E78 E79 E81 E80 E82 E83 E84
PROBE POINTS
R8 100Ω
R9 100Ω
R10 100Ω
R7 100Ω
R15 100Ω
R5 100Ω
R4 100Ω
R3 100Ω
R2 100Ω
GND
GND DR+ GND D7C D6C D5C D4C D3C D2C D1C D0C
4 2
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2
C40MS P10
P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1
1
3
5
7
9
11
13
15
17
19
21
23
25
29 27
31
33
35
37
39
OUTPUT DATA CONN.
GND
GND DR– GND D7T D6T D5T D4T D3T D2T D1T D0T
AD9480
PCB SCHEMATICS
Figure 42. PCB Schematic (2 of 2)
Rev. A | Page 23 of 28
04619-042
E25
C31 X
C30 X
R42 X
R51 X
R39 X
R52 X
VAMPF
E31
E29
E34
E28
OUT+
4
3
R41 X
U13 AD8351
OPTIONAL
RPG2 5
INLO
INHI
GND
AVDD
S1
PWUP 1 RGP1 2
X
C34
PWDN
CLKINPUT
GND
R40 X
AMPIN
GND
E30
E27
R58 1kΩ
R50 1kΩ
E36
E26
E24
R59 1kΩ
VCTRL
VCTRL
3
2
1
U2
Y
D
VPOS OPHI
6
COMM
OPLO
VOCM
9 8
VAMPF
10
7
4
5
OUT+ VIVIS
GND
C16 + 10µF
P4 P3VAMP
GND
VAMPF
R44 X
R45 X
C28 0.1µF
C29 X
R46 X
C24 X
GND
GND
AMPOUT
C25 X
AMPOUT
X
R38
X= NOT NORMALLY POPULATED XX = USER SELECTED, IS NOT NORMALLY POPULATED
SN65LVDS1 OPTIONAL
Z
GND
VCC
C32 0.1µF
VCTRL
AVDD
VAMPF
VCTRL
E21
E23
E22
R48 X
C23 X
GND
C27 X
GND
GND
C14 + 10µF
DRVDD
GND
C7 + 10µF
AVDD
GND
1 2 3
GND
C21 0.1µF
C17 0.1µF
OUT VEE –OUT
VCC
U1 XO-400
VCC 6 PECL6
7
14
GND
OUT+
6 OUT– 5 4
1
8
VCTRL
R54 X
R55 X
VCTRL
C20 0.1µF
C15 + 10µF
VCTRL
C19 0.1µF
OPTIONAL XTALS
C22 0.1µF
C18 0.1µF
GND
R57 X
R56X
GND
C23 0.1µF
C35 0.1µF
R53 X
R49 X CLK– CLK+
AD9480
AD9480
04619-043
04619-045
PCB LAYERS
04619-044
04619-046
Figure 45. PCB Ground Layer
Figure 43. PCB Top-Side Silkscreen
Figure 46. PCB Split Power Plane
Figure 44. PCB Top-Side Copper Routing
Rev. A | Page 24 of 28
04619-047
04619-048
AD9480
Figure 48. PCB Bottom-Side Silkscreen
Figure 47. PCB Bottom-Side Copper Routing
Rev. A | Page 25 of 28
AD9480 OUTLINE DIMENSIONS 1.20 MAX 0.75 0.60 0.45
12.00 BSC SQ 34
44 1
33 PIN 1
TOP VIEW
10.00 BSC SQ
(PINS DOWN)
0° MIN
1.05 1.00 0.95
0.15 0.05
0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY
SEATING PLANE
23
11 12
VIEW A
VIEW A
22
0.80 BSC LEAD PITCH
ROTATED 90° CCW
0.45 0.37 0.30
COMPLIANT TO JEDEC STANDARDS MS-026ACB
Figure 49. 44-Lead Thin Plastic Quad Flat Package [TQFP] (SU-44) Dimensions shown in millimeters
ORDERING GUIDE Model AD9480BSUZ-2501, 2 AD9480ASUZ-2501 AD9480-LVDS/PCB3
Temperature Range
−40°C to +85°C −40°C to +85°C
Description 44-Lead Thin Plastic Quad Flat Package (TQFP) 44-Lead Thin Plastic Quad Flat Package (TQFP) Evaluation Board
1
Z = Pb-free part. Optimized differential nonlinearity. 3 Evaluation board shipped with AD9480BSUZ-250 installed. 2
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Package Option SU-44 SU-44
AD9480 NOTES
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AD9480 NOTES
©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04619–0–4/05(A)
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