A Cmos 110-db@40ks/s Sd Modulator With - Imse-cnm

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A CMOS 110-dB@40KS/s SD Modulator with embedded Design-for-Testability strategies for automotive ASICs DOLPHIN TAMES-2-IST-2001-34283 Workshop on the testing of high-resolution mixed-signal interfaces INTEGRATION Instituto de Microelectrónica de Sevilla Centro Nacional de Microelectrónica IMSE-CNM, CSIC (www.imse.cnm.es) TAMES-2 First Workshop 1 OUTLINE o Design and Design for Test (DfT) • Description of testchip contents • Chip packages • PCB and test set-up DOLPHIN • Experimental measurements INTEGRATION o Test • New test techniques: FFT-INL and Wavelet o Final conclusions TAMES-2 First Workshop 2 OUTLINE o Design and Design for Test (DfT) • Description of testchip contents • Chip packages • PCB and test set-up DOLPHIN • Experimental measurements INTEGRATION o Test • New test techniques: FFT-INL and Wavelet o Final conclusions TAMES-2 First Workshop 3 Test Techniques in Sensor IF: Automotive sensor IF Specifications Resolution: DR = 17bit SNR-peak > 100dB Digital output rate: 40kS/s Signal bandwidth: Bw = 20kHz Signal range: 140dBV (Vref= 2V) Temperature range: (- 40,175)ºC Minimum power consumption Tech.: 3.3V-0.35µm CMOS (I3T80) DOLPHIN INTEGRATION Testchip description AUTOMOTIVE SENSOR INTERFACE ASIC Control Interface Control Functions Digital Interface Bias/ Configure Sensor Signal Conditioning ADC Digital Signal Processing Analog Interface DAC Digital Control Feedback Analog Control Feedback Block diagram Vexc x10 + Preamp - + Transducer TAMES-2 First Workshop x0.5,1,2,4 Σ∆ Modulator Decimation & Digital Signal Processing Control Signals 4 Test Techniques in Sensor IF: Testchip description Programmable-gain chopper-stabilized SC 2-1 cascade Σ∆ Modulator in g1 OPA g2 - g' OPB Y ,Y 1 1 H1 (z) - g' 2 1 ξ se l DAC g3 - g' 3 - g '' 3 OPB Y ,Y 2 2 2 DAC + H2 (z) + out g1 = ξ ⋅ g 1' g1 ' = 0.25 g2 = 1 g2 ' = 0.5 g3 = 1 g3 ' = g3'' = 0.5 –1 H1 ( z ) = z –1 2 H2 ( z ) = ( 1 – z ) Ca ncel lation L ogi c INTEGRATION Linearity > 17bit Signal range: 120dBV Sampling rate: 5.12MHz Power consumption: 14.7mW TAMES-2 First Workshop 0 GAIN = 1 GAIN = 2 -20 Power Spectral Density (dB/Hz) DOLPHIN Electrical performance summary (Post-layout simulation - HSPICE) DR = 17bit SNDR-peak > 100dB (all gains) -40 -60 -80 -100 -120 -140 8192-point FFT -160 -180 103 104 105 Frequency (Hz) 106 5 Test Techniques in Sensor IF: Testchip description Chopper-stabilized fixed-gain (x10) low-noise preamplifier φ1ch g7 − d1 φ1ch φ2ch φ2ch + + vin φ1dch φ 2dch φ1ch φ2ch φ2ch φ1ch INTEGRATION Instrumentation amp. configuration Four-stage opamps Hybrid Nested-Miller compensation Poly+ (nonsalicided) resistors M-i-M capacitors Switchable output current Programmable chopper frequency vout C R1 C − + φ2dch R2 R2 DOLPHIN o ut φ1dch − d1 + g7 − o ut Electrical performance summary Gain: 19.99dB Bandwidth: 995.7kHz SNR (worst case): 99.3 dB THD (worst case): −100dB Power consumption: 36-48mW TAMES-2 First Workshop M4 M3 M7 M9 M11 d1 g7 Cc1 Rc2 Cc2 Ib v- M2 M1 Rc3 Cc3 out v+ Rc1 M5 M6 M8 M10 6 Test Techniques in Sensor IF: Testchip description Building blocks required to implement on-chip DfT techniques Analog buffers For the observability of integrator outputs Performance summary: DC Gain: -0.03dB GB: 30.2MHz Power consumption: 0.3mW M13 M3 M4 M1 M2 vo + vo - v+ M8 M5 M6 INTEGRATION M9 M12 TAMES-2 First Workshop M14 M16 B For the test of the Comparators First and second integrators are settled to buffer mode Electrical performance: DC-Gain: 70dB GB: 13.8MHz PM: 85.1º SR: 20.2V/µs OS: ±2.5V Power cons.: 7.8mW Ib M7 A SW-opamps DOLPHIN M15 M11 M10 v- M17 M M M 13 M 3 17 4 M M M 2 1 M M 2 1 vt+ v- M M1 2 5 M 5 M 5 Ib v+ M8 v+ vo o M M 12 9 M 15 11 10 vt- M M M 6 M A M 14 7 M B 7 16 Test Techniques in Sensor IF: Testchip description Building blocks required to implement on-chip DfT techniques Delay SC stage Additional switches For the reconfiguration of the Σ∆M as a 2nd-order single-loop architecture SC-amplifier configuration g1 vi −g ' 1 gain=1 delay DOLPHIN INTEGRATION oi1 Y1, Y 1 g2 −g ' 2 − Unused blocks DAC 2nd-order Σ∆ Modulator g3 Tin = nTs g3' − g '' 3 DAC TAMES-2 First Workshop out 8 Test Techniques in Sensor IF: Testchip description State-of-the-Art Sigma-Delta Modulators TAMES-2 Sensor IF (prog. gain&preamp) 1,E+05 1,E+04 Σ∆M (gain x1) FOM 1,E+03 Single Loop - Single-bit 1,E+02 Single Loop - Multi-bit 1,E+01 Cascade - Single-bit 1,E+00 DOLPHIN INTEGRATION 1,E-01 1,E-02 1,E+00 Cascade - Multi-bit 1,E+02 1,E+04 DOR (S/s) 1,E+06 1,E+08 2kT ⋅ 3 ⋅ 22⋅ENOB ( bit ) ⋅ DOR(S/s) FOM = Power(W) TAMES-2 First Workshop 9 Test Techniques in Sensor IF: Testchip description Two testchips have been designed and sent for fabrication One chip including only the Σ∆ modulator (December, 2003) One One chip chip including including the the Σ∆ Σ∆M M& & DfT DfT strategies strategies (June, (June, 2003) 2003) DOLPHIN INTEGRATION TAMES-2 First Workshop 10 Test Techniques in Sensor IF: Testchip description Two testchips have been designed and sent for fabrication One One chip chip including including only only the the Σ∆ Σ∆ modulator modulator (June, (June, 2003) 2003) One chip including the Σ∆M & DfT strategies (December, 2003) DOLPHIN INTEGRATION TAMES-2 First Workshop 11 Test Techniques in Sensor IF: Testchip description Layout Floorplanning INT3 INT2 INT1 VDDAD VDDAD VSSAD INT3 SWTS LATCH INT2 SWITS INT1 SWITCHES VSSAD PROG. CAPS ANALOG INT3. CAPS SECTION INT2. CAPS OPB OPB INT3. CAPS INT2. CAPS OPA OPAMPs PROG. CAPS Vrefn Vrefp cm COMP PREAMP FB. CAPS FB. RES MIXED-SIGNAL SECTION Vrefn Vrefp cm COMP PREAMP MASTERBIAS INTEGRATION VDDDD VSSDD PREAMP PGLOGIC DOLPHIN DIGITAL SECTION (CLOCK, CHOPPER & BUFFERS) VDDDD COMMON SUBSTRATE (VSS_ref) TAMES-2 First Workshop INT2 SWTS INT1 SWITCHES VSSAA FB. CAPS VDDAA VSSAA VSSDD INT3 SWTS LATCH VDDAA SIGNALS VDDAA VSSAA BIAS CURRENTS Noiso Area P GuardRing N GuardRing 12 Test Techniques in Sensor IF: Chip Package Bonding package 64-pin plastic quad flat pack Double-bonding and multiple pins for supplies Different pin assignment for analog, mixed and digital DOLPHIN INTEGRATION TAMES-2 First Workshop 13 Test Techniques in Sensor IF: PCB and Test Set-up Conceptual diagram of the PCB MIXED-SIGNAL GROUND MS Supply DIGITAL GROUND ANALOG GROUND 100u 47u 47u Static Control Signals Ground Digital Supply 100u 47u 100u Static Control Signals 47u 100u 47u DOLPHIN INTEGRATION Preamp. Chop. Program. CLOCK 51 Σ∆M Chopper Program. INSDM- INSDM+ Vopreamp+ Psel VSSAA VSSDD Vref+ PEN_CH Digital Outputs Vopreamp- insel Pseln VDDAA PEN_CH_PREAMP SENSOR IF TESTCHIP VOFF+ IN+ INVOFF- POm1 PPDn POm2 Pfch_sel_MSB 620 PPD CLKIN Pfch_sel_LSB 100u VSSAA VDDDD Pfch_sel_LSB_PREAMP Analog Supply VDDAA VSSDD Pfch_sel_MSB_PREAMP Preamp. Chop. Enable Σ∆M Chop. Enable 220 220 PGain_sel_LSB VDDDD PGain_sel_MSB VDDAD VSSAD VSSAD VSS 100u VDDAD 47u 3.98n 1u Reference Voltage 3.98n 1u Reference Voltage 3.98n 1u Analog 470p Inputs 620 Vcm Pextres VrefBIASPREAMP 4.18k 15.49k Bias I=110uA I=145uA TAMES-2 First Workshop 14 Test Techniques in Sensor IF: PCB and Test Set-up DOLPHIN INTEGRATION TAMES-2 First Workshop 15 Test Techniques in Sensor IF: PCB and Test Set-up Precision Voltmeter Spectrum analyser “Clean” environment Precision differential signal generator Digital data acquisition system DOLPHIN INTEGRATION Signal Reference PCB Supply system Control, Data Data processing software, MATLAB or similar TAMES-2 First Workshop 16 Test Techniques in Sensor IF: New testchip – Meas. Testchip received in March 2004 Preliminary experimental measurements: Σ∆ modulator Correct noise-shaping for all cases of the modulator gain Experimental performance close to HSPICE predictions (specs.) DOLPHIN INTEGRATION TAMES-2 First Workshop 17 Test Techniques in Sensor IF: New testchip – Meas. Preliminary experimental measurements: Σ∆ modulator Output spectrum after decimation (gains x1 and x2): DR=110dB Measured In-band Output Spectrum -20 Gain x2 Gain x1 -40 DOLPHIN INTEGRATION Power Spectral Density (dB/Hz) -60 -80 -100 -120 -140 -160 0 TAMES-2 First Workshop 0.2 0.4 0.6 0.8 1 1.2 Frequency (Hz) 1.4 1.6 1.8 2 4 x 10 18 Test Techniques in Sensor IF: New testchip – Meas. Preliminary experimental measurements: DfT techniques Reconfiguration method: Opamp DC gain test Real OPA DC gain (3892(72dB)) detected DOLPHIN INTEGRATION TAMES-2 First Workshop 19 OUTLINE o Design and Design for Test (DfT) • Description of testchip contents • Chip packages • PCB and test set-up DOLPHIN • Experimental measurements INTEGRATION o Test • New test techniques: FFT-INL and Wavelet o Final conclusions TAMES-2 First Workshop 20 New Test Techniques: Static test (Motivation) Mandatory for Sensor interface applications Histogram-based approach as reference M = 128 Nh = 20 Ts = 1/5.12e6 s Thisto ≈ 65s DOLPHIN INTEGRATION Number of hits per code bin Oversampling ratio Resolution Time to perform one measure T = (217 − 1) N MT (T +T ) h s conv over Clock period TAMES-2 First Workshop Post-`processing time for one measure 21 New Test Techniques: Criteria DOLPHIN INTEGRATION Static Test (Motivation) Reference Test Plan FFT HISTO Cost 25,2 411 Spec/funct coverage 0,1 0,9 Weighted cost 252,0 456,67 Most time-consuming part of the reference test plan. Proposed solutions: FFT-INL Wavelet TAMES-2 First Workshop 22 New Test Techniques: FFT-INL (Implementation) an = DOLPHIN 2Y ( in ) , n = 0,..., N h N INTEGRATION g s (in) = a0 + ∑ an Cn (in) 2 inl = TAMES-2 First Workshop g s (in) ∆ ideal 23 New Test Techniques: Samples INLmax (LSB) 65536 2 131072 0.8 262144 Not available yet FFT-INL (Initial results) DOLPHIN INTEGRATION Reference test cost = 411+25,2 = 436,2 cts New approach cost = 228+25,2 = 253,2 cts Smooth INL + dynamic test TAMES-2 First Workshop 24 DOLPHIN INTEGRATION INL (LSB) New Test Techniques: FFT-INL (Initial results) 0 .5 0 -0 . 5 -1 -0 . 2 0 Input( Volts) TAMES-2 First Workshop 0 .2 INLmax 25 New Test Techniques: Wavelet (Implementation) DOLPHIN INTEGRATION ∆/2 ∆/2  1 ∆ dr = −20 log    2 2   ∆  dnl =   −1  ∆ ideal    dr enob =   − 0.5  20 log(2)  TAMES-2 First Workshop snr = dr + 1.76 26 New Test Techniques: DOLPHIN INTEGRATION Wavelet (Initial results) Samples DR (dB)* ENOB (bits)* SNR (dB)* DNL (LSB)* 16384 93.5078 15.0313 92.2485 2.5557 32768 94.400 15.1794 93.1401 1.6253 65536 94.4885 15.1942 93.2291 0.7590 131072 94.5367 15.2022 93.2772 0.7486 262144 94.5121 15.1981 93.2526 0.7675 *Average values extracted from instantaneous results Reference test cost = 411+25,2 = 436,2 cts New approach cost = 150+25,2 = 175,2 cts Allows measurement of instantaneous DNL, ENOB and SNR 75% test time saving (estimated postprocessing time) TAMES-2 First Workshop 27 ENOB (Bits) New Test Techniques: Wavelet (Initial results) 18 16 14 12 Instantaneous ENOB 10 8 DOLPHIN 6 DNL (SB) INTEGRATION Instantaneous DNL 4 2 0 -2 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 # samples TAMES-2 First Workshop 2.2 x 10 5 28 OUTLINE o Design and Design for Test (DfT) • Description of testchip contents • Chip packages • PCB and test set-up DOLPHIN • Experimental measurements INTEGRATION o Test • New test techniques: FFT-INL and Wavelet o Final conclusions TAMES-2 First Workshop 29 Final Conclusions Preliminary experimental results of silicon (March 2004) Σ∆M performance very close to specifications Reconfiguration method works correctly New test alternatives show promising results FFT-INL slower but full coverage achieved Wavelet faster. No full coverage DOLPHIN INTEGRATION Further analysis required to: FFT-INL Accuracy estimation Improvement in test time (post-processing) Wavelet Link instantaneous DNL and standard DNL Improvement in test time (post-processing) TAMES-2 First Workshop 30