A Design Of A Hard Disk Interface For The Micropolic... Brown, William Harold Calhoun: The Nps Institutional Archive 1981

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Calhoun: The NPS Institutional Archive Theses and Dissertations Thesis Collection 1981 A design of a hard disk interface for the micropolic 1223-1. Brown, William Harold http://hdl.handle.net/10945/20488 ' HP m m n ' ' V.V- .' m sk Hi r* MSmMKotw was V H -H ESffSQ Wm WSmi 1 affw mijffl ' 1 88w - EV KNOX LIBRARV NAVAL POSTGRADUATE SCHOOL Monterey, California THESIS A DESIGN OF A HARD DISK INTERFACE FOR THE MICROPOLIS 1223-1 by William Harold Brown December 1981 Thesis Advisor: M. L. Cotton Special Distribution T204549 M SCCUHITV CLASSIFICATION OF TNIC »»Gf .'•»•«. D— i ««...-.*> READ INSTRUCTIONS BEFORE COMPLETING FORM REPORT DOCUMENTATION PAGE V * ITSSt numTFK 4. T|Ti.£ an.* 2. GOVT ACCESSION NO Jutmj.i auThOK, TYNC Of REPORT S. • M», OD COVERED Master's Thesis December 1981 A Design of a Hard Disk Interface for the Micropolis 1223-1 7. RECIPIENT'S CATALOG NUMICf S •/ •• rcrporming one. report I. CONTRACT ON CHANT NUMBERS numkr William Harold Brown »CMPO«MING ORGANIZATION NAMC ANO AOORCtt » PROGRAM ELEMENT. PROJECT TASK AREA * WORK UNIT NUMBERS 10. ' Naval Postgraduate School Monterey, California 93940 I I CONTROLLING OF'ICC NAMC ANO AOORCtt December 1981 Naval Postgraduate School Monterey, California 93940 14 MONITORING AGCNCV NAMC REPORT DATE 12. NUMSIS OF PAGES 19. 87 * AOORESSYI' BWfMwM 555 CmnrmlUng OWc*> IS. SCCUHITV CLASS. CI thf rafrirt; Unclassified \*m. DECLASSIFICATION/ DOWNGRADING SCNCOULC IS. DISTRIBUTION STATCMCNT (ml »!• A«#«fi) Special Distribution 17. DISTRIBUTION STATCMCNT It. SUPPLEMENTARY NOTCS it. iccv won OS (Cmimu* tol <»• «••(?•« a»«*r«« •* '•»•»•• •<#• II In ll.e* 20. If Mllmtmnt i«»c«««arr •»* (Bantu* *r «••* — hmm *•••«) t) Hard Disk Interface, Micropolis Winchester Disk 1223-1 20. ABSTRACT (CiMtM— «m /•»«•• •<#• II n*«*«««rv «Mf i«*m«<4> »r »<•«* —Bf J This thesis develops an interface to the Micropolis 8 inch Winchester disk drive model 1223-1, using an Intel 80/20 single board computer as the programmed input output device. This system is part of the AEGIS modeling group at the Naval Postgraduate School. do ,: 'ZTr, 1473 COITION OP NOV tt S/N o 102-0 M- «S0t I I It OBSOLETE IECURITV CLASSIFICATION O* TNIt PAGE (-»•" Of B*t—4) Special Distribution A Design cf a Hard Disk Interface for the Hicropolis 1223-1 by William H. 3rovn Lieutenant, United States Navy B.S. Physics Auburn University, 1975 Submitted in partial fulfillment of the requirements for the degree of HASTER OF SCIENCE IN ELECTRICAL ENGINEERING from the NAVAL POSTGRADUATE SCHOOL December 1981 DUDLEY KNOX linoA D „ NAVAL POSTGRA?! ia? V ABSTRACT This thesis inch Winchester develops an disk drive 80/20 single board device. interface to model 1223-1, the Micropolis using an computer as the programmed This system is part of the Naval Postgraduate School. 8 Intel input output the AEGIS modeling group at TABLE OF CONTENTS I. II. INTRODUCTION A. PURPOSE OF THIS THESIS 9 B. ORGANIZATION OF THIS THESIS 9 THE HICROPOLIS 1223-1 WINCHESTER DISK OVERVIEW 11 B. THE HICROPOLIS 8-INCH DISK DRIVE 12 C. THE COMMANDS 15 D. PARAMETER AND TERMINATION BYTES 19 E. BOS PROTOCOL 19 1. General Operation 19 2. Host I/O Protocol 21 HICROPOLIS INTERFACE REQUIREMENTS THE INTEL 80/20 SBC 21 30 A. SBC CHARACTERISTICS 30 B. SBC INTERFACE REQUIREMENTS 31 1. C. IV. 11 A. F. III. 9 The 8255 PPI Operational Summary THE INTELLEC MDS SYSTEM THE INTERFACE DESIGN A. B. 31 36 39 39 HARDWARE 1. The Micropolis1223-1 39 2. Intel 80/20 SBC 40 ELECTRICAL CONSIDERATIONS 4 41 SOFTWARE C. 1. SOFTWABE TIMING D. 7. Initialization and Verification CONCLUSIONS AND RECOMMENDATIONS. 44 44 45 51 A. INTERFACE DIFFICULTIES 51 3. RECOMMENDATIONS 52 APPENDIX A 56 APPENDIX B 71 LIST OF REFERENCES 85 BIBLIOGRAPHY 86 INITIAL DISTRIBOTION LIST 87 LIST OF TABLES I. Specification Suamary 15 II. Read Command Byte 17 III. Parameter Bytes 20 IV. Status Byte 25 7. Interface Signals 26 71. Port Definitions 34 711. node Definition Summary 35 LIST OF FIGURES 2.1. Disk Format 2.2. Class Command Byte Coding 13 2.3. Host I/O Protocol 22 2.4. Read/Write Protocol 23 2.5. Command Verify/Wait Status Protocol 24 2.6. Host Interface Pinout 27 2.7. Host Interface Bus Timing 28 2.8. Status Eyte Coding 29 3.1. 8255 Blcck Diagram 33 4.1. Interface Block Diagram 42 4.2. System Interface Pinout 43 4.3. Electrical Interface 48 4.4. Calculated Pulse Timing 49 5.1. Alternative Data Transfer Protocol 55 . 14 Acknowledgements I wish to express my and the members of provided was this report. sincere appreciation to my advisors the AEGIS invaluable in the I would consoles, I never writes my acknowledgements. The assistance they preparation and also like to beautiful wife without whom comforts and group. brillant and thank my would be nothing. complains or writing of She always interferes and INTRODUCTION I. A. PURPOSE OF THIS THESIS interface The formulated for herein was developed computer hardware the to provide a Intel controller for 80/20 single board Micropolis the described 1223-1 hard disk unit. This system along with the interface will be available the for ongoing AEGIS Postgraduate School. programming and Furthermore the interface disk a computer gave the author an about project modeling microcomputer at the Naval experience of wiring with a board single opportunity to learn first hand and hardware programming techniques required for such a project. B. ORGANIZATION OF THIS THESIS This thesis hardware involved is organized and the software Winchester disk interface. descriptions into required for Additional of an operating system to Micropolis disk Chapter drive. working a attention is paid to the modification hard the of accomodate the 2 is a brief introduction into disk drives such as the Micropolis 1223-1. The operating requirements characteristics, are discussed bus protocol in detail. and interface Chapter 3 is a discription of the Intel 80/20 single board computer it f s interface capabilities, followed by Intel Microcomputer Developement System in the interface construction. interface design used for this successful chapter concerning the modeling Chapter encountered applications of appendices contain the covers the actual of system Winchester into the the disk to recommendations in the AEGIS the programs developed disic. some AEGIS of model. as part read/write routine. 10 the future for The of this thesis for initialization and verification of the disk, a the recommendations some pertains 5 and the with implementation of difficulties 4 the bus protocol requirements conclude project. and it f s role modifications communications with will discussion of the (MDS) Chapter including hardware and software to meet a and and THE MICBOPOLIS 1223-1 WINCHE5TEB II. A. DISfi OVERVIEW High performance, high quality, and disk drives systems. are now Most technology, a hard cost reality low disks and other large capacity use hard for micro com pater Winchester modern techniques head media, to achieve high density and high performance. The bottom line specifications volume high for storage units reliability, cost, are capacity, and data access time. One of Winchester over disk a density floppy Megabytes of data, with disk. and With a a of typical double a maximum 48.2 microseconds. microseconds for of 1.6 a Compare that double density floppy Winchester disk dirt, fingerprints, scratches, medium surface Winchester disk stores that a Accessing data on an 8-inch Winchester an average of about 100 Whereas is using the average midrange Winchester can hold almost 18 Megabytes. disk takes for system floppy disk dramatically 'increased capacity. sided double reasons attractive most the units are interferences are almost completely sealed manufactured under cleanroom conditions. 11 nonexistant. after having been B. THE MICROPOLIS 8-INCH DISK DRIVE model 1223-1 The consist of a drive with an integral controller board. overall dimensions same flexible disk as has compatable mounting drive, the same D.C. supply voltages. transfer data arrangements and sectoring computer through group has 3 disk with surface and a disk has been controller. procedures (ECC) be 5 sector. Full attached to selected for the the AEGIS data surfaces, host asynchronous of 35.6 transfers checking error provided ensure Each Megabytes. 24 sectors at a single sector between host Error high and recovery error and performed. to modeling 580 tracks per data The controller has are automatically is standard six in preset at the manufacturer for mode for buffer can formatted capacity 512 bytes each and requires simple bus-oriented interface. Micropolis model The code a inch 8 The controller provides full facilities control and The 1223-1 has the industry standard an disk Micro polis fixed correction integrity. A specification summary can be seen in Table I. The makes 1223-1 controller use of the track/secror format shown in Figure 2.1. Tracks are divided into of sectors which contain a fixed blocklength 12 a number of user data. The beginning of each sector is from the disk drive. identifed by a sector pulse track contains one spare sector Each which at the time of initialization can be made to fall over a defictive area of the track. The sectors are field, divided into an address trailing gap and a significant bit Data area. first where bit is recorded most most significant the 7 is a data field, and bit zero the least significant of each byte. The address field contains a unigue information. commands only. The This track/sector address and associated field during initialize The preamble synchronizes the read circuits. address mark identifies the There are two cylic field. written is of an beginning address redundancy checks (CRC) bytes, conputed from the contents of the address mark and bytes 0-3 using the polynomial This polynomial catches all single and double errors with an odd number of zero bits, length 16 99.998% of 3 oivless, 18 99.997% of bit and longer bursts, all all burst errors of error burst, [fief. 1] Bytes and thru and logical sector addresses. contain the head, cylinder, The data 17 bit errors, field contains user data 13 for transfer to or from < a < M Q ui Ui § -t u • H 3 a O > l-t CJ ccto < CU HJ1 a as ui 0* < » 90 • 00 co en • • • • . v- na as < H < T SO CN r-l ir» CM i-* m O t-i Ul C/] /~\ wuU1§ w u u CO O O >• J >< -3 XUKQ «< £ co co ui OS Ul -i u. a J 5 a < a- as X Ul a z o H U Ul z ^ o CO 03 £ 5O H z CJ Ul Ui o CO CO ±c H \ Disk Format Figure 2.1. 14 • CO vO CN v© «* o «tf >» 1 u H > A JU -j 5 as CO 3 H < H z o s^ CO u T O H H s U) 04 H < 3 < >— u Ul Z c_> Cd CO o in .-* CN fr- ee <»^ g 2 a z < Ul H o I o OS o B >»• z 3 o u o p* u CO ii-Aii ™ T r Ul ">» 09 •< Ul CO «^, r» i Z o CO => BQ Ul Figure 2.7. iS . < a *»«. «>. B 2 CO CO Host Interface Bus Tilling 28 afi STATUS BYTE 7 6 A T U T i- 5 4 D c R B E Q Pigore 2.8. | 3 ^ NN> i 2 1 I R 1 D Y Ft ? Status Byte Coding 29 THE INTEL 80/20 SBC III. A. SBC CHARACTEBISTICS For the purpose of this thesis general description of the Intel is followed by a capabilities more in which will the author feels a brief 80/20-4 is in order. depth presentation prove more useful This I/O of its* actual in the interface design that follows. 80/20-4 SBC The self-contained n-channel is computers MOS 808QA computer system on member a based CPU. SBC 80/20-4 The line powerful the on single 6.75 a Intel's of is a of 8-bit complete by 12 inch printed circuit board. The CP0, system clock, read/write memory, nonvolatile read only memory, I/O and ports drivers, communications interface, interval timer, serial bus control logic and drivers all reside on the board. The 8080A has a 16 bit program counter which allows direct addressing of up to 64K bytes of memory. portion of memory, external stack, accumulator and registers. A located within any may be used as a last in/first out stack retrieve the contents of to store and flags, An sixteen all of the six stack bit addressing of this external stack. 30 the program counter, general pointer purpose controls the Sixteen line address and eight line bidirectional data buses are used to facilitate easy interface to memory and I/O. programmable A Intel's serial communications Universal 8251 interface using Synchronous/Asynchronous Receiver/Transmitter (OSABT) is contained on the board. USART can be programmed by virtually any 1 software to provide s serial data transmission The 8251 in use. tne system provides full The technique presently duplex, double buffered transmission and receive capability. SBC contains The implemented Interface the I/O using two (PPI) in parallel I/O 8255 Programmable combinations customized to In order lines Peripheral The software is used to configure to take unidirectional of and bidirectional ports. may be requirements. programmable Intel devices. lines input/output, interface 48 meet specified advantage number of possible I/O configurations, the I/O Therefore, peripheral of the large sockets are provided for interchangeable I/O line drivers and terminators. B. SBC INTERFACE REQUIREMENTS 1 . The 8255 PPI Operational Summary For the interface considerations preceding sections the disk presented in controller dictates 31 an 8 the bit bidirectional bus for data transfer. Hith this constraint in mind only the 8255 PPI need be discussed in detail. The parallel I/O interface logic provides 48 signial lines for on the SBC 80/20-4 the transfer and control of data to or from the peripheral devices. Sixteen lines have a bidirectional installed. driver and The remaining thirty-two are provided Sockets termination networks the for passive driver/termination perminantly lines are uncommitted. installation of networks. active or optional drivers The and terminators are installed in groups of four by insertion into the 14 pin sockets. be seen in Figure 3.1. 8255 PPI can allow for a can be configured characteristics dictates two 8255 devices The wide varity of I/O configurations. The 8255 contains All basic block diagram of a single A the three 8 bit ports in a varity in Table as described operating wide VI. characteristics of (A,B # of and C) functional The 8080 the ports CPU by outputting control words to the 8255. There are three basic modes of operation that can be selected by the system input/output mode. software. zero is is concerned Mode one input/output while mode Mode with a two is the bidirectional 32 the basic strobed bus mode. o GROUP A PORT A I/O PA7-PAO *— D7-D0 d> GROUP B PORT B J Figure 3.1. 8255 Block Diagraa 33 I/O PB7-PBO < > TABLE VI Port Definitions Port A.... One 8 Port B....One 8 bit data output or input latched buffer. bit data I/O latch buffer and data input buffer. Port C....n25 8 one 8 bit data output latch buffer bit data input buffer. This port can be divided into two ports under mode A summary can be of the mode seen in Table 2 operations. deffinitions and Due to VII. controllers requirement datalines it will only be necessary for bit 4 port configuration the fact that an 8 bit the disk bidirectional to discuss the mode 2 operation of the 8255 here. The provides a mode 2 bidirectional means for communicating or structure on a single 8 bus I/O configuration with a peripheral device bit bus for both transmitting and receiving data. Handshaking signals as seen in Table VII are proviged to maintain proper and bus flow. are enable/disable functions apparent from Table VII that mode Port C provides also 2 Interrupt generation available. is is only used in port A. the five bit control port while 34 It port B can TABLE VII Mode Definition Summary MODE MODE MODE 1 2 ONLY IN CUT IN OOT GROUP PAO IN OCT IN OUT BIDIRECTIONAL PA2 IN COT IN OOT BIDIRECTIONAL PA3 IN OOT IN OOT BIDIRECTIONAL PA 4 IN COT IN OUT BIDIRECTIONAL PA5 IN OOT IN OUT BIDIRECTIONAL PA6 IN OOT IN OOT BIDIRECTIONAL PA 7 IN COT IN CUT BIDIRECTIONAL PBO IN COT IN OUT PB1 IN OOT IN OUT PB2 IN OOT IN CUT PB3 IN COT IN OUT .. A ,__ _— —— urn ' PB4 IN OOT IN OUT PB5 IN OOT IN OUT PB6 IN OOT IN OUT PB7 IN COT IN OUT PCO IN OOT INTB(B) PC1 IN OOT PC 2 IN PC 3 i i. „ I, ., —, __ I ,., i. --- i IBF(B) INTR(B) OBF(B) I/O I/O CUT STB(B) ACK(B) I/O IN OOT INTB(A) INTR(A) PC 4 IN OOT STB (A) I/O STB PC 5 IN OOT IBF(A) I/O IBF(A) PC 6 IN COT I/O ACK(A) ACK(A) PC 7 IN OOT I/O OBF(A) OBF(A) 35 INTR(A) (A) ,. . i.i be used in mode the inputs or 1 . and outputs (Interrupt Request) It should also are latched. high on A output will go low written data to port A lew A. The OBF (Output Buffer indicate that to on the ACK A low on the SIB (Strobed Input) the CPU (Acknowledge) enables the tristate output buffer of port data. the INTfi output can be used to interrupt the CPU for both input or output operations. Full) be noted that both A to has input send out the indicates that data has been loaded into the input latch while IBF (Input Buffer output indicates Full) input latch. or none It that data has been might be pointed out ar this time that all just presented handshaking signals of the loaded into the can be used for the 80/20 to function properly. C. THE INTELLEC MDS SYSTEM was used in this thesis The Intellec MDS center SBC. the 80/20 for microcomputer design The system that as the design Intellec is provides through the entire production design cycle. complete a total support The MDS is also modular, which allows custom tailoring of systems. The standard components: (3) a (1) Intellec MDS central processor, monitor module and (4) (2) system four main frount panel control unit 16K RAM. 36 has The central processor of the MDS capabilities system the as processor was Intel an SBC 80/20 used to develope means of loading the SBC. is 8080 with discussed the same earlier. The the software and provide a the interface programs into the 4K RAM of Memory and I/O interface logic is also provided on the CPU module. The module drives a three state, 16 line address bus, which communicates with the external memory and I/O device decoding logic. provides the means bidirectional, A for the actual data 8 line data bus transfers. The CPU module can address up to 65,536 bytes of memory. The 16K RAM module provides the Intellec MDS system with 16,384K bit words of dynamic random access memory. RAH modules used in the MDS utilized in this thesis, by 8 There are four for a total of 6UK HAH. The monitor module of the resident CPU was not used for the interface developement but the monitor that resided on the SBC was is in order. have therefore used, a brief description The monitor module enables the firmware storage for the monitor program peripheral devices such as interfaces with MDS system to and teletype, I/O CRT, line printers, or paper tape readers. The monitor module can include 2048 by monitor program. 8 bit words of ROM for storage of the system The monitor 37 program used on the SBC is identical to the Debugging DDT (Dynamic program Tool) associated with Digital Research^ CPM operating system. The monitor module in conjunction with used to control the transfer CHT for instance can be of data, information between the SBC and Here again a it must be pointed control, and status it»s associated I/O device. out that the monitor of the MDS system was net used but the monitor on the SBC, which is identical, was utilized. drives the INTERRUPT, The frount panal control module RON and HALT switches. This module served to provide a means of interrupting the execution of a program to allow the user to monitor the progress program or check the contents of the registers. 38 of the THE INTERFACE DESIGN IV. , A. HARDWARE the In interface preceding requirements for thesis was presented. actual interface the chapters characteristics the the hardware involved in and this chapter the author describes In this used and the software developed to successfully communicate with the disk. The Microcolisl 223-1 1 . The first consideration for interface for the Micropolis disk in the buffered provided in Figure be required to operate Using mode. 2.6 and Table V it is signals which source is the host hardware was to determine which of the provided handshaking lines would the system building the the descriptions apparent tnat the would be necessary for the disk controller to function properly, but those which source is the controller could be implimented Inotherwords, the signal lines ATTN, in the CBOSY, software. DREQ, and 00T are also flags in the status byte. These lines were provided for the flexibility environment. of V the disk in a DMA Inaddition, the only other lines required were the SEL and ENABLE lines. Table operating Using this line was connected 39 the definition of SEL from permanently to a +5V source because there was no other The ENABLE was disk controller in used as a programmed reset the system. at the beginning of each execution of a read or write command. XQte; 80/2Q SEC 2. It was established in Chapter III that the SBC's PPI would be required to operate directional needs in mode of the Winchester signals available at port C of the of Figure is conveniant 3.1 it 2 to satisfy the bi Looking at the disk. PPI in the mode 2 column to utilize lines PC0-PC2 to accommadate the WSTB, RSTB This is an obvious decission for port mode C in leaving port B 2 available for mode remaining control lines. port C(L) Secondly, it has an available socket I/O and DATA lines. two reasons. divided can be , the three First of all into 2 or operations for the 1 four bit ports since PC0-PC3 belong to (A4) which is ideal for the terminator network that is required by the disk; more on this later handshaking mode. Since under electrical considerations. OBF, specifically designed signals were programmed for the PPI was transfer and operating in IBF were net needed. The remaining a for a DBA bidirectional bus buffered mode the output signals Likewise, since the SBC was the only device requiring access to the Winchester disk the INT2 40 line was not proper employed. The SBC does require operation those description of BSTB being ACK, in Chapter II 2 Using and STB. it is inputs for the signal the ACK required by the SBC. This implies that all that is necessary for this particular handshake is a feedback of SBC on every read command. The ENABLE line mentioned in the preceding section was designed as from port PBO and at B reset taking it - s inputs a passing it through a termination device before connecting it to the disk controller. pinouts are the interface 4.1 and A basic handshaking lines can be seen block diagram of the data and in Figure to the BSTfi described in Figure 4.2. B. ELECTBICAL CONSIDEBATIONS The 1223 requires industry standard 8 disk was mounted in with only The buffer/driver a supply voltages as an inch flexible disk drive. The Winchester a dual floppy disk frame. slight modification a interfacing DM7438 is the same D.C. of handshaking the gates with quad dual input to the open an This was done mounting brackets. signals required collector output. The NAND gate with the desired open collector feature which made it ideal for the control lines. 41 QPOOO Figure 4.1. Interface Block Diagraa 42 —————————————— HOST FUNCTION DISK PORT PIN# FUNCTION DATA (MSB) PA7 34 DATA (MSB) 2 DATA PA6 36 DATA 4 DATA PA5 38 DATA 6 DATA PA4 40 DATA 8 DATA PA3 42 DATA 10 DATA PA2 44 DATA 12 DATA PA1 46 DATA 14 DATA (LSB) PAO 48 DATA (LSB) 16 ENABLE PBO 16 ENABLE 26 SEL PB1 14 ACK PB2 12 WSTR PCO 24 WSTR 24 RSTR PCI 22 RSTR 22 DATA PC 2 20 DATA 20 STB PC 4 22 (F/B t > Figure 4.2. The electrical 4.3. The bidirectional bus resistors 80/20 28 — — — PC4) System Interface Pinout used can had the drivers with installed. PIN# SEL best interface SBC — Also each 43 8226 in Figure be seen bit four their associated line out of parallel 1K pullup the SBC is inverted as is the input any need for inverters of the disk controller eliminating the in connection was achieved through a data lines. The actual 34 pin flat cable attached to the disk controller edge connector J 101. C. SOFTWARE 1 . Initialization and Verification Each data surface of the disk must with the desired format before normal use. commands are provided for this purpose. be reviewed in section C of Chapter II. seen in Appendix (INTVFY. ASM) The A. Three initialize These commands can This program can be initialize and verify one command Figure 2.3 was used to (19H). The flow diagram of implement this user utility program, with some slight modifications. bottom of the flow diagram for The decision loops at the read and write commands were being executed prevent an accidential INTVFY which would destroy any user data on the disk. what redundant due to the fact in the protocol to prevent and program combines the two commands INITIALIZE TRACK and VERIFY FORMAT into eliminated to be prerecorded verify routine does that command echoing is used just such errors. not This is some envolve any The intialize data transfers between the disk controller and the host. The INTVFY program 44 is designed to foraat one entire platter side by holding all parameter bytes fixed except the cylinder address Once the single disk side is completed user can change the head (approx. monitor on the SBC with the substitute restarting the reformated in 5 and write INTVFY. ASH program disk branching. program is drive INTYFY.ASH is can frequently used aodules written such as IRDY, to be slower than This proved variant single a were Subroutines a comprised of in that it is subroutines whereas CBOSY. using the be minutes using this technique. The read any the command and then (S) The entire program. sec) 18 address paraaeter byte bytes. ORDY, a from the series of string without for most the STATUS, and ideal execution time due to the number of POSH and POP commands that are enherant with subroutines. The read or write program (READRITE.ASM) can be seen in Appendix 3. D. SOFTWARE TIHING The execution of phases: intiation a initiation, phase, controller command consists of three execution, and the specified by the host, controller verifies termination. decides the In the command the validity of parameters and performs housekeeping functions necessary to execute the 45 command. In the execution phase, the requested functions are performed. In the termination phase, the controller performs post execution housekeeping and determines the termination status for the command. An example of delays specified subroutine the software timing, in Figure in Appendix B. 2.7, can be The majority timing involved an extensive use of the program since seen in the ORDY of the software the IN and OUT commands concerned with basically is required by the as I/O data manipulation. By outputting a 02 hex to the SBC control port E6, in this example, control port (port C same port (L) the RSTH ) . pulse is turned on at the This followed with a 00 hex to the turns off the BSTB. The user is also reminded that anytime a read strobe control word is being pulsed that this is also pulsing the STB control line of the SBC. This latches in the the disk controller status byte which is then moved into the accumulator to mask the OBDY bit (bit 1 of status byte) An example of writing a command byte to the command port can be seen in Appendix A. 2.7 to write a Using the timing diagram Figure command byte to the port WSTR needs to disk controller command be pulsed and the ACK to 46 the SBC»s 8226 must be turned on before pulsing and then off after strobing is completed. The pulsing sequence can be seen on line 70 of Appendix A. Here the command INTVFI is being sent to the disk controller's command port. The command is first latched into the SBC's data port (E4) the SBC control port on at The WSTB. The ACK line is next turned . E5 followed by the sequence is completed strobing of by restoring the 8 DATA lines to the input mode by turning ACK off. The next example is the writing of a parameter byte to the disk controller data port. This can best be demonstrated by looking Appendix A. be sent at the PBAH1 module For this particular out contains all zeros. of the INTVFY program case the parameter byte to By using Table implies that the head and unit address is zero. here is the same as it was in the in III this The pulsing preceding example except that the data control line of E6 is pulsed prior to the HSTB line pulsing and pulse going delays low. in Figure This technique 2.7. agreement with Figure The of the upon completion turned off complies with measured pulse 4.4 which is the the delays. 47 HSTB the timing delays are in calculate values of 10 • MAX 34 PIN FLAT CABLE H HOST SYSTFM +5V 1 223 MODULE 220 746 5XX 5V IK BUSO-BUS7 220 + 330 + + 5V DM7438 SEL/ DATA/ RSTR/WSTR/ +. 330 +. 1. All signal lines are low true at the interface connector and high true into drivers and out of receivers. 2. Interface signal levels are lows 0-0.4V^25mA. high= 2.5-5.0V(dOraA 3. Host provides IK pullups on Bus 0-Bus7. 4. 220/330 ohm terminators are installed in 1223 module. Figure 4.3. Electrical Interface 48 u o CO CU V) U] m CO X H 3 > s CO CO «n O »r> • (4 CO o hi O H 3 \—t > £ 1 o [ i i 8.5 SEC 8.5 SEC 8.5 SEC *U +i WSTR RSTR f-2 MHZ MVIa 7 STATES OUT- 10 STATES T» It STATES — Figure 4.4. When the disk Calculated Pulse Tiaing controller has received and command byte, six parameter bytes, and the GO byte the disk controller goes low and executes the command. transfers to or from the host data is then stored in program in Appendix the disk B. verified the The disk then 512 bytes of user data. buffer titled the TABLE1 in This the Opon completion of the data transfer controller finishes up the 49 termination phase by issuing the termination status byte to the host computer. breakdown of the termination status seen in Reference 2. 50 A byte error codes can be CONCLUSIONS AND RECOMMENDATIONS V. From Chapter I? would it appear that design was a clear and strightf orward process. the interface However, the author encountered several inconsistancies that made the job not so candid. The facts that the author was unfamiliar with the hardware and very had limited exposure assembly to language programming techniques compounded the task. A. INTERFACE DIFFICULTIES One of the first difficulties phase of the interface of handshaking number lines and determine which ones definitions or functions The documentation provided for the confusing 80/20 was to the large operations in the buffered mode. the lines had the same compounding the problem. SBC best utilize was how to would not be necessary for Too few of encountered in the design caused mainly by the number of options, modes, and port definitions that are available. The documentation author 1 s pertaining to biggest stumbling the Micropolis The block. "track oriented" commands and "noraml number of hours of reading and 51 disk was manual refered commands". rereading the to It took a the manual in conjunction with phone calls to the difference. author It was at the last possible minute that the able was statement that detailed the manufacturer to resolve the AOXILLABI drive and the manufacturers STATUS bytes, which contain ascertain, from to controller status information, was incorrect in the manual and that two revisions had been made to the text. The MDS system provided additional hardware problems. the outset double of the density MDS density system at necessary. project Once a frustrating MPS a waiting list to use dedicated MDS a cronic a being used being the This was traded habit of 8 double only the system was for crashing second The another. which possessed the the week not to mention burning The author lost on the system was assigned to the single density version HDS directory once supply. system. the problem system is SBC was project the Ax 0/S and the out the power hours a week just recovering from these failures and updating backup disks. B. RECOMMENDATIONS One of the operations in the the system recommendations for future AEGIS modeling system would presented here to allow 52 the disk to hard disk be to modify operate in the DMA node. This would require some hardware and software alterations to the present system. The hardware changes would include handshaking lines provided as four controller namely: the SBC. Osing drivers or terminator installed. A use These four and OUT. port of the second PPI on port A would eliminate any networks because need for adding they are already Then by polling this port it would eliminate the need to read in the status byte after every transfer byte to check for flags. Two additional inputs required of output lines of the disk ATTN, CBOSY, DREQ, lines could be connected to the making on the host computer side for OBP of a would be and IBF to prevent an overrun of data during transfers. The read slight software would need and write command modification. The READ and presented in Figure 2.4 would be flow diagrams in Figure 5.1. provide a loops would which is insensitive to sector the direct mode, flow diagrams modified to conform to the These read data and write data transfer being transferred, WRITE only a general transfer length, number protocol of sectors and the speed of the host interface. interface the host must response to all data requests at disk speed. 53 provide In for Before the Hicropolis disk can be fully implemented in the AEGIS modeling system it will require a Customized Basic Disk Operating intended to but vas System (CBIOS) . had originally an appendix to this thesis because of the number of hardware include a CBIOS as unable to do sc The author failures of the MDS system. 54 WRITE c D J EXIT GET DATA FROM BUFF WRITE DATA TO PT. Z Figure 5.1. ^/ / Alternative Data Transfer Protocol 55 ~"\ APPENDIX A ORG 3000H *************** ******************************************** * THIS IS A USER UTILITY PROGRAM TC INITIALIZE THEN VERIFY* * EACH TRACK ON THE 1223 DISK WITH THE DESIRED FORMAT. * * INITIALIZE TRACK WRITES ENTIRE LENGTH OF CURRENT TRACK * * USING HEAD- CYLINDER, SECTOR SEQUENCING. AND SPARING * * * INFORMATION CONTAINED IN THE ACCOMPANYING PARAMETER * BYTES. DATA FIELDS CONTAIN 51H IN ALL DATA LOCATIONS. * * VERIFY FORMAT VERIFIES THAT THE TRACK IS CORRECTLY INIT * * IALIZED READS ENTIRE TRACK AND COMPARES AGAINST ORIGINAL* * * PATTERN *********************************************************** NOP NOP *********************************************************** ACCUM... ; CLEAR SUB A ;ZERO OUT PRAM2 PRAM2 STA ;ZERO OUT PRAM3 PRAM3 STA ;LOAD COUNTER INTO 6 INTVFY: ADI :3 REGISTER. B.A NOV .*************** ******************************************** ;PRCGRAM 8255 TO A.OCOH MVI CUT MVI OUT ;MODE 2. INITIALIZE ACK/ OUTPUT ACK/ TO PT. B 0E7H A.004H 0E5H ; ; *********************************************************** * * * * READ STATUS BITE. IS CONTROLLER BUSY ? * * * ************** ******************************************** CBUSY1: MVI OCT MVI OUT IN ANI CPI JNZ ;RSTR CMD TO CONTROL PORT A.002H 0E6H A.000H 0E6H 0E4H 010H 010H CBUSY1 ; ;RSTR PULSE OFF ;READ STATUS WORD ;IS CBUSY TRUE ;OR FALSE ;CONTROLLER BUSY GO BACK.. *********************************************************** * * * READ STATUS BYTE TC SEE IF OUTPUT BUFFER IS FULL.. ! * * *********************************************************** ORDY1: MVI CUT MVI OUT IN ANI CPI JNZ ;RSTR CMD TO ;CONTROL PORT. PULSE RSTR ON ;THEN OFF. ;READ STATUS BYTE ;MASK STATUS BYTE FOR ORDY. A,002H 0E6H A,000H 0E6H 0E4H 002H 002H ORDY1 ; ; 56 RETURN TO RSTR IF NO ORDY. A********************************************************* * * LOAD COMMAND BYTE 1 INTO * AND VEBFICATICN OF DISK... * * CONTBOLLEB FOR INITIALIZATION * * ********** ************************ ************ ************** MVI COT MVI OUT MVI OUT MVI OUT MVI OUT A-019H 0E4H A.000H 0E5H A.001H 0E6H A,000H 0E6H A.004H 0E5H ;LOAD CMD 1 ;PUT CMD 1 TO OUTPUT PT. ;TUBN ACK/ ON POST B ;WSTB CONT . WOBD TO ACCUM. PULSE WSTB ON PULSE WSTB OFF ; ; ;BESTOBE ACK/ TO ;B POET *********************************************************** * * * * * COMMENCE COMMAND VEBIFI CF COMMAND BYTE BY BEADING * STATUS BYTE.. * *********************************************************** OBDY2: MVI OUT MVI CUT IN ANI CPI JNZ A.002H 0E6H A,000H 0E6H 0E4H 002H 002H ORDY2 BSTB CMD TO CMD POET ON AND THEN OFF BEAD STATUS BYTE MASK 0BDY2 TBUE OB FALSE IS OBDY2 ? *********************************************************** * * IS INPUT * * * BUFFEB BEADY ? (IE. IS INPUT BUFFEB FULL?) * *********************************************************** IRDY1: MVI OUT MVI OUT IN ANI CPI JNZ PULSE BSTB CMD TO CONTBOL POET TUBN OFF BSTB PULSE BEAD STATUS BYTE MASK IBDY 1 A.002H 0E6H A.000H 0E6H 0E4H 001H 00 1H IS IBDY1 IRDY1 ? *********************************************************** * * COMPABE RECEIVED CMD BYTE WITH ORIG. PATTERN TO VERIFY * CORRECTNESS. ERROR MSG INCORBECT... 1 OUTPUT IF * * * * * *********************************************************** MVI OUT NOP MVI ;TUBN DATA PULSE ON ;TO CONI. PT. ;TIME DELAY ;RSTfi SDATA PULSE A.004H 0E6H A, 006H 57 OUT 0E6H A.004H 0E6H MVI COT NCP MVI A,000H C DT Q e6 H 0E4H 019H 019H ERRMSG1 IN ANI CPI JNZ * * WRITE PARAMETER * TO DATA PORT. .. * ;T0 CONT. PT. ;TURN OFP RSTS ONLY ;TO CONT. PT. ;TIME DELAY ;TOfiN OFF DATA LINE BYTE ;LOAD CMD BITE INTO ACCUM. ;MASK CMD TO VERIFY ;TO ORIGINAL PATTERN WRITE OOT ERROR MSG . 1 ; « 1 CONTAINING HEAD ADD. AND OUTPUT * * * *********************************************************** PRAM1: MVI OUT MVI OUT MVI OUT NCP MVI OUT MVI CUT NCP A,005H 0E6H A,004H 0E6H MVI A,000H 0E6H A,004H 0E5H OUT MVI OUT ;OUTPUT PARAMETER BYTE WITH HEAD ADDRESS ZERO 1 ; ;TURN ACK/ ON PORT E TURN ON DATA LINE TO CONT. PT. TIME DELAY PULSE HSTfi & DATA OUT TO CONTROL PORT TURN OFF HSTR ONLY TO CONT. PT. TIME DELAY ON THEN OFF.. A,000H 0E4H A.000H 0E5H A.004H 0E6H ;RESTORE ACK/ PORT B * * * PARAMETER BYTE... ************************************************ *********** * COMMAND VERIFY FOR FIRST ORDY3: MVI CUT MVI CUT IN ANI CPI JNZ RSTR CMD TO COMMAND PORT ON AND A.002H 0E6H A,000H 0E6H 0E4H 002H 002H ORDY3 THEN OFF. . READ STATUS BYTE MASK 0RDY3 TRUE OR FALSE IS ORDY3 ?... **** *** *************** ************************************* * * IS THE DISK CCNTROLLER READY FOR INPUT (IRDY) ? * * *********************************************************** IRDY2: MVI OUT MVI OUT IN A,002H 0E6H A,000H 0E6H 0E4H ; PULSE RSTR CMD ;TO CONTROL PORT ;TURN OFF ;RSTR PULSE ;READ STATUS BYT 58 ANI CPI 001H JNZ IBDY2 ;MASK IRDY2 00 1H ;IS IRDY2?.. *********************************************************** * * READ BACK PARAMETER BITE 1 FOB VERIFICATION.... * * * *********************************************************** MVI OOT NOP MVI OOT MVI OUT MOP MVI IN ANA JNZ CCB MOV CPI JZ MCV A.004H 0E6H A,006H 0E6H A,004H 0E6H A.000H 0E4H A EBBMS62 B A.B OOOH GOBYTE B, A TORN ON DATA LINE TO CONT. PT. TIME DELAY RSTB S DATA POLSE BEAD BACK PBAM1 TORN OFF RSTR ONLY TO CONT. PT. TIME DELAY TORN OFF STROBE LOAD PRAM1 INTO ACCOM.. MASK PRAM1 TO VERIFY WRITE OOT ERROB MSG 2. IS THIS THE LAST- PARAMETER BYTE ?... IF SO GO TO GO BYTE OTHERWISE SAVE PBAM COONT *********************************************************** * * WRITE PARAMETER BYTE 2 CONTAINING LSB OF CYL. ADD. * AND OOTPOT TO DATA PORT. IF Pram 2 IS IN OVERFLOW COND* TION CARRY OVER TO Pram. BYTE 3 AND CONTINOE TO VERIFY. * * * * * * *********************************************************** LXI MCV OUT MCV POSH MVI OOT MVI OOT NOP MVI COT MVI OOT NOP MVI COT MVI OOT LOAD ADD. PBAM2 IN HL REGS. MOVE PBAM VALOE TO ACCOM.. POT PBAM2 TO OOTPUT PORT H,PRAM2 A.M 0E4H DfA D SAVE PRAM2 VALOE TORN ACK/ ON PORT B TORN ON DATA LINE TO CONT. PT. TIME DELAY POLSE CN THEN OFF DATA AND TORN OFF WSTR ONLY TO CONT. PT. TIME DELAY WSTR TO CONTBOL POBT RESTOBE ACK/ PORT B A, OOOH 0E5H A,004H 0E6H A,005H 0E6H A,004H 0E6H A, OOOH 0E6H A.004H 0E5H *********************************************************** * * * COMMAND VERIFY FOR SECOND PARAMETER BYTE.... * *********************************************************** * * OBDY4: MVI ;RSTR CMD. TO A,002H 59 COT MVI OUT IN AMI CPI JNZ COMMAND PORT. PULSE ON AND THEN OFF. .. BEAD STATUS BYTE MASK OBDY 4 TRUE OB FALSE IS 0BDY4 ?... 0E6H A.QOOH 0E6H 0E4H 002H 002H 0BDY4 ******* *********************************** ********* ******** * * IS THE DISK * CONTBOLLEB BEADY FOB INPUT (IBDY) ?. . . *********************************************************** * IBDY3 MVI OUT MVI CUT IN ANI CPI JNZ A.002H 0E6H A,OOOH 0E6H 0E4H 001H 001H IBDY3 PULSE BSTB CMD TO CONTBOL PORT TUBN OFF ; BSTB PULSE BEAD IN STATUS BYTE MASK IBDY 3 TBUE OR FALSE ; IS IBDY 3 ? ; ; ; ; ; *********************************************************** * * BEAD BACK PABAMETEB BYTE * 2 FOR VEBIFICATION * * * *********************************************************** MVI OUT NOP MVI OUT MVI OUT NOP BVI OUT IN TUBN ON DATA LINE TO CONT. PT. TIME DELAY BSTB S DATA PULSE READ EACK PBAM2 TURN OFF RSTH ONLY TC CONT. PT. TIME DELAY TURN OFF STROBE A.004H 0E6H A,006H 0E6H A.004H 0E6H A.000H 0E6H 0E4H LOAD PRAM2 INTO ACCUM *********************************************************** * Pram. EYTE 2 BITH ORIGINAL VALUE AND INCREMENT * * TRACK NUMBER OB IF CHECK FAILS SEND EBBOR MSG. 3... * * *********************************************************** COMPARE POP CMP JNZ INR JZ MOV DCB MOV CPI JZ MOV JMP D D EBBMSG3 A CABBY M,A B A.B 000H GOBYTE B,A CONTINUE 60 GET PRAM2 VALUE COMPARE TO ORIGINAL 3 SEND ERROR MSG. ... CHG. TO NEXT TBACK IF C FLAG SET GO TO CABBY BOUT OTHERWISE STORE PRAM2. . . IS THIS THE LAST PARAMETER BYTE ?. . . IF SO GO TO GO BYTE.. OTHERWISE SAVE PBAM COUNT. *********************************************************** * * * * * THE CARRY ROUTINE IS UTILIZED IF Pram. BYTE 2 IS IN overFLCH CONDITION TO INCREMENT PARAMETER BYTE 3... * * * *********************************************************** CARRY: H,PRAM3 LXI MOV INR CPI A,M A 002B EXIT N,A JZ MOV INCREMENT ADD. TO PRAM3 AND MOV TO ACCOM. INCREMENT PRAM3 IS THIS CYLINDER 579 ?.. IE SO END INTVFY. SAVE NEW PRAM3 VALUE... ************************************************************ * THE CONTINUE HCUTINE IS USED TO CONTINUE * THAT IS TRANSMIT PARAMETER BYTE 3... * ilTH VERIFY Cmd.* * * ********************************************** ******** ****** CONTINUE: X ************** LXI MOV OUT aov PUSH BVI OUT BVI OUT NCP MVI CUT BVI CUT NOP avi OUT BVI OUT H,PRAM3 A,M 0E4H D,A ;LOAD ADD. PRAM3 IN HL REGS. ;MOVE PRAM3 VALUE TO ACCUM. ;PUT PRAM3 TO OUTPUT PORT D ;SAVE PRAM3 VALUE ;TURN ACK/ ON PORT B ;TURN ON DATA LINE ;TO CONT. PT. ;TIME DELAY CN THEN OFF ; PULSE ;THE DATA AND ;TURN OFF HSTR ONLY ;TO CONT. PT. ;TIME DELAY ;HSTR TO ;CCNTRCL PORT ;RESTORE ACK/ PORT B A.000H 0E5H A,004H 0E6H A.005H 0E6H A,004H 0E6H A.000H 0E6H A.004H 0E5H ******************************************** * * * COMMAND VERIFY FOR THIRD PARAMETER BYTE * * * *********************************************** *********** ORDY5: a VI OUT a vi CUT IN ANI CPI JNZ RSTR CMD. TO COMMAND PORT PULSE ON THEN OFF. .. READ STATUS BYTE MASK CRDY5 TRUE OR FALSE IS ORDY5 ?.. A.002H 0E6H A.000H 0E6H OEUH 002H 002H ORDY5 . *********************************************************** * * * IS DISK CONTROLLER READY FOR INPUT (IRDY4) ?... * * * *********************************************************** 61 IRDY4: MVI CUT HVI OUT IN ANI CPI JMZ A.002H 0E6H A.OOOH 0E6H OEUH 001H 001H IRDY4 PULSE RSTR CMD. TO CONTROL PORT TORN OFF RSTR PULSE READ IN STATUS BYTE MASK IRDY4 TRUE OR FALSE IS IRDY 4 ?.. ************************************************************ * * READ BACK PARAMETER BYTE * 3 * * * FOR VERIFICATION... ******* ** ****** ********************************************* HVI OUT NOP HVI OUT HVI CUT NCP MVI OUT IN A.004H 0E6H TURN ON DATA LINE TO CONT. PT. TIME DELAY RSTR 6 DATA PULSE READ BACK PRAM3 TURN OFF RSTR ONLY TC CONT. PT. TIME DELAY TURN OFF STROBE A.006H 0E6H A.004H 0E6H A,Q00H 0E6H 0E4H ;LOAD PBAM3 IN ACCUM.. *********************************************************** * * COMPARE PRAM. BYTE 3 WITH ORIGINAL PATTERN AND CONTINUE * * 4 OR TRANSMIT ERROR MSG. *, TO PARAMETER BYTE 4... * * *********************************************************** * POP CMP JNZ MOV DCR MOV CPI JZ MOV PUT PRAM3 IN D REGS. COMPARE TO ORIGINAL SEND ERROR MSG. 4.. SAVE PRAM3 IS THIS THE LAST PARAMETER BYTE ?.. IF SO GO TO BYTE.. OTHERWISE SAVE PRAM COUNT D D ERRHSG4 M, A B A.B 000H GOBYTE B,A *************************************************** * * * * * WRITE PARAMETER BYTE 4 CONTAINING STARTING SECTOR ADD. * * FOR INITIALIZATION THIS WILL ALWAYS BE ZERO... * *********************************************************** MVI CUT HVI OUT MVI OUT NCP MVI CUT MVI CUT ;LOAD PRAM4 (START SECT.) LOGICAL SECTOR ZERO ;TURN ACK/ ON PORT B TURN ON DATA LINE TO CONT. PT. TIME DELAY PULSE HSTR & DATA TO COMMAND PORT TURN OFF WSTR ONLY TO CONT. PT. A.000H 0E4H A.000H 0E5H A.004H 0E6H ; A,005H 0E6H A.004H 0E6H 62 NOP MVI COT MVI COT ;TIME DELAY ;TORN CFF POLSE TO ; COMMAND PORT ;RESTOBE ACK/ PORT B A,OOOH 0E6H A,004H 0E5H **** ************************************** **** ************* * * START CMD. VERIFICATION OF * STATOS BYTE.. . * PARAMETER BYTE 4 BY READING * * * * ********* ************************************************** ORDY6: MVI COT MVI OOT IN ANI CPI JNZ A.002H 0E6H A.000H 0E6H 0E4H 002H 002H ORDY6 RSTR CMD. TO COMMAND PORT POLSE ON THEN OFF READ IN STATOS BYTE MASK 0RDY6 TROE OR FALSE IS ORDY6 ?... *********************************************************** * * IS DISK * * * CCNTRCLLER READY FOR INPOT (IRDY5) ?... * *********************************************************** IRDY5: MVI OOT MVI OOT IN ANI CEI JNZ A,002H 0E6H A,O0OH 0E6H 0E4H 001H 001a IBDY5 POLSE RSTR CMD. TO CONTROL PORT TORN OFF RSTR POLSE READ IN STATOS BYTE MASK IRDY5 TROE OR FALSE IS IRDY5 ? *********************************************************** * * * READ BACK PARAMETER BYTE 4 FOR VERIFICATION * * * *********************************************************** MVI OOT NOP MVI OOT MVI COT NOP MVI COT IN TORN ON DATA LINE TO CONT. PT. TIME DELAY RSTR & DATA POLSE READ BACK PRAM4 TORN OFF RSTR ONLY TO CONT. PT. TIME DELAY TORN OFF STROBE... LOAD PRAM4 IN A,004H 0E6H A.006H 0E6H A,Q04H 0E6H A.OOOH 0E6H 0E4H *********************************************************** * * * COMPARE PARAMETER BYTE 4 WITH ORIG. PATTERN AND CONTINOE* * * TO PARAMETER BYTE 5... 5 OR TRANSMIT ERROR MSG. * * *********************************************************** 63 ANA JNZ DCR MOV CPI JZ MOV ;CCMPABE TO OHIG. VALUE ;PRINT ERROR MSG. ;IS THIS THE ;LAST PARAMETER BYTE ;IF SO ;GO TO GOBYTE ; OTHERWISE SAVE PRAM COUNT A ERRMSG5 B A.B 000H GOBYTE B,A *********************************************************** * * * WRITE PARAMETER BYTE 5 CONTAINING # OF SECTORS TO BE * * PROCESSED. FOB INITIALIZATION OF A COMPLETE TRACK A TIME* * THIS NUMBER WILL ALWAYS BE 00.... * * * *********************************************************** MVI OUT MVI CUT MVI OUT NOP MVI OUT MVI OUT NCP MVI CUT MVI CUT A,Q00H 0E4H A.000H 0E5H A,0C4H 0E6H ;LOAD PRAM 5 ;23D OUTPUT PORT ;TURN ACK/ ON PORT B ;TURN ON WSTR ;TO CONT. PT. ;TIME DELAY PULSE WSTR AND DATA ;TO COMMAND PORT ;TURN OFF WSTR ONLY ;T0 CONT. PT. ;TIME DELAY ;TURN CFF PULSE ;TO CMD. PORT ; RESTORE ACK/ PORT B A,005H 0E6H A.004H 0E6H ; A,000H 0E6H A,004H 0E5H *********************************************************** * * START CMD. VERIFICATION OF * STATUS BYTE... * PARAMETER BYTE 5 BY READING * * * * *********************************************************** ORDY7: MVI CUT MVI OUT IN ANI CPI JNZ RSTR CMD TO A.002H 0E6H A.000H 0E6H 0E4H 002H 002H ORDY7 PORT PULSE ON THEN OFF... READ IN STAT. BYTE MASK CRDY7 TRUE OR FALSE IS ORDY7 ?.. CMD. *************** ******************************* ****** ******* * * * IS DISK CCNTRCLLER READY FOR INPUT ? * * * *********************************************************** IRDY6: MVI OUT MVI OUT IN ANI CFI JNZ PULSE RSTR CMD. TO CONTROL PORT TURN OFF RSTR PULSE READ STAT. BYTE MASK IRDY6 TRUE FALSE IS IRDY6 ? A,002H 0E6H A.000H 0E6H 0E4H 00 1H 00 1H IRDY6 64 ******* ***************** ******** ********** ***************** * * * READ BACK PARAMETER BYTE 5 FOR VERIFICATION. * * * . *********************************************************** MVI OUT NOP MVI A.004H 0E6H GOT A.006H 0E6H A,Q0UH 0E6H NCP MVI OUT IN A,000H 0E6H 0E4H OUT MVI TURN ON DATA LINE TO CONT. PT. TIME DELAY RSTR & DATA PULSE READ BACK P3AM5 TURN OFF RSTR ONLY TO CONT. PT. TIME DELAY TURN OFF STROBE... LOAD ERAM5 ACCUM. *********************************************************** * * * COMPARE PARAMETER BYTE 5 WITH ORIG. PATTERN AND * TO PARAMETER BYTE 6 OR XMIT ERROR MSG 6.. * CONTINUE* * * *********************************************************** ANA JNZ DCR MOV CPI JZ MOV ;COMPABE TO ERR. MSG ; PRINT ;IS THIS THE ;LAST PRAM BYTE A ERRMSG6 B A.B OOOH GOBYTE B,A ;IF SO •SAVE PRAM CT. *********************************************************** HRITE PRAM. BYTE 6 CONTAINING NORMAL/SPARED TRACK AND DEFFECTIVE SECTOR ADDRESS. NORMALLY NOT USED BUT MUST BE XMITTED ANYSAY. CONTAINS ALL ZEROS * *********************************************************** MVI OUT MVI OUT MVI CUT NOP MVI CUT MVI OUT NOP MVI OUT MVI OUT ;LOAD PRAM6 ;TO OUTPUT PORT ;TURN ACK/ ON PORT B TURN ON HSTR TO CONT. PT. TIME DELAY PULSE WSTR AND DATA CMD. PT. TURN OFF HSTR ONLY TO CONT. PT. TIME DELAY TURN OFF PULSE CMD PORT TURN ACK/ ON PORT B A.024H 0E4H A, OOOH 0E5H A,004H 0E6H A.005H 0E6H A.004H 0E6H OOOH 0E6H A.004H 0E5H A, 65 ****************************************** ***************** * * * * * * COMMENCE COMMAND VERIFICATION OF PARAMETER BYTE 6 BY * READING STATUS BYTE... * ********************************************************* ORDY8: MVI OUT MVI CUT IN ANI CPI JNZ A.002H 0E6H A.000H 0E6H 0E4H 002H 002H ORDY8 ;RSTR CMD TO ;CMD. PORT ; PULSE CN ;TBEN OFF. ;READ STAT. BY ;MASK 0RDY8 ;TRUE OR FALSE ;IS ORDY8 ? .. *********************************************************** * * * IS DISK CONTROLLER READY FOR INPUT (IRDY7) * ?... ******* ****************************** ********************** IRDY7: IN ANI A.002H 0E6H A.000H 0E6H 0E4H 001H CPI JNZ IRDY7 MVI OUT MVI CUT PULSE RSTR CMD. TO CONT. PT. TURN OFF RSTR PULSE READ STATUS BYTE MASK IRDY7 TRUE OR FALSE IS IRDY7 ? 00 1H ********************************************************** * * READ * * BACK PARAMETER BYTE 6 FOR VERIFICATION... * * ********************************************************** MVI OUT NOP MVI OUT OUT A.006H 0E6H A,004H 0E6H NCP MVI CUT IN A.00OH 0E6H 0E4H MVI TURN ON DATA LINE TO CONI. PT. TIME DELAY RSTR S DATA PULSE READ BACK PRAM6 TURN OFF RSTR ONLY TO CONI. PT. TIME DELAY TURN OFF STROBE LOAD PRAM6 IN ACCUM. A.004H 0E6H *********************************************************** * * * COMPARE PARAMETER BYTE 6 WITH ORIGINAL PATTERN AND CONTINUE TO GO BYTE FOB EXECUTION OF INITIALIZATION... * * *********************************************************** * * * CPI JNZ CCR MOV CPI 024H ERRMSG7 B A.B OOOH 66 COMPAfiE TO ORIG. VALUE PRINT ERROR MSG. 7 IS THIS THE LAST PRAM BYTE ? IF SO JZ GOBITE ;GO TO GOBYTE ****************************************************** ****** * * * OUTPUT GO BYTE TO DISK CONTROLLER. THE GO BYTE CAUSES THE* * COMMAND TO BE EXECUTED AND MAY CONTAIN ANY VALUE. FOR * * SIMPLICITY THE GO BYTE WILL BE FFH. . . * * * ************************************************************ GOBYTE: MVI OUT MVI OUT MVI CUT NOP MVI OUT MVI OUT NOP MVI OUT MVI OUT A.OFFH 0E4H A,O0OH 0E5H A ( 004H 0E6H ;LOAD GO BYTE ;TO OUTPUT PORT ;TURN ACK/ ON PORT B ;TURN ON HSTR ;TO CONT. PT. ;TIME DELAY PULSE HSTR AND ;DATA TO CMD. PT. ;TURN OFF HSTR ONLY ;TO CONT. PT. ;TIME DELAY ;TURN OFF PULSE ;TO CMD. PT. ;RESTORE ACK/ PORT B A.005H 0E6H A,004H 0E6H ; A.000H 0E6H A, OOUH 0E5H *********************************************************** * * * THE HAIT STATUS MODULE IS USED TO READ BACK TERMINATION * * BYTE. TERMINATION STATUS IS ACCESSED BY READING FROM * * * * THE CONTROLLER DATA PORT IN RESPONSE TO ATTN TRUE, USING* * THE TERMINATION PROTOCOL.... *********************************************************** CBUSY2: MVI OUT MVI OUT IN ANI CPI JNZ RSTR CMD. TO CONT. PT. STROBE OFF.. 002H 0E6H A-000H 0E6H OEUH 010H 010H CBUSY2 Ar READ STATUS BYTE IS CBOSY TRUE ? OR FALSE ? CONTROLLER BUSY GO BACK, *********************************************************** * * * * (IRDY8).* * ********************************** ******************* ****** READ STATUS BYTE TO SEE IF INPUT BUFFER READY IRDY8: MVI OUT MVI OUT IN ANI CPI JNZ ? PULSE RSTR CMD. TO CONT. PT. TURN OFF RSTR PULSE READ STATUS BYTE MASK IRDY8 A,002H 0E6H A.000H 0E6H 0E4H 00 1H 00 1H IS IRDY8 IRDY8 67 ? **************************** *********************** ******** * * * READ FROM CONTROLLER DATA PORT THE TERM. STATOS BYTE. DETERMINE ERROR CONDITIONS THAT HAVE OCCURRED DURING THE* COMMAND EXECOTION. THE CODE IN BITS 0-3 INDICATE REASON * * * FOR TERMINATION.... * * * * * *********************************************************** MVI OOT NOP MVI OOT MVI COT NOP MVI OOT IN ANA JNZ J MP ERRMSG1 START1 ERRMSG2; START2: LXI MVI MOV START4: ERRMSG5 ; A.OOOH 0E6H 0E4H ; ; A ; ERRMSG8 INTVFY ERROR 1 B.35D H, D.fi B CALL LXI MVI MOV CALL DCR JZ INX JMP ERRMSG4 ; CONOOT JMP START3: A.006H 0E6H A.004H 0E6H DCR JZ INX JMP LXI MVI MOV LXI MVI MOV CALL TORN ON DATA LINE TO CONT. PT. TIME DELAY RSTR & DATA ; PULSE CONT. PT. ; TO TORN OFF RSTR ONLY TO CONT. PT. TIME DELAY TORN OFF RSTR 6 DATA.. IN TER. STAT. BYTE ; READ MASK TER. STAT. FOR ERROR PRINT ERROR MSG. TO BEGINNING ; RETORN ; caLL DCR JZ INX ERRMSG3 A.004H 0E6H EXIT H STABT1 H,EEROR2 B,33D D.M CONOOT B EXIT H STABT2 H,ERfiOR3 BJ33D D.H CONOOT B EXIT H STABT3 H,EEROR4 B,33D D.M CONOOT DCR JZ INX JMP B LXI MVI H, EXIT H START4 ERRORS B,33D 68 ; STARTS: MOV CALL DCR JZ INX JMP • 9 ERRMSG6: LXI MVI MOV CALL DCR JZ INX START6: D,M CONOOT B EXIT a STARTS H,ERROR6 B,33D D,M CONOOT B EXIT H J MP START6 LXI MVI H, ERROR7 B,33D D,M CONOOT • • ERRMSG7: START7: MOV CALL DCR JZ INX J MP B EXIT H START7 • 9 • ERRMSG8: LXI MVI MOV CALL DCR JZ INX START8: H,ERROR8 B.34D D.M CONOOT B EXIT H STARTS J MP • 9 • EXIT: NOP NOP LXI MVI MOV START9: H £ COMP B,33D D.M CONOOT CALL DCR JZ INX JMP FINISH IN ANI CPI JNZ MOV OOT RET OEDH 00000001B 00000001B CONOOT A,D OECH B H START9 • 9 • CONOOT: PRAM2: DB PRAM3: DB E3R0R1: DB •COMMAND BITE RECEIVED IN ERROR. . ERROR2: DB «PRAM1 BYTE RECEIVED IN ERROR. ..• .» , ,0DH, OAH ODH , OAH ERROR3: DB PRAM2 BYTE RECEIVED IN ERROR. ..«, ODH, OAH ERRORS: DB *FRAM3 BYTE RECEIVED IN ERROR. ..», 0DH # OAH • 69 ERR0B5: DB PRAM4 BYTE BECEIVEO IN ERROR. . . • , ODH, OAH ERROR6: DB • PRAMS BITE RECEIVED IN ERROR. ..», ODH, OAH ERROR7: DB • PRAM6 BITE RECEIVED IN ERROR. ..», ODH, OAH ERROR8: DB 'TERMINATION STATUS BITE ERROR. ..» ,ODH, OAH COMP: FINISH: DB 'THIS COMPLETES INTVFI OF DISK. NOP NOP RST . . ;END INTVFI PGM 1 70 • ,ODH # OAH APPENDIX B ORG 3000H * * THIS IS A SUBROUTINE TO EITHER READ OR WRITE TO THE * MICROPOLIS 1223-1 HARD DISK DEPENDING ON THE COMMAND * BITE. IF THE COMMAND BYTE IS A 4EH IT IS A READ COM* HAND OR U7H FOR A WRITE COMMAND * * * * * * * *********************************************************** NOP NOP ****** * ******** * ************************** **************** * * INITIALIZE CONDITIONS BY PROGRAMING 8255 TO MODE 2, * CLEARING ACCUMULATOR, SETTING ACK/ ON AND SETTING * PARAMETER COUNTER TO 6 . . * * * * * * ********************************************************** A.001H 0E5H HVI READRITE: OUT SUB ADI MOV MVI CUT MVI CUT 6 ;SET DISK CONTROLLER ;ENABLE PT.B ;CLEAB ACCUM. ;LOAD PRAM CT. B,A A,0C0H 0E7H A-005H 0E5H ;MODE TWO ;TURN ON ACK/ PORT B A ;PGM. 8255 ********************************************************** * * READ STATUS BYTE AND MASK TO SEE IF DISK CONTROLLER * IS NOT BUSY (CBUSY=1). FOLLOW BY CHECKING TO SEE IF * HOST MAY SEND COMMAND BYTE (ORDY-1).... * * * * * * ********************************************************** CALL CALL CEUSY ORDY BUSY? ;READY FOR CMD? ;IS CONT. ********************************************************** * * * LOAD READ CR WRITE COMMAND BYTE INTO DISK CONTROL PORT.* * * ********************************************************** LXI MOV OUT MOV PUSH MVI OUT MVI H,CMD A.M 0E4H D.A 5 A,001H 0E5H A,001H ;ADD. OF CMD BYTE ;MOVE CMD TO ACCUM. ;PUT CMD TO OUT PT. ;SAVE ORIG. ;CMD. BYTE ;TURN ACK/ ON PORT B ;STROBE RSTR ON 71 OOT MVI OOT MVI OUT 0E6H A.000H 0E6H A,005H 0E5H ;TO CONT. PT. ; HSTR OFF ;TO CONT. PT. ; RESTORE ACK/ ON POBT B ******* ************************* **************** *********** * * COMMENCE COMMAND VERIFICATION BI BEADING STATUS BYTE * FOB OBDY & IBDI. .. * * * * *************** ************************************ ******** CALL CALL ORDI IRDY BEADY FOB CMD? ;CMD BEADY FOB BEAD BACK ; *************** ******************************************* * * COMPARE RECEIVED COMMAND BTYE HITH ORIGINAL PATTERN * TO VERIFY CORRECTNESS... * * * * * ********************************************************** MVI OUT MVI OOT MVI OOT MVI OOT A.004H 0E6H A.006H 0S6H A.004H 026H A.000H 0E6H 0E4H IN POP D CMP JNZ POSH ERRMSG1 D D TORN DATA POLSE ON TO CONT. PT. TORN ON BSTR & DATA TO CONT. PT. TORN OFF RSTR ONLY TO CONT. PT. TORN OFF DATA TO CONT. PT. READ IN CMD. LOAD ORIG. IN D COMPARE COMMANDS FAIL? PRINT MSG 1 SAVE FOR RD WR DECISION ********************************************************** * * WRITE PARAMETEB BYTE * OOTPOT TO DATA PORT... * 1 CONTAINING HEAD ADDBESS AND * * * ********************************************************** LXI MOV OOT MOV POSH MVI OOT MVI OOT MVI OOT MVI OOT MVI OOT MVI OOT H,PRAM1 A.M 0E4H V A.001H 0E5H A.004H 0E6H A.005H 0E6H A,004H 0E6H A,OOOH 0E6H A.005H 0E5H LOAD ADD. OF HEAD PRAM1 VALOE TO ACCOM. OOTPOT PBAM1 TO DATA PT. SAVE PRAM1 BYTE ON STACK TORN ACK/ ON PORT B TURN ON DATA LINE TO CONT. PT. STROBE HSTB ON TO CONT. PT. TOBN OFF BSTB ONLY TO CONT. PT. TOBN OFF DATA LINE TO CONT. PT. RESTORE ACK PORT B... 72 ******************* ******************************** ******* * * COMMENCE PARAMETER 1 VERIFICATION BY READING STATUS * BTYE FOR ORDY 6 IRDY.. * * ********************************************** ************ * * * CALL CALL ORDY IRDY HOST HAY SEND FRAM2 ;PRAM READY TO READ BACK ; ********************************************************** * * READ * BACK PARAMETER BYTE 1 FOR VERIFICATION... * * ********************************************************** MVI OOT MVI OOT MVI OOT MVI OOT IN POP CMP JNZ DCR JZ A.OOUH 0E6H A, 006H 0E6H A,004H 0E6H A,000H 0E6H 0E4H D D ERRHSG2 B GOBYTE TORN ON DATA STROBE TO CONT. PT. TORN ON RSIR & DATA TO CONT. PT. TORN OFF RSTR ONLY TO CONT. PT. TORN OFF DATA STROBE TO CONT. PT. LOAD PBAM1 ACCOM. LOAD ORIG. PRAM1 IN COMPARE PRAMS FAILED? PRINT MSG. DCR PRAM COONT LAST PRAM END PGM. I ********************************************************** WRITE PARAMETER BYTE 2 CONTAINING LSB OF CYLINDER ADDRESS AND OOTPOT TO DATA PORT. IF PARAMETER 2 IS IN OVERFLOW CONDITION CARRY OVER TO PARAMETER BYTE AND CONTINOE WITH EXECOTION... LXI MOV OOT MOV POSH MVI OOT MVI OOT MVI OOT MVI OOT MVI OOT MVI OOT H,PRAM2 A,M 0E4H D,A D A,001H 0E5H A,004H 0E6H A,005H 0E6H A,004H 0E6H A.OOOH 0E6H A,005H 0E5H 3 * * * * * LOAD ADD. PRAM2 MOVE PRAM2 VALOE TO OOTPOT PORT SAVE PRAM2 VALOE IN STK. TORN ACK ON PORT B TORN ON DATA LINE TO CONT. PT. TORN ON DATA & WSTR TO CONT. PT. TORN OFF WSTR ONLY TO CONT. PT. TORN OFF DATA STROBE TO CONT. PT. RESTORE ACK PORT B ********************************************************** * * * * COMMENCE COMMAND VERIFY FOR PARAMETER BYTE 2... * * ********************************************************** 73 CALL CALL OHDY IBDY HOST MAI SEND PRAM 3 ;PRAM2 BEADY TO HEAD BACK ; ********************** 4*********** ************************ * * * READ BACK PARAMETER BYTE * 2 FOR VERIFICATION... a******************************************************,,** MVI OOT MVI OOT MVI OOT MVI OOT IN A,004H 0E6H A,006H 0E6H A.004H 0E6H A,000H 0E6H 0E4H TORN ON DATA SIROBE TO CONT. PT. RSTR & DATA ON TO CONT. PT. TORN OFF RSTR ONLY TO CONT. PT. TORN DATA OFF TO CONT. PT. ;LCAD IN PEAM2 ********************************************************** * * COMPARE PARAMETER BYTE 2 WITH ORIGINAL VALOE. * CHECK FAILS PRINT ERROR MSG. 3... * IF * * * * ****x********** ******************************* ************ POP CMP JNZ INR D D JC MOV DCR JZ CARRY JMP GET PRAM2 VALOE COMPARE TO ORIG. FAILED? SEND MSG. CHG. TO NEXT TRACK OVERFLOW TO PRAM 4 OTHERWISE SAVE PRAM2 IS THIS LAST PRAM? ERRMSG3 A M, B GOBYTE CONTINOE IF SO END PGM. OTHERWISE CONTINOE .A****************************************.*************** * * THE CARRY ROOTINE IS OTILIZED IF PARAMETER BYTE 2 IS * IN OVERFLOW CONDITION TO INCREMENT PARAMETER BYTE 3.. * * * * * ********************************************************** CARRY: ;LOAD ADD. PRAM3 ;PRAM VALUE TO ACCUM. {INCREMENT PRAM3 579 ;IS THIS TRACK ;IF SO END PGM. ;SAVE NEW PRAM3 BYTE H,PRAM3 A,M LXI MOV INR CPI JZ MOV A 002H EXIT H,A ********************************************************** * * THE CONTINOE ROOTINE IS USED TO CONTINOE WITH READ * WRITE COMMAND. THAT IS TRANSMIT PARAMETER BYTE 3 * * * * * ********************************************************** CONTINOE; LXI MOV H,PRAM3 A,M 74 ;LOAC ADD. PRAM3 ;MOVE PRAM3 VALOE OOT MOV POSH 0E4H MVI OOT HVI OOT MVI OOT HVI OOT MVI OOT MVI OOT A.0O1H 0E5H A.004H 0E6H A,005H 0E6H A.004H 0E6H A,OOOH 0E6H A.005H 0E5H D, A ;POT PRAM3 OOTPOT PT, ;SAVE PRAM 3 :BYTE ;TURN ACK ON POET B TORN ON DATA STROBE TO CONT. PT. TORN ON WSTB & DATA TO CONT. PT. TORN OFF »STR ONLY TO CONT. PT, TORN OFF DATA STROBE TO CONT. PT. RESTORE ACK PORT B * * * COMMENCE VERIFICATION OF PARAMETER BYTE 3.... * * ********************************************************** * CALL CALL * CBDY IRDY HOST MAY SEND PRAM 4 ;PRAM3 READY FOR READ BACK ; ************** *************************** ********* ******* * * READ BACK PARAMETER BYTE * * * FOR VERIFICATION... * *************** ******************************************* MVI OOT MVI OOT HVI OOT HVI OOT IN A,004H 0E6H A.006H 0E6H A,004H 0E6H A.000H 0E6H 0E4H 3 TORN ON DATA LINE TO CONT. PT. TORN ON RSTR & DATA TO CONT. PT TORN OFF RSTR ONLY TO CONT. PT. TORN OFF DATA LINE TO CONT. PT. LOAD IN PRAM3 ********************************************************** * * COMPARE PARAMETER BYTE 3 MITH ORIGINAL PATTERN AND * CONTINOE TO PARAMETER BYTE 4 4 OR PRINT ERROR MSG. * IF CHECK FAILS... * * * * * * ********************************************************** POP CMP JNZ HOV DCR JZ D D EBRMSG4 H,A B GOBYTE POT ORIG, PRAM3 IN COMPARE TWO VALOES EAILED? PRINT MSG. SAVE PRAM 3 VALOE DCR PRAM COONT IS THIS THE LAST PRAM? ********************************************************** * * WRITE PARAMETER BYTE * ADDRESS... * * 4 CONTAINING STARTING SECTOR * * * ********************************************************** 75 LXI MOV OUT MOV POSH MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OCT H,PRAM4 A,M 0E4H D,A D A,001H 0E5H A,004H 0E6H A-005H 0E6H A, 004H 0E6H A.000H 0E6H A.005H 0E5H LOAD ADO. FEAM4 POT PRAM4 VALOE IN ACCOM. PBAM4 OOT TO OOTPOT PT. SAVE PRAM4 BYTE TORN ACK OH PORT B TORN ON DATA LINE TO CONT. PT. POLSE HSTR & DATA ON TO CONT. PT. TORN OFF HSTR ONLY TO CONT. PT. TORN OFF DATA LINE TO CONT. PT. RESTORE ACK PORT B ********************************************************** * * * * COMMENCE VERIFICATION OF PARAMETER BYTE 4 BY READING * * STATOS BYTE FCR ORDY & IRDY... * *************** * ****** ********** ************************** CALL CALL ORDY IRDY ;HOST MAY SEND PRAM 5 ;PRAM4 READY TO READ BACK ********************************************************** * * * READ BACK PARAMETER BYTE 4 FOR VERIFICATION * * ********************************************************** MVI OOT MVI OOT MVI OOT MVI OOT IN A,004H 0E6H A.006H 0E6H A.004H 0E6H A.000H 0E6H 0E4H TORN ON DATA LINE TO CONT. PT. TORN RSTR & DATA ON TO CONT. PT. TORN OFF RSTR ONLY TO CONT. PT. TORN OFF DATA TO CONT. PT. READ IN PRAM4 ********************************************************** * * * COMPARE PARAMETER BYTE 4 WITH ORIGINAL PATTERN AND CONTINOE TO PARAMETER BYTE 5 OR IF FAIL PRINT MSG 5. * ********************************************************** * * POP CMP JNZ DCR JZ D D ERRHSG5 B GOBYTE RECALL ORIG. PRAM COMPARE TWO VALOES BAILED? PRINT MSG. DETERMINE PRAM CT. IF LAST PRAM 76 *************** ******************************************* * * WRITE PARAMETER BYTE 5 CONTAINING NUMBER OF SECTORS * TO BE PROCESSED. FOR THIS PARTICULAR CASE THIS SYSTEM * WILL ONLY WRITE OR READ ONE SECTOR AT A TIME THERE* FORE PRAM5=001H * * *** *** ******** MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT * * * * * * ********* ********************************** A,001H 0E4H A,001B 0E5H A,004H 0E6H A,005H 0E6H A,004H 0E6H A,000H 0E6H A.005H 0E5H LOAD PRAM5 TO OUTPUT PT. TURN ACK ON PORT B TURN ON DATA LINE TO CONT. PT. WSTR & DATA ON TO CONT. PT. TURN OFF WSTR ONLY TO CONT. PT. TURN OFF DATA LINE TO CONT. PT. RESTORE ACK PORT B ********************************************************** * * COMMENCE VERIFICATION OF * STATUS BYTE * PARAMETER BYTE 5 BY READING * * ********************************************************** CALL CALL * ORDY IRDY HOST MAY SEND PRAM6 ;PRAM READY TO BEAD BACK ; ************** ******************************************* * * * READ BACK PARAMETER BYTE 5 FOR VERIFICATION * * * ********************************************************** MVI OUT MVI OUT MVI OUT MVI OUT IN A.004H 0E6H A.006H 0E6H A.004H 0E6H A,000H 0E6H 0E4H TURN ON DATA LINE TO CONT. PT. RSTR & DATA ON TO CONT. PT. TURN OFF RSTR ONLY TO CONT. PT. TURN OFF DATA LINE TO CONT. PT. READ IN PRAM5 ********************************************************** * * COMPARE PARAMETER BYTE 5 WITH ORIGINAL PATTERN AND * CONTINUE TO PARAMETER BTYE 6 OR IF FAILED PRINT ERROR * MSG 6 * * * * * * ********************************************************** ANI CPI JNZ ;COMPARE 001H ;TO ORIG. VALUE 001H EBRMSG6 ;FAIL? PRINT MSG 77 DCB JZ B GOBYTE ;DCR PRAM CT ;LAST PRAM EXECUTE PGM. ***********************************************+********+* * * * * * * WRITE PARAMETER BYTE 6 CONTAINING NORMAL/SPARED TRACK * AND DEFFECTIVE SECTOR ADDRESS. NORMALLY NOT USED BUT * MUST BE TRANSMITTED ANYWAY. CONTAINS ALL ZEROS * * ********************************************************** MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT A.025H 0E4H A.001H 0E5H A,004H 0£6H A.005H 0E6H A,004H 0E6H A,000H 0E6H A.005H 0E5H ;LOAD PRAM6 ;TO OUTPUT PT. ;TURN ACK ON PORT B ;TURN ON WSTR ;TO CONT.PT. ;TURN WSTR & DATA ON ;TO CONT. PT. ;TURN WSTR OFF ;TO CONT.PT. ;TURN OFF DATA ;TO CONT.PT. ;RES10fiS ACK PORT B *** *** **** **i****M**M*Mt***$***V*** **** ************ * * COMMENCE VERIFICATION OF PARAMETER BYTE * STATUS BYTE FCR ORDY & IRDY * CALL CALL * *** * * * ORDY IRDY 6 BY READING * * * * ;HOST MAY SEND GC BYTE ;PRAM6 READY TO SEND BACK ****************** ************************************ READ BACK PARAMETER BYTE 6 FOR VERIFICATION * * * ********************************************************** MVI OUT MVI OUT MVI OUT MVI OUT IN A,004H 0E6H A,006H 0E6H A.004H 0E6H A.000H 0E6H OEUH TURN ON DATA LINE TO CONT.PT. TURN DATA RSTR ON TO CONT.PT. TURN OFF RSTR ONLY TO CONT.PT. TURN OFF DATA LINE TO CONT.PT. READ IN PRAM6 ********************************************************** * * COMPARE PARAMETER BYTE 6 WITH ORIGINAL PATTERN AND 7... * CONTINUE TO GO BYTE OR IF FAIL PRINT ERROR MSG. * * * * * ********************************************************** CPI JNZ ;CCMPARE TO 24 025H ERRMSG7 ;FAILED? PRINT MSG, 78 DCR JZ B GCBYTE ;IS THIS LAST ;YES GO TO EXECUTION **************************** *** *** ******** **** ******** ** ** * * * * OUTPUT GO BYTE TO DISK CONTROLLER. THE GO BYTE CAUSES * THE COMMAND TO BE EXECUTED AND MAY CONTAIN ANY VALUE. * * FOB SIMPLICITY THE GO BYTE WILL BE FFH * * * ********************************************************** GOBYTE: MVI OOT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT A.OFFH 0E4H A.001H 0E5H A,004H 0E6H A-005H 0E6H A,004H 0E6H A.000H 0E6H A-005H 0E5H ;LOAD GO BYTE ;TO DATA POST ;TURN ACK ON PORT B TURN DATA PULSE ON TO CONT. PT. TURN ON WSTR TO CONT.PT. TURN HSTR OFF TO CONT.PT. TURN DATA OFF TO CONT.PT. RESTORE ACK PORT B ******************************** ************** * *********** * * * THE DECISION 80UTINE DETERMINES IF THE COMMAND WAS A * READ OR WRITE. IT THEN PASSES CONTROL OVER TO THE AP* PROPRIATE MODULE FOR EXECUTION * * * * * ********************************************************** POP MOV CPI JZ RECOVER CMD. BYTE ;MOV CMD. TO ACCUM. ;TEST FOR WRITE CMD. ;GO TO WR. MODULE D ; A,D 047H WRITE ********************************************************** * * THE READ MODULE READS THE STATUS BYTE AND DETERMINES * IF DATA IS REQUSTED OR ATTENTION IS TRUE. IF SO DATA * PORT PUTS BYTE TO DATA BUFFER. (FOR DEMONSTRATION THIS * DATA WILL EE PRINTED TO MONITOR CRT. .) * * * * * * * ********************************************************** READ: LXI LXI CALL MVI OUT avi OUT MVI OUT MVI OUT IN MOV MOV CALL B,200H H,TABLE1 STATUS A,004H 0E6H A.006H 0E6H A,004H 0E6H A.OOOH 0E6H 0E4H M,A IS CONTROLLER BUSY? TURN ON DATA LINE TO CONT. ET. TURN ON RSTR & DATA TO CONT.PT. TURN RSTR OFF TO CONT.PT. TURN OFF DATA LINE TO CONT.PT. ;READ IN DATA BYTE D, A CONOUT 79 INX DCS JNZ DCB C JZ EXIT BEAD H BEAD B JHF ;GET NEXT BYTE ********************************************************** * * * THE WBITE HODOLE BEADS STATUS BYTE AND DETEBMINES IF IF DATA BEQOEST OB ATTENTION BITS ABE SET TO ONE. IF * SO GETS DATA FBOM EUFFEB AND WBIIES TO DATA POBT.... * * * * ***************************** ***************** ************ WBITE: CALL LXI MOV OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT INB JHF STATUS H,PBOG A,M 0E4H A.001H 0E5H A,004H 0E6H A-005H 0E6H A.004H 0E6H A-000H 0E6H A,005H 0E5H M HBITE IS CBOSY? LOAD PGM ADD NEXT BYTE OUT PGM BYTE TUBN ACK ON POBT B TUBN ON DATA LINE TO CONT.PT. TUBN WSTB 6 DATA ON TO CONT.PT. TUBN OFF HSTB ONLY TO CONT.PT. TUBN OFF DATA LINE TO CONT.PT. BESTOBE ACK POBT E ADD. NEXT BYTE GET NEXT BYTE ********************************************************** * THE WAIT STATUS MODULE IS USED TO BEAD BACK TEBMINATION BYTE. THIS BYTE IS ACCESSED BY BEADING FBOM THE CCNTBOLLEB DATA POBT IN BESPONSE TO ATTN=1, USING TEBMINATION PBOTOCOL * * * * * ********************************************************** WAIT: WAIT1: MVI LXI CALL CALL MVI OUT MVI OUT MVI OUT MVI OUT IN MOV INX DCB JZ JMP NOP NOP EST 3,0OCH TABLE CBUSY IBDY A-004H 0E6H A.006H 0E6H A.004H 0E6H A.000H 0E6H 0E4H a, IS CONTBOLLEB BUSY? TEB. STAT. BYTE BEADY? TUBN ON DATA LINE TO CONT.PT. TUBN ON BSTB & DATA TO CONT.PT. TUBN OFF BSTB ONLY TO CONT.PT. TUBN OFF DATA TO CONT.PT. BEAD IN TEB. STAT. BYTE M, A H B EXIT WAIT1 ;TO CALLING FBOGBAM 80 *****x* *********************************** **************** * * * * * * * THE CONTROLLER BOSY SOBBCOTINE IS OSED TO DETEBMINE IF * THE DISK CONTROLLEB IS BUSY (CBOSY^O) . IF CONTBOLLEB * IS NOT BUSY CCNTBOL IS HETOBNED TO MAIN PROGBAM AND * EXECUTION CONTINUES * * ********************************************************** CBOSY: CBOSY1 POSH POSH POSH POSH MVI OOT MVI OOT E D H PSH A.002H 0E6H A.000H 0E6H 0E4H IN ANI CPI JNZ POP POP POP POP BET 01 OH 010H CB0SY1 PSH SAVE THE CONTENTS OF ALL BEGISTEBS BSTB ON TO CONT. POBT BSTB OFF TO CONT. PI. BEAD STATOS WORD DOES CBOSY-1 OB NOT GO BACK IF SO H D B ******* ****** ************************************** ******* * * * THE O0TP0T BEADY SOBBOOTINE IS OSED TO DETEBMINE IF * THE DISK CONTBOLLEB IS BEADY TO BECEIVE A WORD FROM * THE HOST COMPOTES * * * * * M ************************************ ********************* ORDY: POSH POSH POSH POSH B D H OBDY1 M7I OUT MVI OOT IN ANI A-002H 0E6H A,000H 0E6H 0E4H 002H 002H OBDY1 CPI JNZ POP POP POP POP PSH SAVE THE CONTENTS OF ALL BEGISTEBS BSTB ON TO CONT.PT. BSTB OFF TO CONT. PT. READ STATOS HORD DOES OBDY=1? TROE OB FALSE? BOFFEB EMPTY PSW H D B RET ************* ********************************************* * * THE INPOT READY SUBROOTINE IS TO DETERMINE IF THE DISK * CONTROLLER HAS A BYTE READY TO BE INPOT TO THE HOST... * * * * * A***-***************************************************** IRDY POSH POSH PUSH B D H ;SAVE THE ;CONTENTS ;OF ALL 81 IHDY1: PUSH PSW MVI OUT MVI OUT IN ANI A £ 002H 0E6H A.000H 0E6H 0E4H 001H 001H IBDY1 PSW CPI JNZ POP POP POP POP RET REGISTERS TORN RSTR ON TO CONT. PT. TURN RSTR OFF TO CONT. PT. READ IN STATUS BYTE MASK IRDY FOR IRDY=1 IF NOT READY GO BACK B D B **** ******************************************** ********** * * * * THE STATUS SUBROUTINE DETERMINES IF ATTENTION OR DATA REQUEST BITS ARE SET... * * * * ********************************************************** STATUS: STATUS1 ERRMSG1 START1 ERRMSG2: START2: POSH PUSH PUSH POSH MVI OUT MVI OUT IN MOV MVI ANA CPI JZ MVI ANA JNZ POP POP PCP POP RET LXI MVI MOV CALL B D H PSW A.002H 0E6H D RSTR ON TO CONT.PT. RSTR OFF TO CCNT. ET. READ STAT. BYTE SAVE BYTE LOAD MASK PERFORM TEST 080H WAIT A,020B IF TRUE GO TO WAIT LOAD MASK A,000H 0E6H 0E4H D,A A,080H D STAT0S1 PSW ;GO BACK OTHERWISE H D B H,ERROR1 B,35D D.M CONOUT DCR B JZ EXIT I NX H J MP START1 LXI MVI MOV H,ERROR2 B,33D D.M CONOUT CALL DCR JZ INX EXIT J MP START2 B H 82 ERRMSG3 I XI START3: HVI MOV 3BRHSG4 START4: CALL H,EHBOR3 B,33D D.M CONOOT DCR JZ EXIT I NX J UP START3 LXI HVI MOV CALL DCR JZ ERRMSG5 STARTS: ERRHSG6 START6: ERRMSG7: START7: START9: B EXIT H STABT4 LXI HVI MOV CALL ECR JZ INX JMP H,ERBOR5 B,33D D.M CONOOT LXI HVI HCV H,ERROR6 B,33D CALL CONOOT DCR JZ INX EXIT E EXIT H STARTS D.M B H J MP START6 LXI HVI HOV H,ERROR7 E,33B D.M CONOOT LXI HVI HOV CALL DCR JZ INX J HP EXIT: H,ERR0R4 B,33D D.M CONOOT J HP DCR JZ INX J MP START8: H I NX CALL ERRHSG8: B NOP NOP LXI HVI HOV CALL DCR JZ INX E EXIT H START7 H,ZRROR8 B,34D D.M CONOOT B EXIT H START8 H,COHP B,34D D,H CONOOT B FINISH a 83 JMP CONOOT: IN STABT9 OEDH ANI 00000001E 0O0O0001B CONOOT CPI JNZ MOV OUT RET A,D OECH CMD: DB OOEH PRAM1: DB 00H PRAM2: DE OOB PRAM3: DB OOH PRAM4: DB 00H ERROR1 DB ERROR2 DB ERROR3 DB ERRORU COMMAND BYTE RECEIVED IN ERROR. PRAM1 BYTE RECEIVED IN ERROR... . »,ODH,OAH ,0DH,0AH DB PRAM2 BYTE RECEIVED IN ERROR... PRAM3 BYTE RECEIVED IN ERROR... ,0DH,0AH ERRORS DB PRAM4 BYTE RECEIVED IN ERROR... ,0DH,0AH ERROR6 DB PRAM5 BYTE RECEIVED IN ERROR... ,GDH,0AH ERROR7 DB PRAM6 BYTE RECEIVED IN ERROR... ,0DH,0AH ERROR8 DB •,0DH,0AH COMP: DB TERMINATION STATUS BYTE ERROR.. THIS COMPLETES RD/HR CMD TABLE: TABLE1: PROG; DS DS DB ,0DH,0AH 1 ,0DH,0AH 12 512 00 ********************* * **** ****** ********** **************** * * THE FINISH ROUTINE PROVIDES A PROGRAMMED RESET FOR * THE DISK CONTROLLER WHICH AUTOMATICALLY INITIALIZES * THE CONTROLLER AFTER EXECUTION OF EACH COMMAND... * * * * * * ********************************************************** FINISH: MVI OUT MVI OUT NOP RST PULSE ENABLE A.000H 0E5H A.001H 0E5H ON PT. B TURN OFF ENABLE PORT 1 84 B LIST OF REFERENCES 1. Tanenbaua, A.S., Computer 1981 2. Burton, T., 1223 Rigid Disk B, Harch, 1981 Rev. 85 Networks f Prentice Hall, Drive Reference Manual , BIBLIOGRAPHY Burton, T.. Hicrcpolis November 1980 Dempsey.J. A., appl irafmns f Installation fosic Digital-Addison Wesley, 1979 Guidelines SleCtEOBJCS Manual. KJJJl Leventhal,!. A., Introduction to Mi croprocessors: Hardware. Programming . Prentice-Hall. 1 378 Intel 8080 Microcomputer Systems User's Guide. September, 1975 Software. Intel Corp., Intel OEH Computers . Intel Corp., November, 1977 Intellec Hardware Reference Manual . Intel Corp. 86 2121 , 1967 INITIAL DISTRIBUTION LIST No. 1. Library, Code 0142 Copies 2 Naval Postgraduate School Monterey, California 93940 2. Department Chairaan, Code 62 Depart aent of Electrical Engineering 1 Naval Postgraduate School Monterey, California 93940 3. Dr. M. L. Cotton, Code 62Cc 2 Departaent of Electrical Engineering Naval Postgraduate School Montrery, California 93940 4. Dr. Rudy Panholzer, Code 62Pz 1 Deparaent of Electrical Engineering Naval Postgraduate School Monterey, California 93940 5. Dr. Dno R. Kcdres, Code 52Kr 1 Departaent of Electrical Engineering Naval Postgraduate School Monterey, California 93940 6. LT. William H. Brown, 0SN 1 386A Bergin Dr. Montrery, Califirnia 93940 87 SPECIAL DISTRIBUTION Brown A design of a har d disk interf nte rface for f-h Q mxcro P oli s 1223-1. • — Thesis B823445 c.l IS Brown A design of a hard disk interface for the micropolis 1223-1. r mm mm 1 g ,,.»„ ° T a nard dlsk interface for th SWSSR 3 2768 001 01884 9 DUDLEY KNOX LIBRARY WmSSRh Si IB mmM '•''. ;•:: 1 [U? . •'•.. WM— Mr P&Hfc HfflV v 'M ':i: wu vfoHrSRS? 1 ' . ii ' ' rawmfTOiua m § ••«;',! 'WcMfl'tyf WMHH :