A Low Power 1mbit Mram Based On 1t1mtj Bit Cell Integrated With

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A Low Power 1Mbit MRAM based based on 1T1MTJ Bit Cell Integrated with Copper Interconnects M. Durlam, P. Naji, A. Omair, M. DeHerrera, J. Calder, J. M. Slaughter, B. Engel, N. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. Kyler, J. J. Ren, J. Molla, B. Feil, R. Williams, S. Tehrani Motorola Semiconductor Products Sector and Motorola Labs Tempe, Arizona 85284 This work supported in part by DARPA June 12, 2002 VLSI 2002 c12p4 1 Outline • Overview of MRAM Technology • Attributes and operation principle • 1Mb MRAM process • Cu metal interconnect • Magnetic Cladding • 1Mb circuit • Memory organization • Reference cell • Read circuitry • Summary June 12, 2002 VLSI 2002 c12p4 2 MRAM Attributes • MRAM offers multiple memory capabilities that are currently realized by separate memories. • Non-Volatility of Flash with fast programming, no program endurance limitation, and byte programmable • Density competitive with DRAM with no refresh refresh • Speed competitive with SRAM (except the fastest) at fraction of the cell size • Nondestructive read • Immunity of bits to soft error June 12, 2002 VLSI 2002 c12p4 3 Memory Cell - 1Transistor 1Magnetic Tunnel Junction (MTJ) 0.6x1.2µm bit at 300mV bias Bit Line 11 i Magnetic Field Flux concentrating cladding layer Di g MTJ it Li ne i RA (KΩ µm2) 10.5 10 9.5 9 MR=37% 8.5 8 7.5 Inlaid Copper interconnects -10 -7.5 -5 -2.5 0 2.5 5 7.5 10 Bit Line Current (mA) MR = (Rmax - Rmin)/Rmin Isolation Transistor June 12, 2002 Digit Line Current 0mA 0mA 4mA 4mA VLSI 2002 c12p4 4 Tunneling Magnetoresistance MTJ Material Structure Top electrode, Bit Line Storage layer State 0 Pinned AF pinning layer Base electrode E F1 Parallel Low Resistance State 1 Pinned Digit Line Isolation Transistor June 12, 2002 E F1 Antiparallel High Resistance VLSI 2002 c12p4 Barrier Barrier AlOx Fixed Ru Pinned V Barrier Barrier Free } Pinned layer Spin Dependent Tunneling Free E F2 Free V E F2 5 Tunneling Magnetoresistance Across wafer uniformity - 200 mm 11.7 10.3 10.1 10.3 11.3 10.3 9.54 9.68 9.80 9.45 10.2 11.0 9.74 10.9 10.4 10.9 10.1 9.52 11.2 10.5 9.88 10.6 10.8 10.5 10.4 9.43 10.2 10.5 10.9 12.3 9.65 9.80 10.2 10.3 9.74 10.8 10.7 9.85 10.8 10.5 9.86 10.6 9.87 9.62 9.56 9.59 10.2 10.4 11.0 11.5 10.5 10.7 10.2 10.9 44.4 44.1 44.5 44.5 44.2 43.9 45.0 45.4 46.1 45.8 45.3 44.1 RA=10.4 kΩ-µm2, σ=6% June 12, 2002 44.5 45.2 42.9 44.3 43.4 45.7 45.3 43.4 44.6 46.0 45.6 45.1 45.4 45.5 45.9 44.0 44.8 44.5 43.1 45.8 46.0 44.6 45.6 45.8 45.5 45.8 46.0 45.9 45.7 45.9 43.9 45.8 45.4 45.6 45.0 44.7 44.8 44.1 43.1 44.5 45.0 44.7 44.0 MR=45%, σ=2% VLSI 2002 c12p4 6 Process Flow 1st MRAM Module Flow 2nd MRAM Module Flow Digit Line Pattern inlaid copper program lines with permeable cladding. 3rd MRAM Module Flow Deposit ILD, form via connection to bottom electrode, deposit, and and pattern MTJ stack. 4th Bit Line Deposit ILD, pattern via for connection to top electrode June 12, 2002 Pattern inlaid copper program line with permeable cladding. VLSI 2002 c12p4 7 Field Enhancement from Magnetic Cladding •Magnetic film surrounding conductor doubles field H for a given current I. + Htot + + − + − M −− − I I I H unclad I I ≈ 2w June 12, 2002 Unclad Line H clad I ≈ w VLSI 2002 c12p4 Clad Line • Cladding concentrates field to top of digit line 8 Field enhancement from cladding cladding Calculated field vs. distance above above cladded and uncladded lines 50 30 With cladding H (Oe) 20 10 0 0 20 I bitline (mA) 40 Astroid curve from CMOS array Uncladded bit line Cladded bit line 15 10 5 Without cladding 0.1 0.2 0.3 0.4 Distance above line (µm) 0 0 2 4 6 8 I digit line (mA) •Factor of 2 field enhancement calculated and observed June 12, 2002 VLSI 2002 c12p4 9 1Mb MRAM Architecture Current/Source or Sink Sink 16 Current/Source or Sink Sink 16 Row PreDecode Current Switch BL 0-511 DL0 0 Current Sink DL1023 Digit Line Row Select t 1023 MRAM Array 512 columns 1024 Rows 16 Ref. Columns 1023 DL1023 Column Select June 12, 2002 } Current/Source or Sink Sink 16 Current Source A 16 Current/Source or Sink Sink 16 Read Circuit dq0 GL511 Column Select 16 32 Current Conveyors 16 Comparators 16 Regenerators Ground Switch MRAM Array 512 columns 1024 Rows 16 Ref. Columns GL0 DL0 0 Current Sink Ground Switch GL0 GL511 Current Switch BL 511-0 dq15 Read Circuit dq15 VLSI 2002 c12p4 dq0 10 Array Architecture Left Bank Right Bank 512K bits 512K bits Ref Ref Ref Ref Ref Ref Ref Ref 32k 32k 32k D0 D1 1 D2 32k 32k D3 3 D4 32k 32k D5 5 June 12, 2002 D6 32k 32k D7 7 D8 32k 32k D9 9 32k 32k 32k 32k 32k D10 D12 D14 D11 D13 D15 Ref Ref Ref Ref Ref Ref Ref Ref 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k D15 D13 D11 D9 D7 D5 D3 D1 D14 D12 D10 D8 D6 D4 D2 D0 0 VLSI 2002 c12p4 11 MRAM 32Kb Memory Segment with Reference Generator ½ Memory block - 1024X16 BL0 BL1 BL14 Reference Generator ½ Memory block - 1024X16 BL15 BL16 BL17 BL30 BL31 Current Conveyors and Differential Amp June 12, 2002 VLSI 2002 c12p4 12 MRAM 32Kb Memory Segment with Reference Generator ½ Memory block - 1024X16 BL0 BL1 BL14 Reference Generator ½ Memory block - 1024X16 BL15 BL16 BL17 BL30 BL31 Current Conveyors and Differential Amp June 12, 2002 VLSI 2002 c12p4 13 Reference Generator Bit Line Rmax Rmin Digit Line Word Line Common Source RRef = ½(Rmax+Rmin) Digit Line Rmax Rmin Reference cell-Series/Parallel combination of MTJ devices generating mid resistance between the two memory states June 12, 2002 VLSI 2002 c12p4 14 Reference Performance 1kb array 13 12 11 10 9 Rhigh 200 Mid Point 150 Rlow 8 7 6 -0.5 -0.4 -0.3 -0.2 -0.1 0 Operating Region Frequency Cell Resistance KΩ 14 0.1 0.2 0.3 0.4 0.5 Mid Point R high 100 50 0 Cell Bias Voltage V June 12, 2002 Rlow 16 18 20 22 24 26 Sense Current (µA) VLSI 2002 c12p4 15 Vref Current Conveyor + - Idata + - + - + - Vbias 1Mb MRAM Read Circuit VP VO Two Stage Comparator VM Regenerator r r June 12, 2002 Vref Current Conveyor Vbias Idataref q VOref Two Differential Current Conveyor VLSI 2002 c12p4 16 Differential Current Conveyor MPG MTJtarget XO XO Column n select select Vbias Vref A1 A1 + + - A2 + A2 + - Current Conveyor + Vbias Vref Current Conveyor Vout June 12, 2002 VLSI 2002 c12p4 17 1Mb Measured Access Time 1.00V/div Output Enable e Data Out 50ns 1 1 <15ns 0 0 20ns/div June 12, 2002 VLSI 2002 c12p4 18 Shmoo Plot of Valid Data out vs. Vdd <50ns @ 3V Valid Data Out X Vdd (3V +/-10%) June 12, 2002 VLSI 2002 c12p4 19 1Mb MRAM Clk Gen Prog. Sources Bitline Select DL Curr Prog. Sources Source Current Conveyor Comparator Ref. I/O Buffer Blk 512K Core Prog. Sources Bitline Select Prog. Sources Current Conveyor Comparator I/O Buffer Digit Line Row Select 20 VLSI 2002 c12p4 June 12, 2002 512K Core 1M MRAM Specification CMOS Technology Memory Organization Cell Size 1M Die Size Array Efficiency Supply Voltage Access Time Cycle Time June 12, 2002 0.6µm Five Metal Double Poly (used as linear resistor) 16K X 16 7.1 µm2 4.25mm X 5.89mm >60% 2.7V to 3.3V 50ns 50ns VLSI 2002 c12p4 21 Summary • Demonstrated 1Mb MRAM with 50ns read and program access time • Integrated MRAM with Cu metal interconnect • Cladding of metal layers reduced the power power for programming by factor of four • New reference generator was demonstrated demonstrated for robust operation • Demonstrated MRAM material uniformity on on 200mm substrate June 12, 2002 VLSI 2002 c12p4 22