Transcript
Applied Mechanics and Materials ISSN: 1662-7482, Vols. 284-287, pp 2423-2427 doi:10.4028/www.scientific.net/AMM.284-287.2423 © 2013 Trans Tech Publications, Switzerland
Online: 2013-01-25
A Low Power CMOS Bulk-controlled Sub-harmonic Mixer for LTE-advanced Applications Hung-Che Wei1,a, and Chih-Lung Hsiao2,b,* 1
Department of Electronic Communication Engineering, National Kaohsiung Marine University, Kaohsiung Taiwan, R.O.C. 81143
2
Department of Electrical Engineering, Lunghwa University of Science and Technology, Taoyuan, Taiwan, R.O.C. 33306 a
b
[email protected],
[email protected] *Corresponding author
Keywords: LTE; linearity; sub-harmonic; mixer
Abstract. In this paper, a 3.5 GHz CMOS sub-harmonic mixer for LTE-advanced applications is presented. The mixer with the bulk-controlled technique improves the linearity and mitigates the power of the local oscillator. The proposed mixer is implemented by tsmc 0.18 µm Mixed Signal RF CMOS 1P6M process and consumes 2.2 mA from a 1.2 V supply. The proposed mixer operates at 3.5GHz LTE-advanced bands and achieves maximum input third-order intercept point (IIP3) of 2.3dBm, power conversion gains of 1.3 dB. Introduction The demand for the mobile internet access Up to now, both of Long-Term-Evolution Advanced(LTE-advanced) and IEEE 802.16m Worldwide Interoperability for Microwave Access(WiMAX) are considered as the candidates of the 4G systems. The operating bands of LTE-advanced are from 698 MHz to 3600 MHz. WiMAX operates from 2305 MHz to 5850 MHz. The low power RF front-end of the proposed project is composed of a wideband low power low noise amplifier(LNA) and a wideband high linearity mixer and is suitable for LTE-advanced and WiMAX applications. In the system budget design of a RF receiver, the overall noise figure (NF) is demonstrated by the noise figure and gain of the LNA. The linearity and port-to-port isolation of the mixer demonstrate the overall linearity and stability of the receiver. In the modern radio frequency(RF) receiver design, there are many architectures such as super heterodyne, image rejection and direct-conversion receivers. The direct-conversion receiver is popular in the past decade due to less components, image elimination, high integration, and lower cost. However, the direct-conversion receiver still suffers from local oscillator(LO) leakage and DC offsets[1]. Fig.1 illustrates a direct-conversion receiver composed of a low noise amplifier(LNA), a down-conversion mixer, an LO, and a low pass filter(LPF). Owing to the finite port-to-port isolation of the mixer, the high power LO signal will leak to the RF port and the intermediate frequency (IF) port. The phenomenon is defined as “LO leakage”. The LO leakage will inject the RF input terminals of the LNA and the mixer. Thus the DC offsets will appear in the IF port and compensate the following circuits. In the mixer design, the sub-harmonic mixers are adopted to avoid the DC offsets of the direct-conversion receiver[2-4]. However, the sub-harmonic mixer suffers from poor linearity and large LO driven power. The linearity of the mixer will affect the overall linearity of the receiver and the large LO driven power will severe the voltage controlled oscillator design.
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Fig. 1 Direct-conversion receiver.
Fig. 2 Proposed bulk-controlled sub-harmonic mixer.
Circuit Topology and Design The proposed single-balanced sub-harmonic mixer is illustrated in Fig. 2. The mixer core consists of M1–M6, and R1–R2. M1–M2 are the LO stage provides small current signal of twice of LO frequency. The twice of LO frequency avoids the LO offsets in the direct-conversion receiver. The LO stage operate in the saturation region. The LO stage acts as ideal switches when the input LO power is large. The commutating stage acts as an amplifier while the LO power is small. The LO power can be determined based on the DC operation point and the aspect ratio of the LO stage. If the transistors of the LO stage are biased in the boundary between the triode region and the saturation region, the LO stage acts as ideal switches with lowest driven power. However, the linearity will be worth. The bulk-controlled technique is adopted to mitigate the requirement of large LO power of the sub-harmonic mixer. By adjusting VBLO, the threshold voltage of MOSFETs of the LO stage can be reduced. The threshold voltage can be calculated by[5] VTHLO = VTH 0 + γ 2Φ F − VBLO − 2Φ F (1)
(
)
Applied Mechanics and Materials Vols. 284-287
VTHRF = VTH 0 + γ
(
2Φ F − (VDS1, 2 − VBRF ) −
2Φ F
)
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(2)
where VBLO and VBRF denote the bulk voltage of the LO stage and the RF stage, respectively. γ represents the body effect coefficient. The transconductor stage consists of M3 and M4. The RF signal is converted from the small voltage signal to the small current signal by the transconductor stage. From equation (2), the overall supply voltage of the proposed mixer can be mitigated by VBRF. Due to the multiplied function caused by the LO stage and transconductor stage, the down-converted IF voltage signal is generated by the load stage consisted of M5, M6, R1 and R2. The voltage headroom is dominated by M5 and M6. R1 and R2 provide the output impedance. M7, M8, R3 and R4 are the output buffer stage. M7 and M8 are the source followers and provide 50Ω impedance matching. Owing to the linearity requirement of the receiver design, the proposed bulk-controlled sub-harmonic mixer can be optimized to achieve high linearity and low power consumption by choosing appropriate VBLO and VBRF.
Simulation Results The mixer presented in this paper is realized by tsmc 0.18 µm Mixed Signal RF CMOS 1P6M model. According to RF of 3.5GHz and IF of 10MHz, LO frequency of the proposed mixer is 1.745GHz. From a 1.2 V supply voltage, the power consumption of the mixer core and buffer consume 0.7 mW and 1.9 mW, respectively. The RF, LO and IF ports are matched to 50Ω for measurement requirement. The RF input return loss is illustrated in Fig. 3. The input return loss is less than –30 dB at 3.5 GHz. Fig. 4 shows the conversion gain versus LO power. When the LO power is –3 dBm, the mixer achieves the maximum conversion gain of 3.3 dB. The LO power of –7 dBm is to optimize the overall performance of the proposed mixer. Thus, the conversion gain of the proposed mixer is 1.3 dB.
Fig. 3 RF input return loss.
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Fig. 4 Conversion gain versus LO power. The two-tone testing method is adopted to evaluate the IIP3 of the mixer. The frequency spacing of the two input RF signals is 250 kHz which is the channel spacing of a LTE-advanced system. Fig. 5 illustrates the extrapolation plot of the IIP3 of the proposed mixer. The maximum IIP3 achieves 2.3 dBm. Table 1 summarizes the simulation results of the proposed mixer. Comparing with the revealed sub-harmonic mixers, the proposed mixer reveals high linearity and low power consumption.
Fig. 5 IIP3 characteristic.
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Table 1 Performance summary of mixers. Ref. Process [µm] Supply Voltage [V] fRF [GHz] fLO [GHz] Current Consumption [mA] LO Power [dBm] IIP3 [dBm] Conversion Gain [dB] DSB Noise Figure [dB]
[6] 0.18 1.8 2.4 1.2 2.4 0 2 -2.76 24.9
[7] 0.18 1.8 5.25 2.625 7.3 –3.6 –11.7 8.89 24
This work 0.18 1.2 3.5 1.745 2.2 –7 2.3 1.3 23.3
Conclusion A 1.2V CMOS high linearity sub-harmonic mixer for LTE-advanced applications is presented in this paper. The proposed mixer reveals high linearity and low power consumption by the bulk-controlled technique. The mixer operates at RF of 3.5 GHz and converts to the IF signal frequency of 10 MHz by mixing with the LO frequency of 1.745 GHz. The mixer achieves conversion gain of 1.3 dB, IIP3 of 2.3 dBm, noise figure of 23.3 dB. The total power consumption including the buffer circuitry is 2.64 mW. The proposed mixer is suitable for direct conversion receiver applications because of the relatively high linearity and sub-harmonic architecture. Acknowledgements The chip fabrication was supported by the National Chip Implementation Center of Taiwan, R.O.C.
References [1] B. Razavi: RF Microelectronics (Prentice-Hall, New Jersey 2011). [2] L. Sheng, J.C. Jensen and L.E. Larson: A wide-bandwidth Si/SiGe HBT direct conversion subharmonic mixer/downconverter. IEEE J. Solid-State Circuits. Vol. 35 No. 9 (2000), p. 1329-1337. [3] T. Yamaji, H. Tanimoto and H. Kokatsu: A I/Q active balanced harmonic mixer with IM2 cancellers and a 45± Phase shifter. IEEE J. Solid-State Circuits. Vol. 33 No. 12 (1998), p. 2240-2246. [4] M. Goldfarb, E. Balboni and J. Cavey: Even harmonic double-balanced active mixer for use in direct conversion receivers. IEEE J. Solid-State Circuits. Vol. 38 No. 10 (2003), p. 1762-1766. [5] B. Razavi: Design of Analog CMOS Integrated Circuits (Mc Graw Hill, New York 2001). [6] M. Gilasgar: A 2.4GHz 1.8-V CMOS Sub-harmonic Mixer with Inherent Harmonic-Rejection, Presented at Proc. Int. Conf. Intelligent Systems, Modelling and Simulation, Liverpool, United Kingdom, (2010). [7] M.F. Huang, S.Y. Lee and C.J. Kuo: A 5.25 GHz Even Harmonic Mixer for Low Voltage Direct Conversion Receivers, Presented at Proc. Asian Solid-State Circuits Conf., Hsinchu, Taiwan, (2005).
