A16 Test Set Motherboard A6 Signal Processing Adc Module (spam)

Transcript

E8356A/57A/58A Overall Block Diagram REAR PANEL INTERCONNECTS USB HUB RS-232 PORT INTERFACE DISPLAY PROCESSOR FLASH A6 SIGNAL PROCESSING ADC MODULE (SPAM) PROBE POWER INVERTER POWER A GPIB ROM +45° VIDEO PROCESSOR To A3 VIDEO RAM L R A4 POWER SUPPLY A30 FLOPPY DISK DRIVE 61 kHz 61 kHz W34 J6 W10 To Phase Lock R1 A OUT 0.3 MHz R I 41.667 kHz W15 I +45° L R L W12 R1 IN R W10 B1-6 W16 B2-6 LOCAL DIGITAL BUS L B0 A17 LO DISTRIBUTION IF Calibration Signal LO In OVLD I -45° ADC POWER BUS Overload Interrupt Output A19 RECEIVER R1 B 61 kHz A14 MOTHERBOARD A IN W33 J5 2nd LO a DSP RAM W11 R B1-6 R2 LINE IN A31 HARD DISK DRIVE I L 2nd LO b ADC VGA INTERFACE VGA 0.3 MHz 1.041667 MHz PCI BRIDGE 10/100 BASE-T ETHERNET LAN R ADC PCI BUS LO In B0 W32 J4 R1 SPEAKER FROM A15 RAM I L I 61 kHz A3 FRONT PANEL INTERFACE MAIN CPU GPIB PORT INTERFACE Overload Interrupt Output OVLD -45° 41.667 kHz ADC EEPROM PARALLEL PORT INTERFACE A A18 RECEIVER A W31 J3 RAM PARALLEL To Phase Lock 2nd LO a USB INTERFACE RS-232 A16 TEST SET MOTHERBOARD PROBE CONNECTORS USB A15 CPU USB A2 DISPLAY A1 KEYPAD R1 OUT 1.041667 MHz 2nd LO b W17 B1 W18 To A8, A11, A16 A10 FREQUENCY REFERENCE W19 2nd LO a W42 EXT REF IN 10 MHz 10 MHz POWER BUS 212 F 10 f 1.041667 MHz 96 SERIAL TEST BUS NODES 2nd LO x4 B1-6: 4 MHz 25 10 MHz HIGH STAB (OCXO) B2, 4 B2-6 2 R 0.3 MHz I +45° I L R J2 B1-6 J105 R L B0: 101.3667140.1667 MHz 213 B1 L R 2nd LO x4 B0:1.366740.1667 MHz 50 MHz 10 MHz REF W36 J7 I 2.4 GHz 2nd LO b 214 F 2 J10 L R 414 To Phase Lock 418 f 166.667 kHz 5 MHz R 218 6 J50 MUX F B0 J6 40 MHz A12 SOURCE W38 J5 1.042 MHz FM 30 kHz W44 F LOCAL DIGITAL BUS POWER BUS W45 Ramp Cal EXT AM J6 EXT DET J7 ALC Delay Comp 317 1V/GHz PRETUNE: 30 kHz SWEEP: 100 Hz Digital Pretune Ramp 10MHz Ref In I R1 +45° R2 I L R L W14 R B IN W10 B1-6 B OUT 1.041667 MHz B Analog Ramp W6 A22 SWITCH SPLITTER 11 GHz From A16 A25 STEP ATTEN 500 B0-3 2.5 GHz Offset EXT DET B0 W1 50 W2 500 314 f B4 5.25 GHz YTO TUNE 100 kHz AQUIRE: ON 0.3 MHz R W7 8.0 GHz B1-6 312 I From A16 B4-6 YTO 3-9 GHz 315 B0 +/- 0.5 - 6 MHz -45° 41.667 kHz A LO In OVLD L E8357A/58A Only 2.083 MHz f B1-6 A21 RECEIVER B Signal Separation Power and Control B6 B5 313 Overload Interrupt Output J5 W39 B0: + B1-6: - 2nd LO a 217 PHASE LOCK REF B0: 0.3-10 MHz B1-6: 1.041667 MHz 311 To Phase Lock To Phase Lock B 2nd LO b W41 A11 PHASE LOCK Counter To Phase Lock To Phase Lock 50 MHz 4 150 MHz 4 I 100.1667 MHz Level Adjust J102 B0 B1-6 L I To 2nd LO b x 4 B0 1.5 GHz R2 IN R2 OUT 1.041667 MHz B0: 0° B1-6: -90° B0: -90° B1-6: 0° ALC FRAC-N LOGIC W37 J6 B0 W20 J101 I W13 R W10 4 2250MHz 415 VCO 417 L B1-6 To 2nd LO a x 4 1.5 GHz 10 MHz EXT AM I B0 POWER BUS FRAC-N LOGIC LO In OVLD L J3 J3 5 MHz REF -45° 41.667 kHz J106 B0, 1 3 GHz W35 J4 5 MHz REF 10 MHz To A11 POWER BUS B0:OFF B1-6:ON 216 1.2 GHz 416 Bx = ACTIVE SOURCE BAND DAC W43 1.5 - 3.0GHz 413 VCO 412 LOCAL DIGITAL BUS LOCAL DIGITAL BUS ALC Overload Interrupt Output A20 RECEIVER R2 W21 B3, 5, 6 LOW DENSITY DATA BUS 100 MHz EXT REF OUT 10 MHz A8 FRACTIONAL-N SYNTHESIZER HIGH DENSITY DATA BUS 211 J2 215 To Phase Lock R2 W4 A23 TEST PORT COUPLER DC BIAS 1 3 dB PORT 1 0-70 dB 117 15 dB ALC W8 113 112 J4 From A16 111 Slope Compensation 114 W40 L I Power DAC A26 STEP ATTEN R 3 GHz 118 Temp Comp 115 DAC 116 From A16 PMYO 3.8 GHz SOURCE BANDS: B0 = 0.3 - 10MHz B1 = 10 - 748 B2 = 748 - 1500 B3 = 1500 - 3000 B4 = 3000 - 4500 B5 = 4500 - 6500 B6 = 6500 - 9000 500 50 500 W3 W5 A24 TEST PORT COUPLER DC BIAS 2 3 dB PORT 2 0-70 dB 15 dB W9 sc854a E8356A/57A/58A Block Diagram