Transcript
140 MHz to 1000 MHz Quadrature Modulator AD8345 140 MHz to 1000 MHz operating frequency +2.5 dBm P1dB @ 800 MHz −155 dBm/Hz noise floor 0.5 degree RMS phase error (IS95) 0.2 dB amplitude balance Single 2.7 V to 5.5 V supply Pin-compatible with AD8346 and AD8349 16-lead TSSOP_EP package
FUNCTIONAL BLOCK DIAGRAM IBBP 1 IBBN 2 COM3 3
LOIN 5 LOIP 6
16
QBBP
15
QBBN
14
COM3
13
COM3
12
VPS2
11
VOUT
10
COM2
9
COM3
+
COM1 4
APPLICATIONS Cellular communication systems W-CDMA/CDMA/GSM/PCS/ISM transceivers Fixed broadband access systems LMDS/MMDS Wireless LAN Wireless local loop Digital TV/CATV modulators Single sideband upconverter
AD8345
PHASE SPLITTER
VPS1 7 BIAS ENBL 8
00932-001
FEATURES
Figure 1.
PRODUCT DESCRIPTION
APPLICATIONS
The AD8345 is a silicon RFIC quadrature modulator, designed for use from 140 MHz to 1000 MHz. Its excellent phase accuracy and amplitude balance enable the high performance direct modulation of an IF carrier.
The AD8345 modulator can be used as the IF transmit modulator in digital communication systems such as GSM and PCS transceivers. It can also directly modulate an LO signal to produce QPSK and various QAM formats for 900 MHz communication systems as well as digital TV and CATV systems.
The AD8345 accurately splits the external LO signal into two quadrature components through the polyphase phase splitter network. The I and Q LO components are mixed with the baseband I and Q differential input signals. Finally, the outputs of the two mixers are combined in the output stage to provide a single-ended 50 Ω drive at VOUT.
Additionally, this quadrature modulator can be used with direct digital synthesizers in hybrid phase-locked loops to generate signals over a wide frequency range with millihertz resolution. The AD8345 modulator is supplied in a 16-lead TSSOP_EP package. Its performance is specified over a −40°C to +85°C temperature range. This device is fabricated on Analog Devices’ advanced silicon bipolar process.
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
AD8345 TABLE OF CONTENTS Features .............................................................................................. 1
Basic Connections .......................................................................... 12
Applications....................................................................................... 1
LO Drive ...................................................................................... 12
Functional Block Diagram .............................................................. 1
LO Frequency Range ................................................................. 12
Product Description......................................................................... 1
Baseband I and Q Channel Drive ............................................ 13
Applications....................................................................................... 1
Reduction of LO Leakage.......................................................... 13
Revision History ............................................................................... 2
Single-Ended I and Q Drive...................................................... 13
Specifications..................................................................................... 3
RF Output.................................................................................... 14
Absolute Maximum Ratings............................................................ 4
Application with TxDAC® ......................................................... 14
ESD Caution.................................................................................. 4
Soldering Information ............................................................... 15
Pin Configuration and Function Descriptions............................. 5
Evaluation Board ........................................................................ 15
Typical Performance Characteristics ............................................. 6
Characterization Setups................................................................. 17
Equivalent Circuits ......................................................................... 10
SSB Setup..................................................................................... 17
Circuit Description......................................................................... 11
Modulated Waveform Setup ..................................................... 18
Overview...................................................................................... 11
CDMA IS95................................................................................. 18
LO Interface................................................................................. 11
WCDMA 3GPP .......................................................................... 18
Differential Voltage-to-Current Converter............................. 11
GSM ............................................................................................. 18
Mixers .......................................................................................... 11
Outline Dimensions ....................................................................... 19
Differential-to-Single-Ended Converter ................................. 11
Ordering Guide .......................................................................... 19
Bias ............................................................................................... 11
REVISION HISTORY 12/05—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Ordering Guide .......................................................... 19 4/05—Rev. 0 to Rev. A Updated Format..................................................................Universal Change to Part Name .........................................................Universal Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 7/01—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD8345 SPECIFICATIONS VS = 5 V; LO = −2 dBm @ 800 MHz; 50 Ω source and load impedances; I and Q inputs 0.7 V ±0.3 V on each side for a 1.2 V p-p differential input, I and Q inputs driven in quadrature @ 1 MHz baseband frequency. TA = 25°C, unless otherwise noted. Table 1. Parameter RF OUTPUT Operating Frequency 1 Output Power
Min 140
−3 Output P1dB Noise Floor Quadrature Error I/Q Amplitude Balance LO Leakage
Sideband Rejection
Third Order Distortion Second Order Distortion Equivalent Output IP3 Equivalent Output IP2 Output Return Loss (S22) RESPONSE TO CDMA IS95 BASEBAND SIGNALS ACPR EVM Rho LO INPUT LO Drive level LOIP Input Return Loss (S11) 2
BASEBAND INPUTS Input Bias Current Input Capacitance DC Common Level Bandwidth (3 dB) ENABLE Turn-On Turn-Off ENBL High Threshold (Logic 1) ENBL Low Threshold (Logic 0) POWER SUPPLIES Voltage Current Active Current Standby 1 2
Typ
0.5 0.5 −1 2.5 −155 0.5 0.2 −41 −40 −42 −33 −48 −42 −52 −60 25 59 −20
Max
Unit
1000
MHz dBm dBm dBm dBm dBm/Hz Degree rms dB dBm dBm dBm dBc dBc dBc dBc dBc dBm dBm dB
+2
−33 −40 −34
Test Conditions/Comments
140 MHz 220 MHz 800 MHz 20 MHz offset from LO, all BB inputs at 0.7 V CDMA IS95 setup (see Figure 38) CDMA IS95 setup (see Figure 38) 140 MHz 220 MHz 800 MHz 140 MHz 220 MHz 800 MHz
See Figure 38 −72 1.3 0.9995 −10
0.6
−2
dBc %
0
−5 −9
dB dB
No termination on LOIP, LOIN at ac ground 50 Ω terminating resistor, differential drive via balun
10 2 0.7 80
μA pF V MHz
Full power (0.7 V ±0.3 V on each input, see Figure 4)
0.8
2.5 1.5 +VS/2 +VS/2 2.7 50
dBm
65 70
μs μs V V 5.5 78
V mA μA
For information on operation below 140 MHz, see Figure 29. See the LO Interface section for more details on input matching.
Rev. B | Page 3 of 20
Enable high to output within 0.5 dB of final value Enable low to supply current dropping below 2 mA
AD8345 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPS1, VPS2 Input Power LOIP, LOIN (re 50 Ω) IBBP, IBBN, QBBP, QBBN Internal Power Dissipation θJA (Exposed Paddle Soldered Down) θJA (Exposed Paddle not Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec)
Rating 5.5 V 10 dBm 0 V, 2.5 V 500 mW 30°C/W 95°C/W 150°C −40°C to +85°C −65°C to +150°C 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 4 of 20
AD8345 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IBBP
1
16 QBBP 15 QBBN
IBBN
2
COM3
3
COM1
4
LOIN
5
LOIP
6
11 VOUT
VPS1
7
10 COM2
ENBL
8
14 COM3
TOP VIEW (Not to Scale)
13 COM3 12 VPS2
9
COM3
00932-002
AD8345
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. 1, 2
Mnemonic IBBP, IBBN
3, 9, 13, 14 4 5, 6
COM3 COM1 LOIN, LOIP
7
VPS1
8 10 11 12
ENBL COM2 VOUT VPS2
15, 16
QBBN, QBBP
Description I Channel Baseband Differential Input Pins. These high impedance inputs should be dc-biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin (0.4 V to 1 V). This gives a differential drive of 1.2 V p-p. Inputs are not self-biasing, so external biasing circuitry must be used in ac-coupled applications. Ground Pin for Input V-to-I Converters and Mixer Core. Ground Pin for the LO Phase Splitter and LO Buffers. Differential LO Drive Pins. Internal dc bias (approximately 1.8 V @ VS = 5 V) is supplied. Pins must be ac-coupled. Single-ended or differential drive is permissible. Power Supply Pin for the Bias Cell and LO Buffers. This pin should be decoupled using local 1000 pF and 0.01 μF capacitors. Enable Pin. A high level enables the device; a low level puts the device in sleep mode. Ground Pin for the Output Stage of Output Amplifier. 50 Ω DC-Coupled RF Output. Pin should be ac-coupled. Power Supply Pin for Baseband Input Voltage to Current Converters and Mixer Core. This pin should be decoupled using local 1000 pF and 0.01 μF capacitors. Q Channel Baseband Differential Input Pins. Inputs should be dc-biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin (0.4 V to 1 V). This gives a differential drive level of 1.2 V p-p. Inputs are not self-biasing, so external biasing circuitry must be used in ac-coupled applications.
Rev. B | Page 5 of 20
Equivalent Circuit Circuit A
Circuit B
Circuit C Circuit D
Circuit A
AD8345 TYPICAL PERFORMANCE CHARACTERISTICS 0 –2
0 TA = –40°C
–2
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p SSB OUTPUT P1dB (dBm)
SSB POWER (dBm)
–4 –6 –8 –10 –12 –14 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–4 –6 TA = +25°C –8 –10 –12
TA = +85°C
00932-007
–16 –14
–20 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY (MHz)
–16 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY (MHz)
Figure 3. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (FLO) (I and Q Inputs Driven in Quadrature at Baseband Frequency (FBB) = 1 MHz; TA = 25°C)
Figure 6. SSB Output 1 dB Compression Point (OP1dB) vs. FLO (VS = 2.7 V, LO Level = −2 dBm, I and Q Inputs Driven in Quadrature, FBB = 1 MHz) 4.0
1.0 0.5
3.5
–1.0
VS = 2.7V, 5V DIFFERENTIAL INPUT = 200mV p-p
–1.5 –2.0
VS = 5V DIFFERENTIAL INPUT = 1.2V p-p
–2.5 –3.0 –3.5 –4.0 –4.5 –5.0 –5.5 0.1
2.5 2.0
TA = +25°C TA = –40°C
1.5 1.0 0.5 0.0
–0.5 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY (MHz)
100
1 10 BASEBAND FREQUENCY (MHz)
TA = +85°C
3.0
00932-011
–0.5
SSB OUTPUT P1dB (dBm)
0.0
00932-008
OUTPUT POWER VARIATION (dB)
00932-010
–18
Figure 7. SSB Output 1 dB Compression Point (OP1dB) vs. FLO (VS = 5 V, LO Level = −2 dBm, I and Q Inputs Driven in Quadrature, FBB = 1 MHz)
Figure 4. I and Q Input Bandwidth (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, I and Q Inputs Driven in Quadrature) 0
–40
–2 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–41
–8 –10 –12 –14 –16
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–18 –20 –22 00932-009
SSB POWER (dBm)
–6
–24 –26 –40
–20
0 40 20 TEMPERATURE (°C)
60
80
Figure 5. SSB POUT vs. Temperature (FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, I and Q Inputs Driven in Quadrature)
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p –42 –43 –44 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p –45 –46 –47 –48 00932-012
CARRIER FEEDTHROUGH (dBm)
–4
–49
–50 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY (MHz)
Figure 8. Carrier Feedthrough vs. FLO (LO Level = −2 dBm, TA = 25°C)
Rev. B | Page 6 of 20
–30
–26
–32
–28
–36 –38 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–40 –42 –44 –46
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–48 –20
0
20 40 TEMPERATURE (°C)
60
–32 –34 –36 –38 –40 –42
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p –44
80
0
Figure 9. Carrier Feedthrough vs. Temperature (FLO = 800 MHz, LO Level = −2 dBm)
T = +85
26
T = –40
45
50
–36 SIDEBAND SUPPRESSION (dBc)
22
PERCENTAGE
15 20 25 30 35 40 BASEBAND FREQUENCY (MHz)
–35
28 24 20 18 16 14 12 10 8 6
00932-014
4 2 –82
–78 –74 –70 –66 –62 –58 CARRIER FEEDTHROUGH (dBm)
–54
–37 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–38 –39 –40 –41 –42
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–43 –44 –45 –40
–50
Figure 10. Carrier Feedthrough Distribution at Temperature Extremes After Feedthrough Nulled to <−65 dBm at TA = 25°C (FLO = 800 MHz, LO Level = −2 dBm)
–32
–25 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–36 –38 –40 –42 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p –44 –46 –48
–50 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY (MHz)
Figure 11. Sideband Suppression vs. FLO (TA = 25°C, LO Level = −2 dBm, FBB = 1 MHz, I and Q Inputs Driven in Quadrature)
0
20 40 TEMPERATURE (°C)
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p –30 –35 –40 –45 –50
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–55 –60 –65 0
5
101
52 02 53 03 54 BASEBAND FREQUENCY (MHz)
04
Figure 14. Third Order Distortion vs. FBB (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, I and Q Inputs Driven in Quadrature)
Rev. B | Page 7 of 20
80
60
00932-018
THIRD ORDER DISTORTION (dBc)
–20
–34
–20
Figure 13. Sideband Suppression vs. Temperature (FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, I and Q Inputs Driven in Quadrature)
–30
00932-015
SIDEBAND SUPPRESSION (dBc)
10
Figure 12. Sideband Suppression vs. FBB (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, I and Q Inputs Driven in Quadrature)
30
0 –86
5
00932-017
–50 –40
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p –30
00932-016
SIDEBAND SUPPRESSION (dBc)
–34
00932-013
CARRIER FEEDTHROUGH (dBm)
AD8345
55
0
–45
80
–50
75
SUPPLY CURRENT (mA)
–55 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p –60
–65
–70
–80 –40
–20
0
20 40 TEMPERATURE (°C)
60
60 55 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
50
40 –40
80
–8
–30
–10
–35
–12 –14 –16 –18
–50 –55
–20
–60
–22
–65
–24
–70 0.0
0.5 1.0 1.5 2.0 2.5 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)
–26 3.0
WITH 50Ω
WITH 100Ω
–10
2
–15
0 –2
–20 –25
SSB POUT
–4
–30
–6
–35
–8
–40
–10
–45
–12 –14
–50 –55
THIRD ORDER DISTORTION
–16
–60
–18
–65
–20
–70 0.0
0.5 1.0 1.5 2.0 2.5 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)
–22 3.0
1GHz
LOIN NO BALUN OR TERMINATION
Figure 19. Smith Chart of LOIN Port S11 (LOIP Pin AC-Coupled to Ground); Curves with Balun and External Termination Resistors Also Shown (VS = 5 V, TA = 25°C) 0
SSB OUTPUT POWER (dBm)
4
00932-021
THIRD ORDER DISTORTION (dBc)
Figure 16. Third Order Distortion and SSB POUT vs. Baseband Differential Input Voltage (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, VS = 2.7 V) –5
250MHz
Figure 17. Third Order Distortion and SSB POUT vs. Baseband Differential Input Voltage (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, VS = 5 V)
Rev. B | Page 8 of 20
–5
–10
–15
–20 VS = 2.7V –25 00932-024
–6
RETURN LOSS (dB)
–4
–20
THIRD ORDER DISTORTION
80
SMITH CHART NORMALIZED TO 50Ω
SSB OUTPUT POWER (dBm)
–15
–45
60
00932-020
THIRD ORDER DISTORTION (dBc)
–2
–40
0 20 40 TEMPERATURE (°C)
1GHz
–10
SSB POUT
–20
Figure 18. Power Supply Current vs. Temperature
Figure 15. Third Order Distortion vs. Temperature (FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, I and Q Inputs Driven in Quadrature)
–25
00932-022
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p 65
45
00932-019
–75
70
00932-023
THIRD ORDER DISTORTION (dBc)
AD8345
VS = 5V –30 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 FREQUENCY (MHz)
Figure 20. Return Loss (S22) of VOUT Output (TA = 25°C)
AD8345 –150
–36
–151
NOISE FLOOR (dBm/Hz)
–153 –154
VS = 5V
–155 –156 –157
00932-025
–158 –159 –160 –10
–9
–8
–7
–6
–5 –4 –3 –2 LO LEVEL (dBm)
–1
0
1
2
Figure 21. Noise Floor vs. LO Input Power (TA = 25°C, FLO = 800 MHz, VS = 5 V, All I and Q Inputs Are DC-Biased to 0.7 V) Noise Measured at 20 MHz Offset from Carrier
Rev. B | Page 9 of 20
–40 –42
VS = 5.5V
–44 –46 –48 –50 –10
00932-026
CARRIER FEEDTHROUGH (dBm)
–38 –152
–9
–8
–7
–6
–5 –4 –3 –2 LO LEVEL (dBm)
–1
0
Figure 22. LO Feedthrough vs. LO Input Power (TA = 25°C, LO = 800 MHz, VS = 5.5 V)
1
2
AD8345 EQUIVALENT CIRCUITS VPS2
VPS2 BUFFER
TO MIXER CORE
100kΩ
100kΩ
ENBL INPUT
100kΩ
00932-005
00932-003
CURRENT MIRROR
TO BIAS FOR STARTUP/ SHUTDOWN
Figure 25. Circuit C
Figure 23. Circuit A
VPS2
VPS1
40Ω
LOIN
40Ω
Figure 24. Circuit B
Figure 26. Circuit D
Rev. B | Page 10 of 20
00932-006
VOUT
00932-004
LOIP
PHASE SPLITTER CONTINUES
AD8345 CIRCUIT DESCRIPTION OVERVIEW The AD8345 can be divided into the following sections: local oscillator (LO) interface, mixer, differential voltage-to-current (V-to-I) converter, differential-to-single-ended (D-to-S) converter, and bias. A block diagram of the part is shown in Figure 27. LOIP LOIN
PHASE SPLITTER
OUT 00932-027
Σ
In this circuit, each baseband input pin is connected to an op amp driving a transistor connected as an emitter follower. A resistor between the two emitters maintains a varying current proportional to the differential input voltage through the transistor. These currents are fed to the two mixers in differential form.
MIXERS
IBBP IBBN
QBBP QBBN
DIFFERENTIAL VOLTAGE-TO-CURRENT CONVERTER
Figure 27. AD8345 Block Diagram
The LO interface generates two LO signals at 90° of phase difference with each other, to drive two mixers in quadrature. Baseband signals are converted into current form in the differential V-to-I converters, feeding into the two mixers. The outputs of the mixers are combined to feed the differential-tosingle-ended converter, which provides a 50 Ω output interface. Bias currents to each section are controlled by the enable (ENBL) signal. A detailed description of each section follows.
There are two double-balanced mixers, one for the in-phase channel (I channel) and one for the quadrature channel (Q channel). Each mixer uses the Gilbert-cell design with four cross-connected transistors. The bases of the transistors are driven by the LO signal of the corresponding channel. The output currents from the two mixers are summed together in two load resistors. The signal developed across the load resistors is sent to the differential-to-single-ended converter.
DIFFERENTIAL-TO-SINGLE-ENDED CONVERTER The differential-to-single-ended converter consists of two emitter followers driving a totem-pole output stage whose output impedance is established by the emitter resistors in the output transistors. The output of this stage is connected to the output pin (VOUT).
LO INTERFACE
BIAS
The LO interface consists of interleaved stages of polyphase phase splitters and buffer amplifiers. The polyphase phase splitter contains resistors and capacitors connected in a circular manner to split the LO signal into I and Q paths in precise quadrature with each other. The signal on each path goes through a buffer amplifier to make up for the loss and high frequency roll-off. The two signals then go through another polyphase network to enhance the quadrature accuracy. The broad operating frequency range (140 MHz to 1000 MHz) is achieved by staggering the RC time constants of each stage of the phase splitters. The outputs of the second phase splitter are fed into the driver amplifiers for the mixers’ LO inputs.
A band gap reference circuit based on the Δ-VBE principle generates the proportional-to-absolute temperature (PTAT) as well as temperature-stable currents used by the different sections as references. When the band gap reference is disabled by pulling down the voltage at the ENBL pin, all other sections are shut off accordingly.
Rev. B | Page 11 of 20
AD8345 BASIC CONNECTIONS IP
AD8345
IN C6 1000pF 5
1
T1 ETC1-1-13
R1 50Ω 4
+VS
2
C7 1000pF
QBBP 16
2 IBBN
QBBN 15
3 COM3
COM3 14
4 COM1
COM3 13
5 LOIN
VPS2 12
6 LOIP
VOUT 11
7 VPS1
COM2 10
8 ENBL
COM3 9
QP
QN
C1 1000pF
+VS VOUT
3
C4 0.01μF
C2 0.01μF
C5 1000pF
C3 1000pF
00932-028
LO
1 IBBP
Figure 28. Basic Connections
In Figure 28, a 50 Ω resistor to ground combines with the device’s high input impedance to provide an overall input impedance of approximately 50 Ω (see Figure 19 for a plot of LO port input impedance). For maximum LO suppression at the output, a differential LO drive is recommended. In Figure 28, this is achieved using a balun (M/A-COM part number ETC1-1-13). The outputs of the balun are ac-coupled to the LO inputs, which have a bias level of approximately 1.8 V dc. An LO drive level of −2 dBm is recommended for lowest output noise. Higher levels degrade linearity while lower levels tend to increase the noise floor slightly. For example, reducing the LO power from −2 dBm to −10 dBm increases the noise floor by approximately 0.3 dB (see Figure 21).
The frequency range on the LO input is limited by the internal quadrature phase splitter. The phase splitter generates drive signals for the internal mixers which are 90° out of phase relative to one another. Outside of the specified LO frequency range of 140 MHz to 1 GHz, this quadrature accuracy degrades, resulting in decreased sideband suppression. See Figure 11 for a plot of sideband suppression vs. LO frequency from 250 MHz to 1 GHz. Figure 29 shows the sideband suppression of a typical device from 70 MHz to 300 MHz. 0 –5 VS = 5V, DIFFERENTIAL INPUT = 1.2V
–10 –15 –20 –25 –30 –35 –40
00932-029
LO DRIVE
LO FREQUENCY RANGE
SIDEBAND SUPPRESSION (dBc)
The basic connections for operating the AD8345 are shown in Figure 28. A single power supply of between 2.7 V and 5.5 V is applied to the VPS1 pin and the VPS2 pin. A pair of ESD protection diodes is connected internally between the VPS1 pin and the VPS2 pin so these must be tied to the same potential. Both pins should be individually decoupled using 1000 pF and 0.01 μF capacitors, located as close as possible to the device. For normal operation, the enable pin (ENBL) must be pulled high. The turn-on threshold for ENBL is VS/2. COM1 to COM3 should all be tied to the same low impedance ground plane.
–45 –50 40
60
80 100 120 140 160 180 200 220 240 260 280 300 LO FREQUENCY (MHz)
Figure 29. Typical Lower Frequency Sideband Suppression Performance
The LO input pins can be driven single-ended at the expense of slightly higher LO leakage. LOIN is ac-coupled to ground using a capacitor and LOIP is driven through a coupling capacitor from a (single-ended) 50 Ω source. (This scheme could also be reversed with the drive signal being applied to LOIN.)
Rev. B | Page 12 of 20
AD8345 BASEBAND I AND Q CHANNEL DRIVE The I channel and Q channel baseband inputs should be driven differentially. This is convenient as most modern high-speed DACs have differential outputs. For optimal performance at VS = 5 V, the drive signal should be a 1.2 V p-p differential signal with a bias level of 0.7 V; that is, each input should swing from 0.4 V to 1 V. If the AD8345 is being run on a lower supply voltage, then the peak-to-peak voltage on the I and Q channel inputs must be reduced to avoid input clipping. For example, at a supply voltage of 2.7 V, a 200 mV p-p differential drive is recommended. This results in a corresponding reduction in output power (see Figure 3). The I and Q inputs have a large input bandwidth of approximately 80 MHz. At lower baseband input levels, the input bandwidth increases (see Figure 4). If the baseband signal has a high peak-to-average ratio (such as CDMA or WCDMA), then the rms signal strength must be backed off from this peak level in order to prevent clipping of the signal peaks. Clipping of signal peaks tends to increase signal leakage into adjacent channels. Backing off the I and Q signal strength, in the manner recommended, reduces the output power by a corresponding amount. This also applies to multicarrier applications where the per-carrier output power is lower by 3 dB for each doubling of the number of output carriers. The I and Q inputs have high input impedances because they connect directly to the bases of PNP transistors. If a dc-coupled filter is being used between a DAC and the modulator inputs, then the filter must be terminated with the appropriate resistance. If the filter is differential, then the termination resistor should be connected across the I and Q differential inputs.
REDUCTION OF LO LEAKAGE Because the I and Q signals are being effectively multiplied with the LO, any internal offset voltages on these inputs result in leakage of the LO. The nominal LO leakage of −42 dBm, which results from these internal offset voltages, can be reduced further by applying offset compensation voltages on the I and Q inputs. (Note that LO feedthrough is reduced by varying the differential offset voltages on the I and Q inputs, not by varying the nominal bias level of 0.7 V.) The reduction is easily accomplished by programming (and then storing) the appropriate DAC offset code. This does, however, require dc coupling the path from the DAC to the I and Q inputs. (DC coupling is also advantageous from the perspective of I and Q input biasing if the DAC is capable of delivering a bias level of 0.7 V.)
The procedure for reducing the LO feedthrough is simple. In order to isolate the LO in the output spectrum, a single sideband configuration is recommended (set I and Q signals to sine and cosine waves at, for example, 100 kHz; set LO to FRF − 100 kHz). An offset voltage is applied from the I DAC until the LO leakage reaches a trough. With this offset level held, an offset voltage is applied to the Q DAC until a (lower) trough is reached. LO leakage compensation holds up well over temperature. Figure 10 shows the effect of temperature on LO leakage after compensation at ambient. Compensated LO leakage degrades somewhat as the frequency is moved away from the frequency at which the compensation was performed. This is due to the effects of LO to RF output leakage, which is not a result of offsets on the I and Q inputs.
SINGLE-ENDED I AND Q DRIVE Where only single-ended I and Q signals are available, a differential amplifier such as the AD8132 or AD8138 can be used to generate the required differential drive signal for the AD8345. Although most DACs have differential outputs, using a singleended, low-pass filter between the dual DAC and the I and Q inputs can be more desirable from the perspective of component count and cost. As a result, the output signal from the filter must be converted back to differential mode and possibly be rebiased to 0.7 V common mode. Figure 30 shows a circuit that converts a ground-referenced, single-ended signal to a differential signal and adds the required 0.7 V bias voltage. Two AD8132 differential op amps configured for unity gain are used. With a 50 Ω input impedance, this circuit is configured to accept a signal from a 50 Ω source (for example, a low-pass filter). The input impedance can be easily changed by replacing the 49.9 Ω shunt resistor (and the corresponding 24.9 Ω resistor on the inverting input) with the appropriate value. The required dc-bias level is conveniently added to the signal by applying 0.7 V to the VOCM pins of the differential amplifiers. Differential amplifiers, such as the AD8132 and AD8138, can also be used to implement active filters. For more information on this topic, refer to the data sheets of these devices.
Rev. B | Page 13 of 20
AD8345 +5V 10kΩ
+ 10μF
0.1μF 1.5kΩ
1000pF
1000pF
0.01μF
348Ω
348Ω
IIN
0.01μF
3
8
5
49.9Ω 2
0.1μF
VPS1 VPS2
AD8132
IBBP
4
348Ω 1
6
IBBN
24.9Ω
Σ
348Ω
0.1μF
–5V
VOUT
LOIP
10μF + QBBP
PHASE SPLITTER LOIN
+5V
0.1μF
+ 10μF
QBBN
348Ω
AD8345
COM1 COM2 COM3
348Ω QIN
3
8
5
49.9Ω 2
0.1μF
AD8132 4
348Ω 1
24.9Ω
+
348Ω
10μF
0.1μF
00932-030
6
–5V
Figure 30. Single-Ended 1Q Drive Circuit
Note that this circuit assumes that the single-ended I and Q signals are ground-referenced. Any differential dc-offsets result in increased LO leakage at the output of the AD8345. It is possible to drive the baseband inputs with a single-ended signal biased to 0.7 V, with the unused inputs being biased to a dc level of 0.7 V. However, this mode of operation is not recommended because any dc level difference between the bias level of the drive signal and the dc level on the unused input (including the effect of temperature drift) results in increased LO leakage. In addition, the maximum output power is reduced by 6 dB.
APPLICATION WITH TxDAC® Figure 31 shows the AD8345 driven by the AD9761 TxDAC. (Any of the devices in the Analog Devices’ TxDAC family can also be used in this application.) The I and Q DACs generate differential output currents of 0 mA to 10 mA and 10 mA to 0 mA, respectively. The combination of 140 Ω resistors shunted to ground off each DAC output, along with 210 Ω resistors shunted between each differential DAC pair, produces a baseband signal into the AD8345 I and Q inputs that has a differential peak-to-peak swing of 1.2 V with a dc common-mode bias of 700 mV.
RF OUTPUT The RF output is designed to drive a 50 Ω load but should be ac coupled as shown in Figure 28. If the I and Q inputs are driven in quadrature by 1.2 V p-p signals, then the resulting output power is approximately −1 dBm (see Figure 3). The RF output impedance is very close to 50 Ω. As a result, no additional matching circuitry is required if the output is driving a 50 Ω load.
Rev. B | Page 14 of 20
AD8345 DVDD
DCOM
AVDD VPS1
IOUTA LATCH "I"
"I" DAC
2⋅
210Ω IOUTB
DAC DATA INPUTS
140Ω
VOUT
AD9761 LOIP
LATCH "Q"
"Q" DAC
2⋅
QOUTB SLEEP
FS ADJ
PHASE SPLITTER LOIN
210Ω
MUX CONTROL
CLOCK
QBBP
140Ω
QBBN
140Ω
AD8345
REFIO
RSET 2kΩ
00932-031
WRITE
Σ
IBBN
140Ω
QOUTA
SELECT
VPS2
IBBP
0.1μF
Figure 31. AD8345/TxDAC Interface
SOLDERING INFORMATION
The board is powered by a single supply (VS) in the range 2.7 V to 5.5 V. The power supply is decoupled by 0.01 μF and 1000 pF capacitors. The circuit closely follows the basic connection schematic with SW1 in Position B. If SW1 is in Position A, the enable pin (ENBL) is pulled to ground by a 10 kΩ resistor, and the device is in its power-down mode.
The AD8345 is packaged in a 16-lead TSSOP_EP package. For optimum thermal conductivity, the exposed pad can be soldered to the exposed metal of a ground plane. This results in a junction-to-air thermal impedance (θJA) of 30°C/W. However, soldering is not necessary for safe operation. If the exposed pad is not soldered down, then the θJA is equal to 95°C/W.
All connectors are SMA-type. The I and Q inputs are dc-coupled to allow a direct connection to a dual DAC with differential outputs. Resistor pads are provided in case termination at the I and Q inputs is required. The local oscillator input (LO) is terminated to approximately 50 Ω with an external 50 Ω resistor to ground. A 1:1 wideband transformer (ETC1-1-13) provides a differential drive to the AD8345’s differential LO input.
EVALUATION BOARD Figure 32 shows the schematic of the AD8345 evaluation board. Note that uninstalled components are marked as open. This is a 4-layer board, with the two center layers used as ground plane, and top and bottom layers used as signal and power planes. R1 (OPEN) IP
IN
R9 (OPEN)
AD8345 1
IBBP
QBBP 16
2
IBBN
QBBN 15
R2 (OPEN)
QP
QN R10 (OPEN)
3
COM3
COM3 14
4
COM1
COM3 13
5
LOIN
VPS2
6
LOIP
VOUT 11
R11 0Ω
C1 1000pF 5
LO R6 50Ω
1
T1 ETC1-1-13 4
2
C2 1000pF
3
7
VPS1
COM2 10
8
ENBL
COM3 9
R14 (OPEN)
R15 (OPEN)
VOUT
C4 1000pF
R7 0Ω
A
ENBL R8 10kΩ
B
SW1
00932-032
C3 0.01μF
VPOS
R12 0Ω C7 1000pF
VPOS
C6 0.01μF
C5 1000pF
12
VPOS
Figure 32. Evaluation Board Schematic
Rev. B | Page 15 of 20
00932-033
AD8345
00932-034
Figure 33. Evaluation Board Silkscreen
00932-035
Figure 34. Layout of Evaluation Board, Top Layer
Figure 35. Layout of Evaluation Board, Bottom Layer
Rev. B | Page 16 of 20
AD8345 CHARACTERIZATION SETUPS SSB SETUP Essentially, two primary setups are used to characterize the AD8345. These setups are shown in Figure 37 and Figure 38. Figure 37 shows the setup used to evaluate the product as a single sideband modulator. The interface board converts the single-ended I and Q inputs from the arbitrary function generator to differential inputs with a dc bias of approximately 0.7 V. The interface board also provides connections for power supply routing. The HP34970A and its associated plug-in 34901 are used to monitor power supply currents and voltages being supplied to the AD8345 characterization board. Two HP34907 plug-ins are used to provide additional miscellaneous dc and control signals to the interface board. The LO inputs are driven directly by an RF signal generator, and the output is measured directly with a spectrum analyzer. With the I channel driven with a sine wave and the Q channel driven with a cosine wave, the lower sideband is the single sideband output. The typical SSB output spectrum is shown in Figure 36.
IEEE
AMPLITUDE (dBm)
–20
–60 –70
–90 –100 CENTER = 900MHz
HP34970A D3
34907
34907
D1
D2
D3
TEKAFG2020
VN
I_IN
OUTPUT_1
Q_IN
OUTPUT_2
IP
QP QN
QP
AD8345
QN
CHARACTERIZATION BOARD LO VOUT ENBL P1
HP8593E RF I/P
SWEEP OUT 28V
SPECTRUM ANALYZER IEEE
IEEE
ARB FUNCTION GEN IN
IP IN
SPAN = 1MHz
Figure 36. Typical SSB Output Spectrum
34901
GND VP P1
00932-037
–80
INTERFACE BOARD
HP3631
RFOUT
–50
VPS1
–25V MAX
IEEE
–40
D2
+25V MAX
HP8648C
–30
D1
COM IEEE
–10
PC CONTROLLER
Figure 37. Characterization Board SSB Test Setup
Rev. B | Page 17 of 20
IEEE
00932-036
+15V MAX
0
AD8345 MODULATED WAVEFORM SETUP
WCDMA 3GPP
To evaluate the AD8345 with modulated waveforms, the setup shown in Figure 38 is used. A Rohde & Schwarz AMIQ signal generator with differential outputs is used to generate the baseband signals. For all measurements, the input level on each baseband input pin is 0.7 V ±0.3 V peak. The output is measured with a Rohde & Schwarz FSIQ spectrum/vector analyzer.
To evaluate the AD8345 for WCDMA, the 3GPP standard is used with a chip rate of 3.84 MHz. The plot in Figure 40 is an ACPR plot of the AD8345 using Test Model 1 from the 3GPP specification with 64 channels active. –10 CH PWR = –10.95dBm ACP UP = –52.51dB ACP LOW = –52.41dB
–20 –30
AMPLITUDE (dBm)
PC CONTROL AMIQ IP
QP
QN
IEEE PC CONTROLLER IP
HP8648C
AD8345
IN
–60 –70 –80
QN
CHARACTERIZATION LO BOARD ENBL VOUT P1
RFOUT
IEEE
QP
–50
–90
FSIQ RF I/P
–100 IEEE
–110 CENTER = 380MHz
SPECTRUM ANALYZER
SPAN = 14.7MHz
Figure 40. Typical AD8345 WCDMA 3GPP Output Spectrum
+15V MAX COM IEEE
00932-040
IN
–40
GSM
+25V MAX 00932-038
–25V MAX
HP3631
Figure 38. Test Setup for Evaluating AD8345 with Modulated Waveforms
CDMA IS95 To measure ACPR, the I and Q input signals used are generated with Pilot channel (Walsh Code 00), Sync channel (WC 32), Paging channel (WC 01), and six Traffic (WC 08, 09, 10, 11, 12, 13) channels active. Figure 39 shows the typical output spectrum for this configuration.
To compare the AD8345 output to the GSM transmit mask, I and Q signals are generated using MSK modulation, GSM differential coding, a Gaussian filter, and a symbol rate of 270.833 kHz. The transmit mask is manually generated on the FSIQ using the GSM BTS specification for reference. The plot in Figure 41 shows that the AD8345 meets the GSM transmit mask requirements. 0 –10 –20
AMPLITUDE (dBm)
To perform EVM, Rho, phase, and amplitude balance measurements, the I and Q input signals used are generated with only the Pilot channel (Walsh Code 00) active. –10 CH PWR = –12.41dBm ACP UP = –72.9dB ACP LOW = –72.9dB
–20
–40 –50 –60 –70
–30
–80
–40
00932-041
AMPLITUDE (dBm)
–30
–90
–50
–100 –60
CENTER = 900MHz
SPAN = 1MHz
Figure 41. Typical AD8345 GSM Output Spectrum
–70 –80
00932-039
–90 –100 –110 CENTER = 880MHz
SPAN = 7.5MHz
Figure 39. Typical IS95 Output Spectrum
Rev. B | Page 18 of 20
AD8345 OUTLINE DIMENSIONS 5.10 5.00 4.90
16
BOTTOM VIEW 9
4.50 4.40 4.30
TOP VIEW 1
EXPOSED PAD (Pins Up)
6.40 BSC
3.00 SQ
8
1.05 1.00 0.80
1.20 MAX 0.15 0.00 SEATING 0.65 BSC PLANE
0.30 0.19
0.20 0.09
8° 0°
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-ABT
Figure 42. 16-Lead Thin Shrink Small Outline with Exposed Pad (TSSOP_EP) (RE-16-2) Dimensions shown in millimeters
ORDERING GUIDE Model AD8345ARE AD8345ARE-REEL7 AD8345AREZ 1 AD8345AREZ-RL71 AD8345-EVAL 1
Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C
Package Description 16-Lead TSSOP with Exposed Pad, Tube 16-Lead TSSOP with Exposed Pad, 7" Tape and Reel 16-Lead TSSOP with Exposed Pad, Tube 16-Lead TSSOP with Exposed Pad, 7" Tape and Reel Evaluation Board
Z = Pb-free part.
Rev. B | Page 19 of 20
Package Option RE-16-2 RE-16-2 RE-16-2 RE-16-2
AD8345 NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00932-0-12/05(B)
Rev. B | Page 20 of 20
