Transcript
400 MHz to 2700 MHz ¼ Watt RF Driver Amplifier
ADL5320
Data Sheet FEATURES
FUNCTIONAL BLOCK DIAGRAM
Operation: 400 MHz to 2700 MHz Gain of 16.9 dB at 880 MHz OIP3 of 45.0 dBm at 880 MHz P1dB of 25.4 dBm at 880 MHz Noise figure: 4.1 dB at 880 MHz Power supply voltage: 3.3 V to 5 V Power supply current: 44 mA to 104 mA Dynamically adjustable bias No bias resistor required Thermally efficient, MSL-1 rated SOT-89 package Operating temperature range: −40°C to +105°C ESD rating of ±4 kV (Class 3A)
GND (2)
ADL5320
2
3
RFIN
GND
RFOUT
05840-001
BIAS 1
Figure 1.
APPLICATIONS Wireless infrastructure Automated test equipment ISM/AMR applications
GENERAL DESCRIPTION
Rev. B
–20 –30 –40 SOURCE VCC = 5V VCC = 3.3V
–50 –60 –70 –80 –90 –20
–15
–10
–5
0 5 POUT (dBm)
10
15
20
05840-131
The ADL5320 is also rated to operate across the wide temperature range of −40°C to +105°C for reliable performance in designs that experience higher temperatures, such as power amplifiers. The 1∕4 watt driver amplifier also covers the 400 MHz to 2700 MHz wide frequency range and only requires a few external components to be tuned to a specific band within that wide range. This high performance, broadband RF driver amplifier is well suited for a variety of wired and wireless applications including cellular infrastructure, ISM band power amplifiers, defense equipment, and instrumentation equipment. A fully populated evaluation board is available.
The ADL5320 also delivers excellent adjacent channel power ratio (ACPR) vs. output power and bias voltage. The driver can deliver greater than 17 dBm of output power at 2140 MHz while achieving an ACPR of −55 dBc at 5 V. If the bias is reduced to 3.3 V, the −55 dBc ACPR output power reduces to 9 dBm. ACPR @ 5MHz CARRIER OFFSET (dBc)
The ADL5320 incorporates a dynamically adjustable biasing circuit that allows for the customization of OIP3 and P1dB performance from 3.3 V to 5 V without the need for an external bias resistor. This feature gives the designer the ability to tailor driver amplifier performance to the specific needs of the design. This feature also creates the opportunity for dynamic biasing of the driver amplifier, where a variable supply is used to allow for full 5 V biasing under large signal conditions and then can reduce the supply voltage when signal levels are smaller and lower power consumption is desirable. This scalability reduces the need to evaluate and inventory multiple driver amplifiers for different output power requirements from 22 dBm to 26 dBm output power levels.
Figure 2. ACPR vs. Output Power, Single Carrier W-CDMA TM1-64 at 2140 MHz
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ADL5320
Data Sheet
TABLE OF CONTENTS Features .............................................................................................. 1
High Temperature and 3.3 V Operation ................................. 11
Applications ....................................................................................... 1
Applications Information .............................................................. 12
Functional Block Diagram .............................................................. 1
Basic Layout Connections ......................................................... 12
General Description ......................................................................... 1 Revision History ............................................................................... 2
Soldering Information and Recommended PCB Land Pattern ................................................................................ 13
Specifications..................................................................................... 3
Matching Procedure ................................................................... 14
Typical Scattering Parameters..................................................... 4
Optimizing OP1dB .................................................................... 15
Absolute Maximum Ratings ............................................................ 5
W-CDMA ACPR Performance ................................................ 15
Thermal Resistance ...................................................................... 5
Evaluation Board ............................................................................ 16
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 18
Pin Configuration and Function Descriptions ............................. 6
Ordering Guide .......................................................................... 18
Typical Performance Characteristics ............................................. 7
REVISION HISTORY 10/13—Rev. A to Rev. B Changed 1805 MHz to 2110 MHz .............................. Throughout Changes to Figure 27 ...................................................................... 10 Changes to Figure 34 and Table 6 ................................................. 12 Changes to Figure 35 ...................................................................... 13 Changes to Matching Procedures Section ................................... 14 Added Optimizing OP1dB Section, Table 10, Table 11, Table 12, and Figure 39; Renumbered Sequentially ................... 15 Changes to Evaluation Board Section ............................................. 16 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 6/12—Rev. 0 to Rev. A Changes to Features Section and General Description Section........ 1 Added Application Section and Figure 2; Renumbered Sequentially ....................................................................................... 1 Changes to Specifications Section .................................................. 3 Deleted θJC (Junction to Paddle) Parameter, Table 3.................... 5
Changes to Operating Temperature Range Parameter, Table 3 .................................................................................................5 Added Thermal Resistance Section and Table 4; Renumbered Sequentially ........................................................................................5 Added EPAD Notation to Figure 3 .................................................6 Added Figure 27 ............................................................................. 10 Added High Temperature and 3.3 V Operation Section and Figure 28 to Figure 33 .................................................................... 11 Added Applications Information Section and Figure 35 .......... 12 Changes to Soldering Information and Recommended PCB Land Pattern .................................................................................... 12 Changed −82 dBc to −80 dBc in W-CDMA ACPR Performance Section .............................................................................................. 14 Added Figure 39 ............................................................................. 14 Updated Outline Dimensions ....................................................... 17 2/08—Revision 0: Initial Version
Rev. B | Page 2 of 20
Data Sheet
ADL5320
SPECIFICATIONS TA = 25°C, unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Frequency Range FREQUENCY = 880 MHz Gain 1 vs. Frequency vs. Temperature vs. Supply Output 1 dB Compression Point Output Third-Order Intercept Noise Figure FREQUENCY = 2140 MHz Gain1 vs. Frequency vs. Temperature vs. Supply Output 1 dB Compression Point Output Third-Order Intercept Noise Figure FREQUENCY = 2600 MHz Gain1 vs. Frequency vs. Temperature vs. Supply Output 1 dB Compression Point Output Third-Order Intercept Noise Figure POWER INTERFACE Supply Voltage Supply Current vs. Temperature Power Dissipation 1
Test Conditions/Comments
Min
3.3 V Typ
400
±50 MHz −40°C ≤ TA ≤ +85°C 3.2 V to 3.4 V, 4.75 V to 5.25 V Δf = 1 MHz, POUT = 10 dBm per tone
±50 MHz −40°C ≤ TA ≤ +85°C 3.2 V to 3.4 V, 4.75 V to 5.25 V Δf = 1 MHz, POUT = 10 dBm per tone
±100 MHz −40°C ≤ TA ≤ +85°C 3.2 V to 3.4 V, 4.75 V to 5.25 V Δf = 1 MHz, POUT = 10 dBm per tone
Max
Min
2700
400
5V Typ
Max
Unit
2700
MHz
15.6 ±0.2 ±0.6 ±0.2 21.5 34 3.2
16.3
16.9 ±0.3 ±0.6 ±0.1 25.4 45 4.1
17.5
dB dB dB dB dBm dBm dB
12.2 ±0.3 ±0.7 ±0.15 22.6 32 3.7
12.4
13.2 ±0.33 ±0.8 ±0.06 25.7 42 4.4
14.0
dB dB dB dB dBm dBm dB
10.7 ±0.2 ±0.6 ±0.2 25.7 29 4.1
11.5
12.5 ±0.6 ±1.1 ±0.1 27.4 37 5.1
13.4
dB dB dB dB dBm dBm dB
3.3 44 ±5.0 145
4.5
5 104 ±6.0 520
5.5 124
V mA mA mW
Pin RFOUT
−40°C ≤ TA ≤ +85°C VSUP = 3.3 V, VSUP = 5 V
Guaranteed maximum and minimum specified limits on this parameter are based on six sigma calculations.
Rev. B | Page 3 of 20
ADL5320
Data Sheet
TYPICAL SCATTERING PARAMETERS VSUP = 5 V and TA = 25°C; the effects of the test fixture have been de-embedded up to the pins of the device. Table 2. Freq (MHz) 400 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 2650 2700
S11 Magnitude (dB) −1.42 −1.38 −1.42 −1.48 −1.54 −1.62 −1.70 −1.80 −1.90 −2.01 −2.13 −2.27 −2.43 −2.63 −2.84 −3.09 −3.39 −3.73 −4.13 −4.59 −5.13 −5.76 −6.48 −7.36 −8.45 −9.74 −11.32 −13.34 −16.00 −19.89 −26.68 −33.34 −23.21 −18.39 −15.39 −13.26 −11.63 −10.31 −9.20 −8.23 −7.38 −6.61 −5.89 −5.23 −4.62 −4.05
Angle (°) −179.88 +175.04 +173.05 +171.25 +169.59 +168.11 +166.66 +165.36 +163.99 +162.65 +161.32 +159.98 +158.61 +157.11 +155.60 +153.91 +152.08 +150.14 +147.98 +145.57 +143.05 +140.31 +137.18 +133.46 +129.65 +125.36 +120.71 +115.47 +109.24 +100.84 +83.39 −26.40 −71.32 −83.50 −92.08 −100.04 −107.86 −115.84 −123.94 −132.24 −140.88 −149.66 −158.59 −167.51 −176.26 +175.18
S21 Magnitude (dB) +14.16 +13.97 +13.81 +13.66 +13.49 +13.32 +13.17 +13.05 +12.94 +12.84 +12.73 +12.65 +12.62 +12.59 +12.56 +12.55 +12.56 +12.57 +12.61 +12.66 +12.72 +12.79 +12.83 +12.89 +12.93 +12.98 +12.99 +12.99 +12.97 +12.93 +12.86 +12.76 +12.64 +12.49 +12.31 +12.11 +11.88 +11.62 +11.33 +11.01 +10.64 +10.24 +9.78 +9.27 +8.70 +8.07
Angle (°) +134.74 +126.21 +122.24 +118.41 +114.71 +111.12 +107.64 +104.27 +100.86 +97.48 +94.09 +90.72 +87.34 +83.90 +80.41 +76.75 +73.03 +69.24 +65.23 +61.05 +56.75 +52.20 +47.46 +42.49 +37.41 +32.12 +26.74 +21.16 +15.43 +9.57 +3.65 −2.46 −8.60 −14.83 −21.09 −27.46 −33.90 −40.49 −47.09 −53.81 −60.65 −67.57 −74.53 −81.60 −88.50 −95.43
Rev. B | Page 4 of 20
S12 Magnitude (dB) −32.56 −32.02 −31.84 −31.70 −31.56 −31.43 −31.29 −31.16 −31.01 −30.85 −30.69 −30.52 −30.32 −30.15 −29.95 −29.74 −29.54 −29.33 −29.12 −28.91 −28.69 −28.48 −28.28 −28.10 −27.95 −27.81 −27.70 −27.61 −27.56 −27.55 −27.58 −27.65 −27.75 −27.89 −28.07 −28.29 −28.54 −28.82 −29.15 −29.50 −29.89 −30.31 −30.76 −31.23 −31.73 −32.22
Angle (°) +13.47 +8.58 +6.81 +5.25 +3.85 +2.63 +1.35 +0.20 −0.95 −2.23 −3.43 −4.80 −6.24 −7.92 −9.61 −11.56 −13.63 −15.87 −18.39 −21.17 −24.17 −27.48 −31.05 −34.99 −39.05 -43.45 −48.12 −53.06 −58.23 −63.67 −69.38 −75.33 −81.44 −87.92 −94.55 −101.56 −108.80 −116.46 −124.41 −132.81 −141.70 −150.89 −160.57 −170.68 +178.90 +168.34
S22 Magnitude (dB) −3.42 −3.71 −3.84 −3.96 −4.08 −4.19 −4.30 −4.41 −4.52 −4.62 −4.71 −4.81 −4.89 −4.98 −5.06 −5.12 −5.18 −5.25 −5.28 −5.29 −5.27 −5.19 −5.12 −5.06 −4.94 −4.80 −4.65 −4.47 -4.30 −4.14 −3.99 −3.86 −3.74 −3.65 −3.58 −3.54 −3.50 −3.47 −3.44 −3.42 −3.40 −3.36 −3.31 −3.24 −3.17 −3.09
Angle (°) +176.22 +175.38 +175.10 +174.89 +174.74 +174.71 +174.74 +174.89 +175.10 +175.37 +175.78 +176.29 +176.85 +177.52 +178.29 +179.17 −179.85 −178.72 −177.52 −176.26 −174.93 −173.52 −172.60 −171.45 −170.38 −169.52 −168.95 −168.68 −168.76 −169.26 −170.11 −171.37 −172.97 −175.01 −177.37 +179.90 +176.83 +173.43 +169.75 +165.83 +161.63 +157.29 +152.82 +148.32 +143.81 +139.40
Data Sheet
ADL5320
ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE
Table 3. Parameter Supply Voltage, VSUP Input Power (50 Ω Impedance) Internal Power Dissipation (Paddle Soldered) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range
Rating 6.5 V 20 dBm 683 mW 150°C −40°C to +105°C −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 4 lists the junction-to-air thermal resistance (θJA) and the junction-to-paddle thermal resistance (θJC) for the ADL5320. Table 4. Thermal Resistance Package Type 3-Lead SOT-89
θJA1 35
θJC2 11
Unit °C/W
Measured on Analog Devices, Inc., evaluation board. For more information about board layout, see the Soldering Information and Recommended PCB Land Pattern section. 2 Based on simulation with JEDEC standard JESD51. 1
ESD CAUTION
Rev. B | Page 5 of 20
ADL5320
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFIN 1
ADL5320 GND 2
TOP VIEW (2) GND (Not to Scale)
NOTES 1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GND. SOLDER TO A LOW IMPEDANCE GROUND PLANE.
05840-002
RFOUT 3
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin No. 1 2 3
Mnemonic RFIN GND RFOUT Exposed Paddle
Description RF Input. Requires a dc blocking capacitor. Ground. Connect to a low impedance ground plane. RF Output and Supply Voltage. DC bias is provided to this pin through an inductor that is connected to the external power supply. RF path requires a dc blocking capacitor. Expose Paddle. Internally connected to GND. Solder to a low impedance ground plane.
Rev. B | Page 6 of 20
Data Sheet
ADL5320
TYPICAL PERFORMANCE CHARACTERISTICS 50
50
30
OIP3 (10dBm) OIP3 (–40°C)
35
OIP3 (+85°C)
OIP3 (dBm)
40
30
P1dB 25 20
28
35
27
30
15
26
GAIN
P1dB (–40°C)
10
P1dB (+85°C)
05840-003
25
NF
5 0 800
29
OIP3 (+25°C)
820
840
P1dB (dBm)
45
40
860 880 900 FREQUENCY (MHz)
920
940
25
P1dB (+25°C)
20 800
960
Figure 4. Gain, P1dB, OIP3, and Noise Figure vs. Frequency, 800 MHz to 960 MHz
820
840
860 880 900 FREQUENCY (MHz)
920
940
24 960
05840-006
GAIN, NF (dB); P1dB, OIP3 (dBm)
45
Figure 7. OIP3 and P1dB vs. Frequency and Temperature, 800 MHz to 960 MHz 50
19.0
930MHz
18.5
–40°C
17.5 +25°C
17.0
OIP3 (dBm)
GAIN (dB)
880MHz
46
18.0
+85°C
16.5 16.0
42 960MHz
850MHz
830MHz
38
15.5
05840-004
14.5 14.0 800
820
840
860 880 900 FREQUENCY (MHz)
920
940
30 –2
960
05870-007
34
15.0
0
2
4
6
8
10
12
14
16
18
20
22
POUT (dBm)
Figure 5. Gain vs. Frequency and Temperature, 800 MHz to 960 MHz
Figure 8. OIP3 vs. POUT and Frequency, 800 MHz to 960 MHz
–25.0
0
7.0
–5
6.5
–25.5
S22
–26.5
–15
–27.0
–20 S12
–27.5
–25 S11
–28.0
5.5 NF (dB)
–10
S11 (dB) AND S22 (dB)
S12 (dB)
6.0
–26.0
+85°C
5.0 4.5
+25°C
4.0 3.5
–40°C
–30
–29.0 700
750
800 850 900 FREQUENCY (MHz)
950
–40 1000
05840-005
–35
–28.5
Figure 6. Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, 800 MHz to 960 MHz
Rev. B | Page 7 of 20
2.5 2.0 700
750
800 850 900 FREQUENCY (MHz)
950
Figure 9. Noise Figure vs. Frequency and Temperature, 800 MHz to 960 MHz
1000
05840-008
3.0
ADL5320
Data Sheet 45 OIP3 (10dBm)
35
28.5
OIP3 (–40°C)
43
28.0
41
OIP3 (+85°C) OIP3 (+25°C)
30 OIP3 (dBM)
P1dB 25 20
27.5
39 27.0 37
P1dB (–40°C)
26.5
35 26.0
15 33
10
31
5 NF 0 2060
25.5 P1dB (+25°C)
2080
2100
2120 2140 2160 FREQUENCY (MHz)
2180
2200
2220
25.0 P1dB (+85°C)
29 2060
Figure 10. Gain, P1dB, OIP3, and Noise Figure vs. Frequency, 2060 MHz to 2200 MHz
2080
2100
2120 2140 2160 FREQUENCY (MHz)
2180
2200
24.5 2220
05840-012
GAIN
05840-009
GAIN, NF (dB); P1dB, OIP3 (dBm)
40
29.0
P1dB (dBm)
45
Figure 13. OIP3 and P1dB vs. Frequency and Temperature, 2060 MHz to 2200 MHz
16
43 2190MHz
41
15
2140MHz
2060MHz 2090MHz
–40°C
39
+25°C
13 +85°C
35
11
33
2080
2100
2120 2140 2160 FREQUENCY (MHz)
2180
2200
2220
05840-010
12
31 –2
2
4
6
8
10
12
14
16
18
20
22
POUT (dBm)
Figure 11. Gain vs. Frequency and Temperature, 2060 MHz to 2200 MHz
–23
Figure 14. OIP3 vs. POUT and Frequency, 2060 MHz to 2200 MHz
0
8.0 7.5
–5 –24
–15
S11 –26
–20 S12 –25
–27
6.5 6.0
NF (dB)
–25
S11 (dB) AND S22 (dB)
7.0 –10
S22
–30
2000
2050 2100 2150 FREQUENCY (MHz)
2200
2250
05840-011
1950
5.0 +25°C
4.5 4.0 –40°C
3.0
–35 –40 2300
+85°C
5.5
3.5
–28
–29 1900
0
Figure 12. Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, 2060 MHz to 2200 MHz
Rev. B | Page 8 of 20
2.5 2.0 1900
1950
2000
2050 2100 2150 FREQUENCY (MHz)
2200
2250
Figure 15. Noise Figure vs. Frequency and Temperature, 2060 MHz to 2200 MHz
2300
05840-014
10 2060
S12 (dB)
2220MHz
37
05840-013
OIP3 (dBm)
GAIN (dB)
14
Data Sheet
ADL5320 39 OIP3 (–40°C)
31
37
OIP3 (+25°C)
30
OIP3 (dBm)
20 15
35 P1dB (–40°C)
28
33
P1dB (+25°C)
32
GAIN
10
29
34
27
31
5
NF
0 2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700
P1dB (+85°C)
26
30 29 2500
2550
2600 FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. Gain, P1dB, OIP3, and Noise Figure vs. Frequency, 2500 MHz to 2700 MHz
05840-018
25
30
OIP3 (+85°C)
36
P1dB
05840-015
GAIN, NF (dB); P1dB, OIP3 (dBm)
38
OIP3 (10dBm)
35
32
P1dB (dBm)
40
25 2700
2650
Figure 19. OIP3 and P1dB vs. Frequency and Temperature, 2500 MHz to 2700 MHz
15
46 44
14 –40°C
42
+25°C
40
OIP3 (dBm)
GAIN (dB)
13
12 +85°C
2600MHz
2700MHz
38 36
11
2500MHz
34
10
2550
2600 FREQUENCY (MHz)
2650
2700
30 –3
Figure 17. Gain vs. Frequency and Temperature, 2500 MHz to 2700 MHz –25.0
3
5
7
9 11 13 POUT (dBm)
15
17
19
21
23
8.0 7.5
–5 7.0
S22
–26.5
–15
–27.0 S11
–27.5
–20
S12
–28.0
–25
–28.5
6.5 +85°C
6.0
NF (dB)
–10
S11 (dB) AND S22 (dB)
–26.0
5.5 +25°C
5.0 4.5
–40°C
4.0 3.5
–30 –29.0
3.0
2450
2500
2550 2600 2650 FREQUENCY (MHz)
2700
2750
–40 2800
05840-017
–35
–29.5
Figure 18. Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, 2500 MHz to 2700 MHz
Rev. B | Page 9 of 20
2.5 2.0 2400
2450
2500
2550 2600 2650 FREQUENCY (MHz)
2700
2750
2800
Figure 21. Noise Figure vs. Frequency and Temperature, 2500 MHz to 2700 MHz
05840-020
S12 (dB)
1
Figure 20. OIP3 vs. POUT and Frequency, 2500 MHz to 2700 MHz
0
–25.5
–30.0 2400
–1
05840-019
9 2500
05840-016
32
ADL5320
Data Sheet
18
50
16 40
12
PERCENTAGE (%)
10 8 6 4
30
20
10 05840-021
2 0 42.0
42.8
43.6
44.4
45.2
46.0
46.8
0
47.6
05840-024
PERCENTAGE (%)
14
3.80
3.88
3.96
4.04
4.12
4.20
4.28
NF (dB)
OIP3 (dBm)
Figure 22. OIP3 Distribution at 880 MHz
Figure 25. Noise Figure Distribution at 880 MHz
60
120 115 5.25V
SUPPLY CURRENT (mA)
PERCENTAGE (%)
50
40
30
20
110 5.0V
105 100 95
4.75V 90
10
24.4
24.8
25.2
25.6
26.0
26.4
80 –40 –30 –20 –10
26.8
P1dB (dBm)
Figure 23. P1dB Distribution at 880 MHz
0 10 20 30 40 TEMPERATURE (°C)
50
60
70
80
05840-025
05840-022
0
85
Figure 26. Supply Current vs. Supply Voltage and Temperature (Using 880 MHz Matching Components) 240
30
5V, +25°C
220 200 SUPPLY CURRENT (mA)
20
15
10
180
3.3V, –40°C
5V, +85°C
3.3V, +85°C
5V, +105°C
3.3V, +105°C
160 140 120 100 80
0
05840-040
60 5
40 05840-023
PERCENTAGE (%)
25
3.3V, +25°C
5V, –40°C
16.65
16.75
16.85
16.95
17.05
17.15
20 –6 –4 –2 0
17.25
2
4
6
8 10 12 14 16 18 20 22 24 26 28
POUT PER TONE (dBm)
GAIN (dB)
Figure 27. Supply Current vs. POUT and Temperature (2140 MHz Matching Components)
Figure 24. Gain Distribution at 880 MHz
Rev. B | Page 10 of 20
Data Sheet
ADL5320
HIGH TEMPERATURE AND 3.3 V OPERATION The ADL5320 has excellent performance at temperatures higher than 85°C. At 105°C, the gain and P1dB decrease by 0.2 dB, the OIP3 decreases by 0.4 dB, and the noise figure increases by 0.2 dB, compared with the data at 85°C. Figure 28, Figure 29, and Figure 30 show the performance at 105°C. 16
15.0 14.5
15
14.0 GAIN (dB)
14
13.5
13
GAIN (dB)
25°C 85°C 105°C 12
–40°C
13.0 12.5
+25°C 12.0 11.5
11
+85°C
11.0
+105°C 2120
2140
2160
2180
2200
2220
FREQUENCY (MHz)
10.0 2060
2080
2100
2120
2140
2160
2180
2200
2220
FREQUENCY (MHz)
Figure 28. Gain vs. Frequency and Temperature, 5 V Supply, 2060 MHz to 2200 MHz 45
29.0 28.5
27
26
37
27.0
35
26.5
P1dB (dBm)
39
105°C
25
31
24
30 –40°C
23
25°C
26.0
33
85°C
28
22
31
+85°C
2080
2100
2120
2140
2160
2180
2200
29 2220
05840-134
FREQUENCY (MHz)
21 2060
6.5
6.0
6.0 NOISE FIGURE (dB)
6.5
105°C 85°C 25°C
4.0 3.5
2160
2180
2200
27 2220
+105°C
5.0
+85°C
4.5 4.0
+25°C
3.5
–40°C 3.0
2.5
2.5
2.0 1900
2140
5.5
3.0
1950
2000
2050
2100
2150
2200
2250
05840-135
NOISE FIGURE (dB)
7.0
4.5
2120
Figure 32. OIP3 and P1dB vs. Frequency and Temperature, 3.3 V Supply, 2060 MHz to 2200 MHz
7.0
5.0
2100
FREQUENCY (MHz)
Figure 29. OIP3 and P1dB vs. Frequency and Temperature, 5 V Supply, 2060 MHz to 2200 MHz
5.5
2080
+105°C
2300
FREQUENCY (MHz)
Figure 30. Noise Figure vs. Frequency and Temperature, 5 V Supply, 2060 MHz to 2200 MHz Rev. B | Page 11 of 20
2.0 1900
1950
2000
2050
2100
2150
2200
2250
2300
FREQUENCY (MHz)
Figure 33. Noise Figure vs. Frequency and Temperature, 3.3 V Supply, 2060 MHz to 2200 MHz
05840-138
25.0 2060
29
+25°C
105°C
25.5
32
–40°C
OIP3 (dBm)
85°C
+105°C
+25°C
41
27.5
33
+85°C
43
25°C
28.0 P1dB (dBm)
Figure 31. Gain vs. Frequency and Temperature, 3.3 V Supply, 2060 MHz to 2200 MHz
OIP3 (dBm)
2100
05840-137
2080
05840-136
10.5 05840-133
10 2060
ADL5320
Data Sheet
APPLICATIONS INFORMATION BASIC LAYOUT CONNECTIONS
GND
The basic connections for operating the ADL5320 are shown in Figure 34. Table 6 lists the required matching components. Capacitors C1, C2, C3, C4, and C7 are Murata GRM155 series (0402 size) and Inductor L1 is a Coilcraft 0603CS series (0603 size). For all frequency bands, the placement of C3 and C7 are critical. From 2300 MHz to 2700 MHz, the placement of C2 is also important. Table 7 lists the recommended component placement for various frequencies.
VSUP
(2)
GND
C6 10µF C5 10nF C41
ADL5320 2
RFOUT
3
λ22
1 λ42 C2
λ32
C31
A 5 V dc bias is supplied through L1 which is connected to RFOUT (Pin 3). In addition to C4, 10 nF and 10 µF power supply decoupling capacitors are also required. The typical current consumption for the ADL5320 is 110 mA.
1SEE 2SEE
C71
TABLE 6 FOR FREQUENCY SPECIFIC COMPONENTS. TABLE 7 FOR RECOMMENDED COMPONENT SPACING.
Figure 34. Basic Connections
Table 6. Recommended Components for Basic Connections Frequency (MHz) 450 to 500 800 to 960 2110 to 2170 2300 to 2400 2500 to 2700
C1 (pF) 100 47 22 12 12
C2 (pF) 100 47 22 2.2 1.0
C3 (pF) 18 6.8 0.5 1.2 1.8
C4 (pF) 100 100 22 12 12
C5 (nF) 10 10 10 10 10
C6 (μF) 10 10 10 10 10
C7 (pF) 6.8 2.2 1.5 1.0 0.5
L1 (nH) 47 47 15 15 15
Table 7. Matching Component Spacing Frequency (MHz) 450 to 500 800 to 960 2110 to 2170 2300 to 2400 2500 to 2700
λ1 (mils) 391 200 300 225 142
λ2 (mils) 75 75 75 75 75
Rev. B | Page 12 of 20
RFOUT
λ3 (mils) 364 100 175 125 89
λ4 (mils) 50 350 275 125 75
05840-026
λ12
1
GND
RFIN
RFIN
L11 C11
Data Sheet
ADL5320
SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN
1.80mm
Figure 35 shows the recommended land pattern for the ADL5320. To minimize thermal impedance, the exposed paddle on the SOT-89 package underside is soldered down to a ground plane along with Pin 2. If multiple ground layers exist, stitch them together using vias. For more information on land pattern design and layout, refer to the Application Note AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
3.48mm
0.635mm 5.37mm
0.20mm
0.62mm
0.86mm
1.27mm
The land pattern on the ADL5320 evaluation board provides a measured thermal resistance (θJA) of 35°C/W. To measure θJA, the temperature at the top of the SOT-89 package is found with an IR temperature gun. Thermal simulation suggests a junction temperature 10°C higher than the top of the package temperature. With additional ambient temperature and input/output power measurements, θJA can be determined.
0.762mm
0.86mm
3.00mm
Figure 35. Recommended Land Pattern
Rev. B | Page 13 of 20
05840-041
1.50mm
ADL5320
Data Sheet
MATCHING PROCEDURE
05840-028
The ADL5320 is designed to achieve excellent gain and IP3 performance. To achieve this, both input and output matching networks must present specific impedance to the device. The matching components listed in Table 7 were chosen to provide −10 dB input return loss while maximizing OIP3. The load-pull plots (Figure 36, Figure 37, and Figure 38) show the load impedance points on the Smith chart where optimum OIP3, gain, and output power can be achieved. These load impedance values (that is, the impedance that the device sees when looking into the output matching network) are listed in Table 8 and Table 9 for maximum gain and maximum OIP3, respectively. The contours show how each parameter degrades as it is moved away from the optimum point.
Figure 36. Load-Pull Contours, 880 MHz
05840-029
From the data shown in Table 8 and Table 9, it becomes clear that maximum gain and maximum OIP3 do not occur at the same impedance. This can also be seen on the load-pull contours in Figure 36, Figure 37, and Figure 38. Thus, output matching generally involves compromising between gain and OIP3. In addition, the load-pull plots demonstrate that the quality of the output impedance match must be compromised to optimize gain and/or OIP3. In most applications, where line lengths are short and where the next device in the signal chain presents a low input return loss, compromising on the output match is acceptable. To adjust the output match for operation at a different frequency or if a different trade-off between OIP3, gain, and output impedance is desired, the following procedure is recommended.
Figure 37. Load-Pull Contours, 2140 MHz
1. 2.
3.
4.
Install the recommended tuning components for a 800 MHz to 960 MHz tuning band, but do not install C3 and C7. Connect the evaluation board to a vector network analyzer so that input and output return loss can be viewed simultaneously. Starting with the recommended values and positions for C3 and C7, adjust the positions of these capacitors along the transmission line until the return loss and gain are acceptable. Push-down capacitors that are mounted on small sticks can be used in this case as an alternative to soldering. If moving the component positions does not yield satisfactory results, then the values of C3 and C7 should be increased or decreased (most likely increased in this case as the user is tuning for a lower frequency). Repeat this process until the desired gain and return loss are achieved. Once the desired gain and return loss are realized, OIP3 should be measured. Most likely, it will be necessary to go back and forth between return loss/gain and OIP3 measurements (probably compromising most on output return loss) until an acceptable compromise is achieved.
05840-030
For example, to optimize the ADL5320 for optimum OIP3 and gain at 700 MHz, take the following steps:
Figure 38. Load-Pull Contours, 2600 MHz
Table 8. Load Conditions for Gain MAX Frequency (MHz) 880 2140 2600
ΓLoad (Magnitude) 0.5147 0.6611 0.5835
ΓLoad (°) 159.88 134.40 133.80
Gain MAX (dB) 17.76 13.78 12.36
Table 9. Load Conditions for IP3 MAX Frequency (MHz) 880 2140 2600
Rev. B | Page 14 of 20
ΓLoad (Magnitude) 0.4156 0.5035 0.4595
ΓLoad (°) −138.22 +110.27 +102.48
IP3 MAX (dBm) 46.29 42.72 43.01
Data Sheet
ADL5320
OPTIMIZING OP1dB
W-CDMA ACPR PERFORMANCE
In some applications, power handling (P1dB) is a more important parameter than IP3. In such cases, it is possible to retune the output load to increase the compression point of the ADL5320. Table 10 shows the performance of the ADL5320 after tuning the output load for higher OP1dB. Table 11 lists the component spacing, and Table 12 lists the component values.
Figure 40 shows a plot of adjacent channel power ratio (ACPR) vs. POUT for the ADL5320. The signal type being used is a single W-CDMA carrier (Test Model 1−64) at 2140 MHz. This signal is generated by a very low ACPR source. ACPR is measured at the output by a high dynamic range spectrum analyzer, which incorporates an instrument noise correction function.
Table 10. OP1dB, Gain, and IP3 Results with Optimized OP1dB
The ADL5320 achieves an ACPR of −80 dBc at 0 dBm output, at which point device noise and not distortion is beginning to dominate the power in the adjacent channels. At an output power of 10 dBm, ACPR is still very low at −70 dBc, making the device particularly suitable for PA driver applications.
Frequency (MHz) 880 2140 2600
Gain (dB) 17.9 13.5 12.4
OIP3 (dBm) 36 40 35
OP1dB (dBm) 28.5 28 28.2
λ1 (mils) 200 300 142
λ2 (mils) 75 75 75
GND
λ3 (mils) 339 89 89
λ4 (mils) 100 275 75
VSUP
(2)
GND
C6 10µF C5 10nF C41
3
λ22
C31
1SEE 2SEE
λ32
1 λ42 C2
SOURCE VCC = 5V VCC = 3.3V
–50 –60 –70 –80
–15
–10
–5
0 5 POUT (dBm)
10
15
20
Figure 40. ACPR vs. POUT, Single Carrier W-CDMA (Test Model 1−64) at 2140 MHz Evaluation Board
RFOUT
C71
05840-039
2
RFOUT
1
GND
λ12
RFIN
L11 C11
–40
–90 –20
ADL5320 RFIN
–30
TABLE 12 FOR FREQUENCY SPECIFIC COMPONENTS. TABLE 11 FOR RECOMMENDED COMPONENT SPACING.
Figure 39. Component Values and Spacing for Increased OP1dB
Table 12. Matching Component Values for Optimized OP1dB Frequency (MHz) 800 to 960 2110 to 2170 2500 to 2700
C1 (pF) 47 22 12
C2 (pF) 47 22 1.0
C3 (pF) 6.8 0.5 1.8
05840-031
Frequency (MHz) 800 to 960 2110 to 2170 2500 to 2700
ACPR @ 5MHz CARRIER OFFSET (dBc)
–20
Table 11. Matching Component Spacing for Optimized OP1dB
C4 (pF) 100 22 12
Rev. B | Page 15 of 20
C5 (nF) 10 10 10
C6 (μF) 10 10 10
C7 (pF) 5.6 1.8 1.0
L1 (nH) 47 15 15
ADL5320
Data Sheet
EVALUATION BOARD The schematic of the ADL5320 evaluation board is shown in Figure 41. This evaluation board uses 25 mil wide traces and is made from FR4 material. The evaluation board comes tuned for operation in the 2110 MHz to 2170 MHz tuning band. Tuning options for other frequency bands are also provided in Table 13. The recommended placement for these components is provided in Table 14. The inputs and outputs should be ac-coupled with appropriately sized capacitors. DC bias is provided to the amplifier via an inductor connected to the RFOUT pin. A bias voltage of 5 V is recommended. GND
10uF 10nF 22pF
C1 22pF
15nH C3 0.5pF
C2 22pF
C7 1.5pF
VSUP
C5 10nF 05840-033
(2)
GND
C6 10µF
C4 22pF
2
C3 0.5pF
L1 15nH 3
λ2
λ3
λ4
C2 22pF
RFOUT
Figure 42. Evaluation Board Layout and Default Component Placement for Operation from 2110 MHz to 2170 MHz
05840-032
1
RFOUT
λ1
GND
RFIN
C1 22pF
RFIN
ADL5320
C7 1.5pF
Figure 41. Evaluation Board, 2110 MHz to 2170 MHz
Table 13. Evaluation Board Configuration Options Component C1, C2 C4, C5, C6
L1 C3, C7 R1 VSUP, GND
Function AC coupling capacitors Power supply bypassing capacitors DC bias inductor Tuning capacitors
450 MHz to 500 MHz 0402, 100 pF
800 MHz to 960 MHz 0402, 47 pF
2110 MHz to 2170 MHz (Default Configuration) 0402, 22pF
C4 = 0603 100 pF, C5 = 0603 10 nF, C6 = 1206 10 µF 0603, 47 nH C3 = 0402 18 pF, C7 = 0402 6.8 pF
C4 = 0603 100 pF, C5 = 0603 10 nF, C6 = 1206 10 µF 0603, 47 nH C3 = 0402 6.8 pF, C7 = 0402 2.2 pF
C4 = 0402 22pF, C5 = 0603 10 nF, C6 = 1206 10 µF 0603, 15 nH C3 = 0402 0.5 pF, C7 = 0402 1.5 pF
Power supply connections
VSUP red test loop, GND black test loop
VSUP red test loop, GND black test loop
VSUP red test loop, GND black test loop
2300 MHz to 2400 MHz C1= 0402 12 pF, C2 = 0402 2.2 pF C4 = 0603 12 pF, C5 = 0603 10 nF, C6 = 1206 10 µF 0603, 15 nH C3 = 0402 1.2 pF, C7 = 0402 1.0 pF R1 = 0402 0 Ω VSUP red test loop, GND black test loop
2500 MHz to 2700 MHz C1 = 0402 12 pF, C2 = 0402 1.0 pF C4 = 0603 12 pF, C5 = 0603 10 nF, C6 = 1206 10 µF 0603, 15 nH C3 = 0402 1.8 pF, C7 = 0402 0.5 pF R1 = 0402 0 Ω VSUP red test loop, GND black test loop
Table 14. Recommended Component Spacing on Evaluation Board Frequency (MHz) 450 to 500 800 to 960 2110 to 2170 2300 to 2400 2500 to 2700
λ1 (mils) 391 200 300 225 142
λ2 (mils) 75 75 75 75 75
Rev. B | Page 16 of 20
λ3 (mils) 364 100 175 125 89
λ4 (mils) 50 350 275 125 75
Data Sheet
ADL5320
10uF
10uF
10nF
10nF
100pF
C1 100pF
15nH C3 1.2pF
C7 1pF
C2 2.2pF
R1 0Ω
05840-037
05840-035
C7 6.8pF
C3 18pF
12pF
C1 12pF
C2 100pF
47nH
Figure 43. Evaluation Board Layout and Component Placement 450 MHz to 500 MHz Operation
10uF
10uF
10nF
10nF
100pF
C1 47pF
47nH
C2 47pF
12pF
C1 12pF
C7 2.2pF
15nH
C3 1.8pF
C7 0.5pF
C2 1.0pF
R1 0Ω
05840-036
05840-034
C3 6.8pF
Figure 45. Evaluation Board Layout and Component Placement 2300 MHz to 2400 MHz Operation
Figure 44. Evaluation Board Layout and Component Placement 800 MHz to 960 MHz Operation
Figure 46. Evaluation Board Layout and Component Placement 2500 MHz to 2700 MHz Operation
Rev. B | Page 17 of 20
ADL5320
Data Sheet
OUTLINE DIMENSIONS 1.75 1.55
(2)
4.25 3.94
1
2
2.413 2.380 2.337
2.60 2.30 3
1.20 0.75
1.50 TYP
1.270 1.252 1.219 BOTTOM VIEW
0.635 0.569 0.508
3.00 TYP TOP VIEW
2.29 2.14
4.60 4.40
1.60 1.40
0.44 0.35
PKG-003480
0.52 0.32
COMPLIANT TO JEDEC STANDARDS TO-243
09-12-2013-C
END VIEW
0.56 0.36
Figure 47. 3−Lead Small Outline Transistor Package [SOT-89] (RK-3) Dimensions shown in millimeters
ORDERING GUIDE Model 1 ADL5320ARKZ-R7 ADL5320-EVALZ 1
Temperature Range −40°C to +105°C
Package Description 3-Lead SOT-89, 7“ Tape and Reel Evaluation Board
Z = RoHS Compliant Part.
Rev. B | Page 18 of 20
Package Option RK-3
Data Sheet
ADL5320
NOTES
Rev. B | Page 19 of 20
ADL5320
Data Sheet
NOTES
©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05840-0-10/13(B)
Rev. B | Page 20 of 20
