Transcript
ADS2009 High Frequency and High Speed Co-Design Platform
Chip Package Board
Agilent Confidential 1
Agenda 1. Co-Design, What is it? – Case Study: RFIC differential power amplifier 2. Complete Co-Design for 4G LTE application – – – –
Ptolemy system level co-design X-Parameters Integrated 3DEM ADS/EMPro Co-Design for Improving Handset Performance
3. Summary
Agilent Confidential 2
Co-Design, Why is it? - The Trends in High Frequency and High Speed Electronic Designs Market pressures in consumer wireless electronics are driving exponential growth in functionalities that must be integrated into the same sized and same priced packages. •
Much closer proximity, embedded passives – increased parasitics, couplings
•
Multichip modules, and stacked die become more common - forcing IC, package, and board designers to work together more closely
•
Multiple available technologies are integrated onto the PCB as shown instead of designing all onto an IC
Chip/package/module/board co-design from the beginning of design process is inevitable! Chips
RF SiP
SiP
Packages
SMD PoP
Board
Agilent Confidential 3
Motivation for Co-Design: Reducing risk of designing in isolation IC Design
90% success
Module Design
90% success
Board Design
90% success
90% x 90% x 90% = 73% chance of integration success Risk increases when more components are integrated 4
Another View of Co-Design Sequential Design Process
DR2
DR1 DR1
DR3
DR2
DR4 DR3
DR3
DR4
N Y OK?
Done
Project Start
DR2
Integration
DR1
Con-current Co-Design Process
Project Start
DR1
DR1
DR2
DR3
DR3
DR2
DR2
DR4
DR3
Done
DR1
DR4 Ex: EEsof Build Process Agilent Confidential
5
Chip/Pkg/Module/Board Co-Design Case Study RFIC Differential Power Amplifier Test Board Bondwires
Single Ended PA Output
PCB
LTCC Balun
Single Ended PA Input
6
Si PA
LTCC Balun
Package Agilent Confidential Developed Feb 2009
Let’s Prove Whether The Integration Works RFIC PA + Balun RFIC PA, integrated with Ideal and LTCC Balun, meets the performance goals Blue: Ideal Balun Red: LTCC Balun
Ideal to LTCC Balun Spectre Netlist
Spectre Compatibility Agilent Confidential 7
Let’s Prove Whether The Integration Works Final Integration of Balun + RFIC PA + Package
Agilent Confidential 8
Unexpected or Unpredicted Parasitic Resonance Caught in Last Minute Final Integration Test! Unexpected parasitic resonance around 1.7GHz How will this unexpected or unpredicted behavior impact on the development schedule?
S21
S12
S21
S12 S11
S22
Agilent Confidential 9
Last Minute Design Failure Could Impact Greatly on Design Wins and Time to Market What if, this is a design failure to meet the spec?
Ground Through W/B
So, will you re-spin the chip? $$$ & TTM Or re-spin the package? $$$ & TTM Or bandage the design or just blame others? Typical grounding problem with RFIC
Agilent Confidential 10
Agenda 1. Co-Design, What is it? – Case Study: RFIC differential power amplifier 2. Complete Co-Design for 4G LTE application – – – –
Ptolemy system level co-design X-Parameters Integrated 3DEM ADS/EMPro Co-Design for Improving Handset Performance
3. Summary
Agilent Confidential 11
Designing for The Single Goal, LTE Ant Design
MIMO Ant
IC Design
PDF
Board Design
RFIC Duplexer MMIC
S1
S1
X2
X2
S1
LTE
S1
Pkg Design
RF LNA
Package
LTCC Balun
Module Design
LTCC LPF
RF Power Amp
Agilent Confidential 12
Why Not Verify and Test The Designs Against The Targeted System, LTE As realistic as possible! As harsh as possible! We want every circuit, component, even for sub-system designer to use ADS Ptolemy to verify and test their designs under a true co-design environment So don’t over or under-design circuits, components, or even sub-systems
Agilent Confidential 13
System
System Design – LTE Front-End Co-Design Ptolemy system level co-design allows designers to • Find problems that will degrade the system’s performance • Reduce risks inherent in making RF hardware work within a PHY – Optimize RF HW to work well with PHY baseband algorithms and HW
Why choose LTE? Why does LTE need Co-Design? • 3.9G on to 4G standard in same small form-factor to co-exist with existing 2G-3G HW – multiplies the risk • Challenging RF HW design due to modulation, multiple bands, MIMO, power
ADS2009 has LTE library that is fully framed and coded, supports TDD mode, same algorithms as instruments with full MIMO Tx/Rx and can demodulate faded MIMO channel
Agilent Confidential 14
ADS 2009 front-end Co-Design infrastructure 1.
Simulation platform for multi-technology – Faster, higher capacity multi-threaded simulators
IC Desig n
– Acceleration with graphics processors – Parallel simulation on compute clusters – Intelligent algorithms for increased capacity and accuracy 2.
Package/Module Design
Model support for multi-technology – X-parameters non-linear models from measurement – 3D electromagnetic components for package, antennas, shields
Board Integration & Design
– Behavioral & transistor level models – Netlist compatibility with HSPICE and Spectre – Signal stimulus data to and from instruments 3.
15
Interoperability with back-end co-design platforms from Cadence and Mentor
System
LTE Front-End Co-Design Flow and Enabling Technologies • Integrated 3D EM • 3D Components • Antenna Modeling
Spectrasys, WhatIF
Create candidate Analyze for noise, architecture spurs, leakage
Validate frequency plan
Replace behavioral models with component designs
Re-validate each Validate Tx, Rx w/behavioral models, change w/LTE test benches generate component specs
= Lockout 16 16
•X-Parameters •Connected Solutions
Trade-off and optimize components, add packages, modularize
Re-validate w/LTE test benches
Perform validation of final design; substitute measured components as they become available
• Ptolemy •LTE Wireless Library •Circuit Envelope CoSimulation • Simulation consistent with Agilent VSA/Instruments
Agilent Confidential
System
LTE Architectural Design – SpectraSys and WhatIF
Spectrasys root-cause analysis capability accounts for all frequencies at all nodes as well as all mismatches and all possible signal or leakage paths across any arbitrary WhatIF for frequency planning • Finds Tx, Rx or Tx/Rx spur-free zones, spurs near desired IF or RF
Agilent Confidential 17 17
System
Spreadsheets Enough? – Toxic Approximation Create candidate architecture
Spreadsheet NodeNames
Parts ( )
CF (MHz)
CP (dBm)
GAIN (dB)
CGAIN (dB)
COMP (dB)
CNP (dBm)
CNF (dB)
CNDR (dB)
SDR (dB)
ECGAIN (dB)
ECNF (dB)
1
TxSource
220
-0.366
0
0
0
-101.151
0
100.785
100.366
0
0
9
TxIFBPF
220
-8.421
-8.054
-8.054
0
-101.151
8.054
92.73
108.421
-8
8
15
TxIFAmp
220
-2.427
5.993
-2.061
3.407e-3
-91.55
11.662
61.329
20.278
-2
11
14
TxMixer
1880
-10.535
-8.109
-10.17
0
-96.033
15.288
27.991
110.531
-2
11
12
TxBPF1
1880
-12.542
-2.007
-12.176
0
-97.274
16.053
28.003
112.542
-4
11.309
6
TX_Driver
1880
3.939
16.481
4.305
9.343e-3
-79.136
17.71
27.988
16.041
12.5
12.046
11
Tx_PA
1880
23.472
19.519
23.824
0.241
-59.588
17.74
23.144
1.908
32.5
12.061
16
TxCoupler
1880
23.072
-0.4
23.424
0
-59.988
17.74
23.144
76.285
32.1
12.061
Target Pout
• Avoid unnecessary over-specification causing design delays and increased component costs
Correct Gain from Spectrasys Simulator
• “Traditional Spreadsheet” Gain is 9 dB too high – will cause missspecification and force a re-spin Agilent Confidential
18 18
Circuit/System/EM Co-Simulation Co-Validates Candidate System to LTE Specs Fully framed and coded, bit accurate LTE UL source; set frequency and power
Validate Tx, Rx w/behavioral models, generate component specs
6 1
3
2
5
2 4
Circuit-Level Components in Uplink:
19
1.
Gilbert Cell Mixer
2.
PC Board Amps
3.
LTCC Low-Pass Filter
4.
X-Parameter Driver Amp
5.
Packaged MMIC PA
6.
Tunable antenna match
Replace behavioral models with component designs
LTE measurements use same algorithms as Vector Signal Analyzer / Instruments
Breath and Depth of ADS Co-Design LTE Transmitter Sub-System Test Bench Board AMP
LTE CoDesign
Antenna
RFIC LTCC LPF
MMIC
Agilent Confidential 20
Real Time Ptolemy Co-simulation with VSA for TX
LTE CoDesign
Agilent Confidential 21
MMIC
Chip/Package Co-Design in MMIC PA X-Parameters Driver Amp
MMIC DFN Package
MMIC PA Amp
S11 < -15 dB S22 < -15 dB Gain > 20 dB LTE SPECS Transmitter Pout = 23 +/- 2 dBm PA Pout = 24.5 +/- 2 dBm Duplexer + Coupler loss 1.5 dB
Agilent Confidential 22
MMIC
Completed MMIC PA with DFN Package + Bondwire
True MMIC Design Verification prior to Manufacturing is done by Co-simulating the MMIC inside the package and with bond wires using 3D EM simulation in ADS
Agilent Confidential 23
MMIC
MMIC PA Verification With/Without Package+Bondwires
S21 Spec > 20 dB
S21 Spec > 20 dB
A slight drop in gain (.12 dB) is due to the bond wire and Package effects.
Agilent Confidential 24 24
LTE Wireless library Verification in ADS ADS •True Circuit Level Co-Simulation with Fast Verification modeling (AVM) •CE ties the circuit with Ptolemy •Able to optimize for ACPR, EVM… •Accounts for the Frame structure •Identical to the real Wireless signal •True and Accurate verification
25
LTE Wireless library Verification in ADS ADS Gating “ON” on a typical wireless signal; “Measures on the burst” Fully compliant with wireless stds
Gating ON
Gating OFF
Gating OFF Gating ON
Other EDA Tools
Gating ON
Gating ON
Gating OFF Gating OFF
26
Gating is “OFF” Not accurate & not compliant with wireless standards
X-Para
Simple Simulation Based X-Parameter Extraction in ADS 2009 X Parameters in ADS
X-Parameters XP_Bias XPTerm3 Num=3
XP_Source XPTerm1
Amp Amp1
1.
Insert X Parameter template which is already setup for the extraction.
X_Param XP1
2.
Connect your DUT.
Freq[1]=1 GHz Z0=50 Ohm
3.
Modify Power levels and frequencies as needed.
4.
Simulate.
XP_Load XPTerm2 Num=2
Num=1
In ADS 2009, you will be able to create simulation based X Parameters for your circuits. You can then use these X parameters in X-Parameter model to do higher level simulations to understand more about your design.
Agilent Confidential 27
X-Para
What are X-Parameters? Parameters that capture non-linearties of amplitude and phase at specified harmonics Extracted either from measurement or simulation • Easy extraction of parameters based on automated NVNA • New devices, for example GaN, with inaccurate models can be easily characterized
ADS
• Drag and Drop-in ADS X-Parameter models PHD model generation for ADS
Cable / connectors
Source Pull Tuner
NVNA
Measures X-Parameters
MDIF File
Load Pull Tuner Tuners that covers all regions on the Smith Chart (all Impedances)
28
LSOP In Our Example 20
dB(v3_T) dB(v3_S) dB(V3)
15
Voltage @ DC-bias port
10 5 0 -5
6.0E9
5.5E9
5.0E9
4.5E9
4.0E9
3.5E9
3.0E9
2.5E9
2.0E9
1.5E9
1.0E9
5.0E8
0.0
indep(dB(V3)) indep(dB(v3_S)) indep(dB(v3_T )) 20 0
dB(i3_T) dB(i3_S) dB(I3)
-20
Current @ DC-bias port
-40 -60 -80 -100 -120
Output incident 0
-50
dB(a2) dB(A2)
dB(a1) dB(A1)
6.0E9
5.5E9
5.0E9
4.5E9
4.0E9
3.5E9
3.0E9
2.5E9
2.0E9
1.5E9
1.0E9
5.0E8
0.0
Input incident
0 -50
indep(dB(I3)) indep(dB(i3_S)) indep(dB(i3_T))
-100 -150
-100 -150 -200
-200
VCC -250
-250
-300 4.0E9
4.5E9
5.0E9
5.5E9
6.0E9
4.0E9
4.5E9
5.0E9
5.5E9
6.0E9
3.5E9
3.0E9
2.5E9
2.0E9
1.5E9
1.0E9
RF in
5.0E8
6.0E9
5.5E9
5.0E9
4.5E9
4.0E9
3.5E9
3.0E9
2.5E9
2.0E9
1.5E9
1.0E9
5.0E8
0.0
0.0
-300
indep(dB(A2)) indep(dB(a2))
RF out
indep(dB(A1)) indep(dB(a1))
0
0 -50
x_1_AmpDUT Amp1
-100 -150 -200
dB(b2_T) dB(b2_S) dB(B2)
dB(b1_T) dB(b1_S) dB(B1)
-50 -100 -150 -200 -250
-250 -300 3.5E9
3.0E9
2.5E9
2.0E9
1.5E9
1.0E9
5.0E8
6.0E9
5.5E9
5.0E9
29
4.5E9
4.0E9
3.5E9
3.0E9
2.5E9
2.0E9
1.5E9
1.0E9
5.0E8
0.0
Input reflected
indep(dB(B1)) indep(dB(b1_S)) indep(dB(b1_T))
0.0
-300
Output reflected indep(dB(B2)) indep(dB(b2_S)) indep(dB(b2_T ))
X-Para
Breakthrough Non-Linear X-Parameters Value for Co-Design: • PA vendors can offer X-parameters to the system integrators such as mobile phone manufacturing companies for an evaluation from the early stage of design process • PA vendors can protect the design IP (Intellectual Property)
System Integrators
New Designs
Existing parts
IC Design Houses
30
System
Validate Candidate Rx in MIMO Configuration Dual handset antennas with correlation, from EMPro FDTD
Perform validation of final design; substitute measured components as they become available
Only ADS can test this 2X2 MIMO configuration for the one performance spec that really matters: BER/PER with channel fading Agilent Confidential 31
Breath and Depth of ADS Co-Design Receiver Sub-System Test Bench
LTE CoDesign
Board LNA LTCC Balun RFIC
Agilent Confidential 32
Real Time Ptolemy Co-simulation with VSA for RX
LTE CoDesign
Agilent Confidential 33
Breath and Depth of ADS Co-Design LTE Top Level System Test Bench
LTE CoDesign
Entire system simulation that includes Tx, Channel, and Rx Fully framed and coded, bit accurate LTE UL source; set frequency and power
LTE measurements use same algorithms as Vector Signal Analyzer / Instruments
Agilent Confidential 34
Real Time Ptolemy Co-simulation with VSA for Whole System
LTE CoDesign
Agilent Confidential 35
3DEM
Integrated 3D EM is the Key to Co-Design Integrated 3D EM is essential technology to Co-Design as demonstrated Integrated 3D EM also saves cycle time on the EM front-end process Reducing “EM front-end process”, the process from entering the design geometry to being ready for the simulation, could save hours of simulation setup time (1hr +) and also on CAD resources
Non-Integrated EM Flow
Integrated EM Flow Agilent Confidential
36
3DEM
3DEM Co-Design With FlipChip IC Packaging Our value: Greatly reduce the risk that comes with the final integration by co-designing the circuit, package, and board interface together. Create 3D components, like solder bumps (with EMPro UI) and use them in ADS to get the most accurate prediction of the overall behavior. Multiple E field plot
3D Component Generated with EMPro 2008
E-field plot
Application Area: Package/Board interface with Solder Bumps Agilent Confidential 37
3DEM
3DEM Co-Design With RF/MMIC QFN Packaging Improved Package Transition
Microstrip Line on ThinFilm Substrate Chip Top View
Board Microstrip Feed Board dB(S11)
dB(S21)
Double Bonding Wires
Cyan & Dark Green: Original Design Agilent Confidential 38
3DEM
3DEM Co-Design With Mechanical Shield Our value: RF Designers can create EM shielding in minutes – No need to waste time redraw difficult 2-D layout, set up layers, material parameters, ports, boundary conditions, etc. in standalone 3DEM tools just to see what happens when you place a shield on top.
Shield ADS 3D component
Frequency Response Shift
Parasitic Resonance due to bad grounding
No more approximation! What you see is what you get (WYSIWYG) Agilent Confidential 39
Antenna
ADS/EMPro Co-Design for Improving Handset Performance Adaptive Antenna Matching Co- Design using EMPro – ADS
Co-Design and Optimization of Switched WLAN antenna using EMDS G2, Momentum G2 & Circuit Simulation
Calculate Antenna Diversity for Use in LTE MIMO Channel Simulation Using EMPro & Ptolemy
Agilent Confidential 40
Co-Design with Adaptive Antenna Matching 16
Tuning Time Const
14
GSM_antenna Signal dB(fs(Vbw_coupler[1],,,,,"Kaiser")) dB(fs(Vfw_coupler[1],,,,,"Kaiser"))
12 Vdc _ Tune (V)
Antenna
10 8 6 4
-260 -280 -300 -320 -340 -360 -380 -800
-600
-400
-200
0
200
400
600
800
freq, KHz
Time Switch Between 2 Antenna Configurations
2 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 time, usec
VSWR
Tuning Network
VSWR block
1.9E9
1.8E9
1.7E9
1.6E9
1.5E9
1.4E9
1.3E9
1.2E9
1.1E9
1.0E9
9.0E8
8.0E8
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0
Adaptive BST
VSWR
BST
Freq_sweep
Agilent Confidential 41
Antenna
EMPro Antenna Diversity calculations and MIMO System Simulations Solve The Multiple Reflection Problem For Increased Bandwidth EMPro Assures Antenna Diversity In All Environments Indoor Environment MIMO Antennas
PDF
Outdoor Environment
42
PDF
ADS 2009 enables frontend Co-Design with: Signal Integrity • • • • • •
Channel Simulator GPU Accelerated Transient Simulator New, fast eye diagram measurements Djordjevic loss model for fast, causal multilayer models Causality-corrected microstrip and stripline models Threaded impulse characterization for faster convolution
Simulation • • • • • •
Support HSPICE .pat statement Arbitrary Jitter Analysis Multi-threaded harmonic balance Improved Passive Circuit Design Guide Wireless Libraries (WiMedia v1.2, 3GPP/ LTE MIMO v8.3.0 & v8.4.0) Pole-zero custom frequency-dependent voltage and current sources
EMDS G2 full 3DEM • • • •
43
3D parameterized components Improved mesher and solver Fast frequency sweep for iterative solver Symmetry planes
Momentum G2 Planar 3DEM • • • • •
Improved meshing Improved resistance modeling Port re-sequence for easy S-Parameter interpretation Substrate stack driven viewing utilities Enhancements to Broadband Spice Model Generator for passivity and causality
Physical Layout • • • •
DRC for Flattened Layout DRC 3rd-party integration (Assura, Calibre, MailDRC) PDK Builder for Schematic Enhanced layout and SMT connectivity transfer from Allegro PCB, APD and SIP
Usability • • • • •
AEL Debugger for ADS customization Data Display snap-to-grid alignment New 50 ADS examples Direct drawing of pass-fail limit lines on plots Fast variable setup tab for statistics and DOE simulation
Summary ADS 2009 enables front-end Co-Design with: IC Design
1.
Multi-Technology Simulation Platform •
Multi-threading
•
Acceleration
•
Channel Simulator
• 2.
3.
44
LTE, Wimax, WiMedia verification libraries
Packaged IC
Multi-technology Model Support •
X-parameters
•
3D EM integration Interoperability with backend design platforms
Mounted on Board
