Transcript
Analog Application Note
AAN-17
REQUIRED EQUIPMENT n
CDK8307 datasheet
n
Logic analyzer or other data capture hardware
n
Analog high performance signal source
n
Lab power supply, +5V fixed or adjustable
n
Antialiasing filter
n
Low jitter clock source
Product Description The CEB8307 Evaluation Board is an evaluation platform for the CDK8307x family of Analog-to-Digital converters (ADC). The board contains the ADC chip with necessary clock input circuitry and input signal conditioning. The LVDS output signals are converted to parallel CMOS format for each channel using a Virtex-5 FPGA from Xilinx. A microcontroller is used to implement a USB interface allowing the board to be fully controlled by computer software. The software is Java-based and can run on all standard Java installations under all commonly used operating systems. The evaluation board is configured to interface with commonly used test equipment. Output data can be captured with a logic analyzer or other Data Capture hardware. The input clock can be supplied by CMOS or LVDS clock sources selectable by replacing a few components on the board.
Test Setup Block Diagram Low Noise, Low Jitter Sine Source, e.g. Aeroflex/IFR/Marconi 2041
Bandpass Filter
Evaluation Board
Low Jitter Clock Source e.g. Stanford Research CG635
Logic Analyzer or Other Data Capture Hardware
Clock Circuitry
Rev 1A
1 to 3dB Attenuator (optional)
Input Circuitry
ADC
+5V Power Supply MCU
FPGA
De-Serializers & Buffers
USB Interface
This device can be damaged by ESD. Even though this product is protected with state-of-the-art ESD protection circuitry, damage may occur if the device is not handled with appropriate precautions. ESD damage may range from device failure to performance degradation. Analog circuitry may be more susceptible to damage as very small parametric changes can result in specification incompliance.
Exar Corporation 48720 Kato Road, Fremont CA 94538, USA
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
CEB8307 Evaluation Board User Guide for CDK8307 Family of Analog-to-Digital Converters
www.exar.com Tel. +1 510 668-7000 - Fax. +1 510 668-7001
Analog Application Note
Quick Start Guide The Evaluation Board is configured and tested for the following conditions during manufacturing. n
1.8V CMOS clock input
The evaluation board can either be configured to use external or internal power regulators. The default configuration is to use the on-board regulators.
11. Start the configuration tool. 12. The next step is to set a test pattern to verify the signal flow. This can be done by loading the script StartupRamp14b.txt. 13. Verify that the output is a ramp.
The following procedure describes how to initialize measurements for these conditions. Details on how the board can be modified for other conditions are described in later sections of this document. 1.
Find the ADC data sheet and check functionality and description of each pin on the device.
2.
Connect +5V and ground to JP3 (upper left corner) and JP7 (top center) as indicated on the PCB. (The other pins on JP3 and JP7 are not used, unless unregulated supply is selected with JP1/JP2.) Measure and verify analog supply voltage on the top side of C29 (typ 1.8V). Adjust with adjacent potmeter, R_POT2) if necessary or if other voltages are desired.
4.
Check that jumpers are present at JP1/JP2 in the “rightmost” position. Note that only one of the two top jumpers, pin 5 and 6 marked AVDD3, should be mounted. The top jumper is mounted for 3.3V CMOS logic levels on the SPI interface. The second top jumper is mounted for 1.8V logic levels.
5.
Check that there are no jumpers applied to JP4
6.
Check that LED1 (FPGA Programmed) is illuminated. If not, press the FPGA_PROG button
7.
Apply clock signal to SMA connector, CLK. Use CMOS levels. See detailed instructions in the Clock Generation section if other logic formats are desired.
8.
9.
Connect a data capture unit to CON_OUT1 to CON_ OUT8 to capture ADC output data. Output data are in 3.3V CMOS format. The pinout of CON_OUTx is shown in section Digital Outputs. For 12-bit ADC output the data will be aligned with MSB. Hence, the 2 LSB bits are tied low. Connect a USB cable between the computer and the USB connector on the PCB.
14. Apply input signals to the desired channels. SMA connectors X1 to X8 corresponds to ADC input channels 1 to 8, respectively. Note that high performance (low noise and low phase noise) sources must be used together with bandpass filters. This is necessary to obtain sufficiently low noise and harmonic distortion. It may in some instances be advantageous to use 1 to 3 dB attenuators between the filter and the evaluation board. This will reduce the problem of impedance mismatch between the evaluation board and the cable. Such mismatch will result in reflections and would significantly impact both harmonic distortion and noise. 15. It is necessary to mount the filter as close to the SMA connectors as possible. Use maximum 5 cm / 2 inch cable length. The picture in figure 2 shows the recommended connection between the filter and the evaluation board. See the Analog Inputs section for details. 16. Load the NormalRun14b.txt script or turn off the ramp LVDS test mode.
Analog Inputs The quality of the input signals is the most important criterion to obtain good measurement results. The following points must be taken into consideration. ■■
10. Configure the serial USB interface. Refer to section ©2009-2013 Exar Corporation
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Select a signal source with low noise and low phase noise. Excellent results are obtained with the Aeroflex/ IFR/Marconi 2041. Rev 1
Rev 1
3.
Figure 1: Recommended Connection of Filter
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
Single +5V supply with on-board regulators for each power domain n
“Setup of CEB8307 configuration tool and USB connection“ at the end of this document for detailed instructions on setting up the software.
Analog Application Note
■■
■■
■■
The input network on this PCB is optimized for fast settling. Hence there are no capacitors to attenuate the kickback from the ADC input. This has proven to yield the best results over a wide range of input and sampling frequencies as long as the filter is mounted close to the input connector. However, if a cable is used between the board and filter, the kickback will travel over the cable, be reflected in the filter and add an error component to the signal causing severe harmonic distortion. The input of the Evaluation Board assumes a 50Ω source. However, with filters, transformers and cables it is hard to ensure impedances of 50Ω for a wide frequency range. In addition, the sampling capacitor of the ADC must be charged for each clock cycle. This results in a kickback into the transformer that will propagate back into the filter. Such reflections may severely impact performance. The input network can be optimized if a long cable is required between the filter and the board input. The configuration in Figure 2 is designed to attenuate the kickback from the ADC and to provide an input impedance that looks as resistive as possible for frequencies below Nyquist. Values of the series inductor will however depend on board design and conversion rate. In some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pF) may improve results. However, the impedance match may become worse.
Optional
68Ω
33Ω
220Ω
120nH
22pF
ADC
33Ω
Figure 2: Alternative Input Network ■■
To reduce the problems of reflections, an attenuator can be added between the filter and the Evaluation Board. Best performance is obtained with 3 to 6dB attenuators (or even a 50Ω termination). It might however be hard to get sufficient signal level into the ADC in such case. Using 1 to 3dB attenuators may be a good tradeoff.
The ADC performance is optimized by applying a differential signal to the analog inputs. The transformers TR1 to TR8 are configured to convert the input signal to differential with the common mode voltage set by the center tap. The transformer can be used for frequencies from 2 MHz and up. The common mode voltage of the input signals are controlled by the common mode output voltage pin of the ADC when the bottom jumper of JP1/JP2 is applied at the “rightmost” position. Other voltage levels can be applied from an external source if the jumper is applied in the “leftmost” position of JP1/JP2. The terminal for the external voltage can be found at the bottom pin of JP3 (top left side of the board) labeled “VCM_EXT”.
Clock Generation The clock input to the ADC accepts CMOS, LVDS, LVPECL and sine wave inputs, and can be provided via SMA connectors directly. An on-board crystal oscillator (not mounted) can also be used. The board is configured to use the external SMA connector, X6, with CMOS format. It is of utmost importance to supply a clock with low jitter. Poor jitter performance will directly result in reduced SNR. The SNR contribution from jitter is given by equation (1) assuming a full scale input signal at frequency, FIN, and RMS-jitter,
εRMS, measured in seconds.
SNR = -20log (2 * π * FIN *
εRMS)
One can see that a 1ps clock jitter with a 25MHz full scale ©2009-2013 Exar Corporation
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Rev 1
■■
Make sure that the bandpass filter is mounted as close to the input connectors as possible. Using the connection in Figure 1 has proven to yield the best results over a wide range of sampling rates and input signal frequencies.
120nH
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
■■
Apply bandpass filters between the signal source and the Evaluation Board. This is required to obtain sufficiently low white noise levels and to reduce harmonic components from the signal source. Excellent results have been obtained with the TTE (www.tte.com) filter series Q56T or KC4T. Make sure that large magnetic cores are used in the filters to avoid nonlinearity due to core saturation. Alternative vendors are K&L Microwave (www.klmicrowave.com) and Allen Avionics Inc. (www. allenavionics.com). The input signal after filtering could be checked with a spectrum analyzer to ensure that noise and harmonic levels are significantly better than the theoretical contribution from the ADC.
Analog Application Note
input signal results in an additional SNR component of
tion: The external 3.3V supply is selected for U6. Apply external voltage to JP7 on the pin labeled 3V3_EXT
76dBc. Because of this the clock signal should be treated with the same care as the analog inputs to the ADC. Jitter numbers below 1ps RMS has been achieved with the LVDS and LVPECL signals with adjustable amplitude. The following modifications are necessary to convert the Evaluation Board clock input to other formats than CMOS: Convert from CMOS to LVDS: ■■
Remove R55
■■
Mount 100Ω resistor at R56
■■
4. Jumper applied at pin 5 in the “leftmost” position: The external 1.8V supply is selected for U6. Apply external voltage to JP3 on the pin labeled 1V8 Attention: pin 5 and pin 6 should never be applied at the same time.
Check if the clock source requires decoupling to ground and, if necessary, add suitable resistors at R45 and R55 (the CG635 requires 50Ω to ground on each output instead of 100Ω differential)
Convert from CMOS to LVPECL: ■■
■■
Figure 3: Default Power Jumper Settings
Remove R55 Mount suitable resistors at R54 and R55. CG635 requires 50Ω load to ground on each input
Digital Control Signals The digital control signals are applied to the ADC through an SPI interface. In addition, there is a seperate Power Down pin for the ADC and a Reset pin for the SPI interface. Both the control pins and the SPI interface is controlled by a microcontroller on the PCB. A USB interface is used to apply commands to the microcontroller from a computer. For detailed information about the software, see section “Software Usage” and “Setup of CEB8307 configuration tool and USB connection”.
The LVDS output data from CDK8307 is captured by the Virtex-5 FPGA residing on the Evaluation Board. The standard FPGA code captures the serial LVDS data, converts it to parallel 3.3V CMOS format and outputs it on the output connectors CON_OUTx. A buffered version of the LVDS frame clock is present on each of the CON_OUT connectors, pin 16. This clock can be used as master clock for the logic analyzer or other data capture device. The data bits are set up on the rising edge of the output clock signal. The pinout of CON_OUTx is designed to interface directly with Agilent Logic Analyzer Termination Adapter (model 01650-63203). The pinout is shown in Figure 4. MSB corresponds to pin 13 and LSB to pin 0. The data are always aligned with MSB. This means that bit 13 always is the MSB. When the ADC is configured for 14 bit output, bit 0 is the LSB. When the ADC is configured for 12-bit operation, bit 2 will be the LSB and bit 0 and 1 are tied low. PCB
1. Jumper applied at pin 6 (top) in the “rightmost position”: The regulated 3.3V supply is selected for U6
2
4
6
8
10
12
NC CLK NC
GND
1
3
5
7
9
11
13 NC NC
CON_OUTx
2. Jumper applied at pin 6 (top) in the “leftmost” posi©2009-2013 Exar Corporation
0
Figure 4. CON_OUT Pinout (Top View) 4/24
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Rev 1
The digital control signals from the microcontroller to the CDK8307 are buffered by U6 which is a level shifting buffer. The primary side of U6 is supplied with the same supply voltage as the microcontroller. The secondary side of U6 is supplied through pin 5 or 6 (top two pins) of jumper JP1/JP2. See Figure 3. The same supply is connected to pin 60 of CDK8307 to ensure that the I/O pins of CDK8307 are supplied at the same voltage as the SPI pins are driven with. Four different options are available:
Digital Outputs
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
Stanford Research CG635 clock source. It provides CMOS,
3. Jumper applied at pin 5 in the “rightmost” position: The regulated 1.8V supply is selected for U6
Analog Application Note
FPGA Deserialization
Software Usage Start by inserting the software CD. It includes the graphical user interface for configuring the ADC and a USB driver setup file for the windows usbser.sys driver. Plug an USB cable between the evaluation board and the PC. Refer to section “Setup of CEB8307 configuration tool and USB connection“ at the end of this document for detailed instructions on setting up the software. The ADC configuration tool is a java program, and should run on standard java installations. Start the program by clicking on the “CEB8307config.jar” file that is located on the CDROM. Connect to the evaluation board by selecting the correct (most often the highest numbered) serial port (COM/ttyS) in the configuration dialog. Figure 19 is a screen shot of the configuration interface. The GUI is divided in different sections. In the upper right corner, there is a logo and a table over the hardware and software versions. Always include this information when making support quires.
Just right of the boxes for sending SPI commands and MCU commands there is a history box. All commands that are sent on the serial USB interface will end up in this box. The history can be saved and later loaded again. When it is loaded, all commands are immediately written to the serial USB interface. On the right side of the history box there are two ADC control signal buttons. They control the RESETN and PD pins on the converter. By setting “PD: high”, the converter is set in power down, regardless of the register settings. When PD is set to “low” the ADC resumes operation from the state it had before Power Down. ©2009-2013 Exar Corporation
On the bottom half of the screen, there are configuration buttons for the most common ADC functions. These buttons are initialized to the default reset values of the ADC. To change the configuration, make adjustments to the desired settings, and press Apply. When pressing Apply, all registers that have been changed are written to the SPI interface. By pressing Apply all, all registers are written to the SPI interface, regardless if they have been changed or not. In the GUI section “Advanced SPI control” each button corresponds to an ADC register In some cases there are more than one button for each register controlling different register bits. These register settings are documented in the CDK8307 datasheet. Refer to the datasheet description of the registers for detailed information about the possible settings.
Controlling the FPGA Just below the “Send MCU command” button, there are three buttons for controlling the FPGA deserialization function. SYN: Pressing this button triggers the internal FPGA algorithm that aligns the internal clocking with the LCLK input clock. For 90 (or 270) deg phase on LCLK in DDR mode this ensures sampling of data and FCLK in the middle of the data window. INC: Increases the internal FPGA delay on LCLK. The sample point of data and FCLK will be delayed. This function can be used if bit errors appear in the output data to fine tune the FPGA data sampling. DEC: Decreases the internal FPGA delay on LCLK. The sample point of data and FCLK will be advanced. This function can be used if bit errors appear in the output data to fine tune the FPGA data sampling. Note: The internal FPGA delay on LCLK is adjusted in 63 steps of approximately 75ps. Increasing the delay beyond 63 will wrap to 0, causing a large change in the delay. Likewise, decreasing below 0 will wrap to 63.
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Rev 1
On the top left corner there is an input form for sending bare SPI commands. Just below there is a box for sending general MCU commands over the RS232 interface. The Soft Reset button sets the configuration back to default.
Commonly Used Registers
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
The FPGA data deserialization program is set up to work on the default ADC configuration for 12 or 14 bit output only. This means that the deserialization will work only for DDR mode, in 90 (or 270) deg phase mode. 0 and 180 deg phase modes may also be used, but manual timing adjustment may be needed by using the INC or DEC buttons. Data on the CON_OUT connectors will have correct order for LSB first mode only.
By setting “Reset_N: low”, all registers are reset to default value. Set “Reset_N: high” before writing to the SPI interface. Check datasheet for details.
Analog Application Note
IO Connectors This section is discussing the different IO connectors used to configure the evaluation board.
JTAG for PROM and FPGA The JTAG is not in use for normal board usage. The JTAG connector is located at the middle top of the board and labeled JTAG_PROM. This is the JTAG connector for the PROM and the FPGA. JP9 is used to configure the JTAG chain. The default jumper position is a jumper between TDI_PROM and TDI_PORT, and a jumper between TDI_FPGA and TDO_PROM. This sets up the FPGA and PROM in a “FPGA Master Serial Mode” To bypass the FPGA or the PROM, set the jumpers according to figure 7. For advanced FPGA usage, please refer to the Xilinx Virtex-5 documentation.
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
Figure 5: Print Board Mark-Up
Rev 1
Figure 6: JTAG Configuration for PROM and FPGA
USB The USB connector is located at the right side of the board.
JTAG for MCU The MCU JTAG is not in use for normal board usage. The JTAG connector for the AVR32 MCU is located at the right side of the board, below the USB connector. It is used to configure and program the AVR32. ©2009-2013 Exar Corporation
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Analog Application Note
Push Buttons on the Evaluation Board Button
Description Loads the program stored in the PROM into the FPGA
FPGA_RESET
Not used
MCU_RESET
Reloads and restarts the running program in the MCU. Power cycles the ADC. The USB interface is reinitialized.
Jumper Descriptions Jumper #
Default setting
Description
JP2/JP1 1
Right Position
Applies the common mode voltage generated by the ADC (pin 53) to the transformer center taps
2
Right Position
Selects analog supply voltage from the regulator
3
Right Position
Selects reference supply voltage (AVDD_REF) from the regulator
4
Right Position
Selects digital supply voltage from the regulator
5
Open
6
Right Position
Selects the regulated 3.3V supply voltage to the level shifting buffer (U6) and the I/O supply (pin 60) of CDK8307
JP4 M0
Open
M1
Open
M2
Open
Sets up the FPGA to read configuration data from the PROM (U10)
JP9 TDI PROM TDI PORT TDI FPGA TDO PROM TDO FPGA/PORT
Jumper Applied Jumper Applied
Refer to Xilinx Virtex-5 documentation
Open
CEB8307 Evaluation Board Bill of Materials (BOM) Qty Value
Device
Parts
CDK8307x
CDK8307x
UASD
1
5VLX30FF324
5VLX30FF324
U2
1
XCF08P
XCF08P
1
AT32UC3A0VQFP144
AT32UC3A0VQFP144
1
AT45DB642D
AT45DB642D
Maufacturer
Part #
QFN64
Exar
CDK8307xILP64
1FF324C
Xilinx
XC5VLX30-1FF324C
U10
VOG48
Xilinx
XCF08PVOG48C
U4
144-LQFP
Atmel
AT32UC3A0512-ALUT
U8
8-CASON
Atmel
AT45DB642D-CNU
LLP-8
National Semiconductor
LP38500SD-ADJ
TO-263 THIN
National Semiconductor
LP38500TJ-ADJ
SOT23-5
Maxim
MAX825_EUK-T SN74LVC8T245 ADT1-1WT
1
LP38500
LP38500
U3
3
LP38500TJ
LP38500TJ
U1, U5, U7
1
MAX825
MAX825
U9
1
SN74LVC8T245
SN74LVC8T245
U6
SSOP24
Texas Instrument
8
ADT1-1WT
ADT1-1WT
TR1, TR2, TR3, TR4, TR5, TR6, TR7, TR8
CD542
Mini-Circuits
©2009-2013 Exar Corporation
7/24
Rev 1
Rev 1
1
Package
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
FPGA_PROG
Analog Application Note
CEB8307 Evaluation Board Bill of Materials (BOM) Continued Qty Value
Device
Parts
Package
ECS-.327-6-17X-TR
CRYSTALMM20SS
Q3
8mm x 3.8mm
1
CRYSTALCTS406
CRYSTALCTS406
Q1
6.0mm x 3.5mm
1
ECS-3953M-240AU-TR
XO-ECS395
QG1
16
YC248
YC248
U$1, U$2, U$3, U$4, U$5, U$6, U$7, U$8, U$9, U$10, U$11, U$12, U$13, U$14, U$15, U$16
1
PN61729-S
PN61729-S
1
GREEN
1
Part #
ECS Inc
ECS-.327-6-17X-TR
CTS
406C35B12M28800
ECS Inc
ECS-3953M-240AU-TR
0603 x 8 (Convex)
Yageo
YC248-JR-0722RL
XUSB
Type B Single, Right angle
Molex
67068-9000
LEDCHIPLED_0805
LED1
805
Osram
LG R971-KN-1-020-R18
CZRER52C3V3
DIODE-SMD
D1
503
Comchip
CZRER52C3V3
10
BU-SMA-H
BU-SMA-H
CLK, CLKN, X1, X2, X3, X4, X5, X6, X7, X8
BU-SMA-H
3
DTSM-6
DTSM-6
FPGA_PROG, FPGA_RESET, MCU_RESET
6 x 6 mm
APEM Components
ADTSM62RV
1
87758-1416
87758-1416
JTAG_PROM
Molex
87831-1420
1
20k
VAR_RES
R_POT2
BOURNS
3296W-1-203LF
4
PINHD-1X1
PINHD-1X1
JP6, JP10, JP11, JP12
1
PINHD-1X4
MPT-4
JP7
Term Block 2.54 mm
1
PINHD-1X5
MPT-5
JP3
Term Block 2.54 mm
2
PINHD-1X5
PINHD-1X5
JP5, JP9
PINHEAD 2.54 mm
1
PINHD-1X6
PINHD-1X6
JP2
PINHEAD 2.54 mm
8
PINHD-2X10
PINHD-2X10
CON_OUT1, CON_OUT2, CON_ OUT3, CON_OUT4, CON_OUT5, CON_OUT6, CON_OUT7, CON_ OUT8
PINHEAD 2.54 mm
1
PINHD-2X3
PINHD-2X3
JP4
PINHEAD 2.54 mm
1
PINHD-2X5
PINHD-2X5
JP8
PINHEAD 2.54 mm
1
PINHD-2X6
PINHD-2X6
JP1
PINHEAD 2.54 mm
3
47nF
C-EUC0402E
C12, C13, C14
402
402
SMD 7mm x 5mm
Through Hole 2 mm 3296W PINHEAD 2.54 mm
220nF
C-EUC0402E
1
470pF
C-EUC0603E
C58
603
3
2.7uF
C-EUC0603E
C47, C59, C60
603
4
22pF
C-EUC0603E
C50, C51, C52, C53
603
5
2.7nF
C-EUC0603E
C39, C40, C41, C42, C49
603
©2009-2013 Exar Corporation
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Rev 1
33
"C65, C66, C69, C70, C71, C72, C73, C75, C77, C78, C79, C80, C81, C82, C83, C84, C85, C86, C87, C88, C89, C90, C91, C92, C93, C94, C95, C96, C97, C98, C99, C100, C101"
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
1
Maufacturer
Rev 1
Analog Application Note
CEB8307 Evaluation Board Bill of Materials (BOM) Continued Qty Value
Device
Parts
Package
2.2uF
C-EUC0603E
C1, C19, C23, C26, C15, C16
603
9
47nF
C-EUC0603E
C68, C74, C76, C102, C103, C104, C105, C106, C108
603
15
33nF
C-EUC0603E
C27, C33, C34, C35, C36, C43, C44, C45, C46, C55, C56, C57, C61, C63, C64
603
603
21
100nF
C-EUC0603E
C2, C5, C6, C7, C8, C9, C10, C11, C20, C24, C30, C31, C32, C37, C38, C54, C62, C67, C109, C110, C111
4
4.7uF
C-EUC0805
C3, C21, C25, C28
805
1
4.7uF
C-EUC1206
C48
1206
4
100uF
C-EUC1210
C4, C18, C22, C29
1210
1
47k
R-EU_R0603
R36
603
1
330
R-EU_R0603
R47
603
1
15k
R-EU_R0603
R30
603
1
10
R-EU_R0603
R38
603
1
33k
R-EU_R0603
R2
603
1
6.8k
R-EU_R0603
R34
603
1
12k
R-EU_R0603
R29
603
2
100k
R-EU_R0603
R41, R42
603
3
4.7k
R-EU_R0603
R45, R46, R53
603
5
0
R-EU_R0603
R4, R6, R31, R55, RSD
603 603
7
10k
R-EU_R0603
R3, R35, R37, R40, R50, R51, R52
10
39
R-EU_R0603
R7, R9, R12, R15, R18, R21, R24, R27, R43, R44
603
10
100
R-EU_R0603
R11, R14, R17, R20, R23, R26, R33, R48, R49, R65
603
603
33
R-EU_R0603
1
NC
C-EUC0402E
C17
402
1
NC
C-EUC0603E
C107
603
R-EU_R0603
"R1, R5, R8, R10, R13, R16, R19, R22, R25, R28, R32, R39, R54, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75"
603
32
NC
©2009-2013 Exar Corporation
9/24
Rev 1
16
"RINN1, RINN2, RINN3, RINN4, RINN5, RINN6, RINN7, RINN8, RINP1, RINP2, RINP3, RINP4, RINP5, RINP6, RINP7, RINP8"
Part #
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
6
Maufacturer
Rev 1
Analog Application Note
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs Rev 1
Figure 7. CEB8307 Schematic Diagram (1 of 5) ©2009-2013 Exar Corporation
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Analog Application Note
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs Rev 1
Figure 8. CEB8307 Schematic Diagram (2 of 5) ©2009-2013 Exar Corporation
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Analog Application Note
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs Rev 1
Figure 9. CEB8307 Schematic Diagram (3 of 5) ©2009-2013 Exar Corporation
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Analog Application Note
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs Rev 1
Figure 10. CEB8307 Schematic Diagram (4 of 5) ©2009-2013 Exar Corporation
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Figure 11. CEB8307 Schematic Diagram (5 of 5) ©2009-2013 Exar Corporation
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Figure 12. All Routing Layers ©2009-2013 Exar Corporation
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Figure 13. Component Side (Top View) note: Top layer metal fill (ground) not shown ©2009-2013 Exar Corporation
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Figure 14. Internal Layer 1, Ground Plane (Top View) ©2009-2013 Exar Corporation
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Figure 15. Internal Layer 2, Routing Layer (Top View) ©2009-2013 Exar Corporation
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Figure 16. Internal Layer 3, Routing Layer (Top View) ©2009-2013 Exar Corporation
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Figure 17. Internal Layer 4, Power Plane (Top View) ©2009-2013 Exar Corporation
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Figure 18. Solder Side (Bottom View) ©2009-2013 Exar Corporation
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Setup of Configuration Tool and USB Connection
The configuration tool is located on the CD that follows the evaluation board. You can also download the software from the Exar website: http://www.exar.com 1. Insert software CD, or unpack the downloaded software. 2. Put an USB cable between the PC and the CEB8307. A screen similar to the one below should appear when the board is connected.
6. Start the CEB8307 configuration tool by running the file CEB8307config.jar. 7. Choose which COM port to communicate through. Usually it is the one with the highest number. 8. The CEB8307 configuration tool will start up. Figure 19 shows the interface.
Troubleshooting 1. The configuration tool looses its connection to the evaluation board ■■
Close the program
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Press the MCU_reset button on the board
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Restart the program
2. The configuration program does not seem to give any result on the ADC function ■■
See point 1
3. The “FPGA_programmed” LED does not light up ■■ ■■
Press the “FPGA_program button on the PCB If this does not work, switch off and on the power supplies and verify that all supply voltages are correct
4. There are no signals on the output 3. If installing from a CDROM, press “Next”. If installing downloaded software, select “Install from a list or specific location” and press “Next”. Then browse to the location the downloaded software was unpacked and find the file CEB8307.inf.
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Check that the right channel is connected to the data capture tool Check for activity on each pin of CON_OUTX Try reprogramming the FPGA by pressing the “FPGA_ program” button on the PCB Close configuration tool, press MCU_reset, open configuration tool Check that +5V is applied on both JP3 and JP7
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Check the power level on C29, and adjust to 1.8V
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Check the signal level on the signal source
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Try setting up an LVDS test pattern with the “Test mode” GUI buttons
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©2009-2013 Exar Corporation
Switch on and off “Reset_N” and “PD” using the GUI. Verify that ADC control signals are as expected on the JP5 pins on the PCB
Check that the frequency on the signal source corresponds to the filter passband Check that all jumpers are present and correct according to the Jumper Descriptions table Measure supply voltages at the center pins of JP1/ JP2. See Figure 3 Rev 1
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4. On windows, install USB serial driver. Press “Continue Anyway” when you are informed that the evaluation board has not passed Windows Logo testing.
Press the “Soft Reset” button in the GUI
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
The Sun Java Run time environment must be installed and setup correctly for this configuration tool to work. You can download and install java from this website: http://www. java.com/getjava
5. Windows will now install a new COM port where the configuration tool can communicate with the board. Optionally, one can see what COM port number has been assigned in the Device manager.
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Figure 19: CEB8307 Configuration Tool Interface
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This evaluation board and accessories are intended for use for Engineering, Evaluation and Demonstration purposes only. It is not intended for consumer use and is hence not tested to comply with relevant FCC or other regulatory body rules. Operation of this evaluation board may cause interference with radio communications, and the user will bear the full responsibility towards the authorities. Important Notice
For Further Assistance: Exar Corporation Headquarters and Sales Offices 48720 Kato Road Tel.: +1 (510) 668-7000 Fremont, CA 94538 - USA Fax: +1 (510) 668-7001 www.exar.com NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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This evaluation board is intended used in a professional electronic lab environment. Personnel handling the equipment must have electronics training and must show good engineering practice. The evaluation board is not intended to be complete regarding required protective considerations as product safety and environmental information and warnings. It does also not fall withing the European Union, FCC, UL or CE directives regarding restricted substances (RoHS), recycling (WEEE) and electromagnetic compatibility, and may not meet all requirements of these and related directives.
AAN-17 CEB8307 Evaluation Board User Guide for CDK8307 ADCs
FCC Warning
