Transcript
INTERNET OF THINGS: DRIVING TECHNOLOGY TRENDS ON SYSTEM SCALING AND SEMICONDUCTOR MANUFACTURING EFFECTIVENESS LODE LAUWERS VICE PRESIDENT, PHD BUSINESS DEVELOPMENT & SALES
MAY 2015
THE CONFAB 2015: Exploring the Edges of IoT and Mobile
THE IOT PREMISE: EveryThing connected, managed, secured Billions of wirelessly interconnected devices will communicate intelligently
Smart Watch Smart Phones
Smart Glasses
Drones Laptop
Smart Cars
Smart Textiles Smart Homes
Source: http://blogs.jabil.com/2014/08/13/internet-of-things-infographic/
Source: Market Realist
#CONNECTED DEVICES: A MATTER OF MATH
Source: Bosch; IDC
Source: Bosch; IDC
KEY DRIVERS IN IOT ECOSYSTEM
Source: Bosch
IOT CHALLENGES: READINESS CHECKLIST
Source: TI
TECHNOLOGY CHALLENGES
IOT SYSTEM INNOVATION NEW SYSTEM ARCHITECTURE
SPECIALTY DEVICE
NEW APPLICATION ULP DRIVEN
NOVEL MEMORY TECHNOLOGY
System applications requirements 10 Mbp/s
1Mbp/s
1Gbp/s
100Gbp/s
1Tbp/s
I/O bandwidth
Power 500 Watt (mains level)
Performance: Operations per second (Ops)
Core
I/O bandwidth: Bits per second (bp/s) Off Chip Memory
Memory: # Bits
Stationary
100 Watt
1Watt (battery level)
Mobile
100mWatt (battery level)
Ambient 100mW (ambient level) 10Mop/s
10 Gop/s
100Gop/s
1Top/s
1Pop/s
Performance
System applications requirements 10 Mbp/s
1Mbp/s
1Gbp/s
100Gbp/s
1Tbp/s
I/O bandwidth
Power 500 Watt (mains level)
Performance: Operations per second (Ops)
Core
I/O bandwidth: Bits per second (bp/s) Off Chip Memory
Memory: # Bits
Stationary
100 Watt
Increased Performance @ constant power density Wired, heat dissipation constrained
1Watt (battery level)
Mobile Increased Performance @ constant leakage Cost trade-off Wireless, battery constrained
100mWatt (battery level)
Ambient Ultra low power, cost trade-off Wireless, energy scavengers
100mW (ambient level) 10Mop/s
10 Gop/s
100Gop/s
1Top/s
1Pop/s
Performance
System applications requirements 10 Mbp/s
1Mbp/s
1Gbp/s
100Gbp/s
1Tbp/s
I/O bandwidth
Power 500 Watt (mains level)
Performance: Operations per second (Ops)
Core
I/O bandwidth: Bits per second (bp/s) Off Chip Memory
Memory: # Bits
100 Watt
1Watt (battery level)
More performance per Watt: 1. Technology: transistor improvement 2. Circuit: e.g. Near Threshold Computing (NTC) 3. Architecture: e.g. Multi-Core, Neuromorphic
100mWatt (battery level)
100mW (ambient level) 10Mop/s
10 Gop/s
100Gop/s
1Top/s
1Pop/s
Performance
Imec Logic Device Roadmap Device Technology Features
Early
2013 - 2014
2015 - 2016
2017 - 2018
2019 - …
production
16 -14nm
10nm
7nm
5nm
Vdd (V)
0.8
0.8-0.7
0.7-0.5
0.7-0.5
Planar SOI
Device
SOI FinFET
SiGe/Ge channel
IIIV channel
Lateral Nanowire
FinFET (Bulk, SOI)
FinFet width (nm)
7-8nm
Improve 5-7nm Electrostatics
5nm
5nm
FinFET pitch (nm)
42-48nm
30-32nm
21-24nm
14-16nm
HKMG
HKMG
HKMG
HKMG
CPP (nm)
64-80nm
50-64nm
32-42nm
22-32nm
Channel n/p
Si / SiGe
Si / SiGe (Ge>80%)
Si / SiGe (Ge)
Si / SiGe (IIIV / Ge)
N S/D Si:P:C P S/D eSiGe (>60%) Low-k spacer
TBD
10-15nm
10nm
S/D Strain
Lgate (nm)
N S/D Si:P P S/D eSiGe (55%) Low-k spacer 20-25nm
N S/D Si:P:C P S/D eSiGe (>60%) Low-k spacer Improve Performance 15-20nm
FinFET (GAA, QW, SOI)
Vertical Nanowire
FinFET (Bulk, SOI), FDSOI
Gate Stack
imec confidential
Bulk FinFET
GAA lateral NW; (Vert. NW)
13
Improve Device Electrostatics From finfets to lateral nanowires Straight Fin FinW=7-8nm
200
Tapered Fin FinW=7-10nm
Subthreshold Swing (mV/dec)
120 45nm
110
N14 FinFET
100 90
SSSAT median (mV/dec)
Ultra-Thin Fin FinW=5nm
Closed symbols: D2 anneal 150
SiGe25% FinFET
100 SiGe25% GAA 50
0.1 0.2 Gate length (mm)
Gate-All-Around Nanowire Nanowire = 7nm SiGe25%
80 70 N5
N7
N10
FinFETs (Vdd ~ 0.7-0.8V)
N22
N14
60
10nm Gate-All-Around NW
10
15
20
25
30
Gate length (nm) Introduction of Gate-All-Around Nanowires to improve device electrostatics beyond N10
0.3
Improve Performance HETEROGENEOUS CHANNELS: INTEGRATING GE AND IIIV ON SI Extrinsic gm,sat (ms/mm)
PFET sGe
Si1-xGex (x>0.7)
Si(100)
Ge State-of-the-art Si FinFETs (0.8V)
sGe QW FinFET (STI last) (300mm Fab 2013) Si (0.5V)
TSMC Ge Bulk FinFET (0.5V) (IEDM 2013)
HAADF STEM Ssat (mV/dec)
NFET
InGaAs
Extrinsic gm,sat (ms/mm)
State of Art Si FinFETs (0.8V)
InP
Defect Trapping InP
Si
Si
InAs planar (Chang,,TSMC) IEDMIMEC-Lab 2013 (0.5V) InGaAs
planar
(0.5V)
Intel 2009 InGaAs planar
Sematech IEDM 2013 InGaAsEgard IEDM 2011
InGaA s planar
Lee, VLSI 2013 InAs channel Ko, Nature2010 InAs-O-I IMEC-300mm
InGaAs FinFET (0.5V) IMEC-300mm InGaAs GAA (0.5V)
Ssat (mV/dec)
Imec logic BEOL roadmap Improve RC parasitics and electro-migration
Early
2013 - 2014
2015 - 2016
2017 - 2018
2019 - …
production
16 -14nm
10nm
7nm
5nm
Contact
Self-aligned, adv. Contact beyond Ni
Self-aligned, adv. Contact beyond Ni
Self-aligned, adv. Contact beyond Ni
Self-aligned, adv. Contact beyond Ni
32-42nm
22-32nm
2.4 – 2.1 (air gaps 1.3x)
2.4 – 1.9 (air gaps 1.3x)
Contact pitch (nm) Low k Metallization
Metal pitch (nm) e-Memory (um2)
imec confidential
64-80nm 2.5 – 2.4
Lower Capacitance 50-64nm 2.5 – 2.3 (air gaps 1.3x)
PVD TaN/Ta
PVD TaN
CVD Mn(N)
PVD RF CuMn
CVD Co or Ru
CVD Ru or Co
ECD Cu
PVD Cu + ECD Cu
ECD seed + ECD Cu
ELD/CVD Cu; (Cu alternative)
28-32nm
20-22nm
SRAM < 0.05
SRAM < 0.05; (STT-RAM)
56-64nm SRAM 0.08-0.07
40-45nm Lower Resistance SRAM 0.06-0.05
16
Advanced Cu / low k engineering Significantly improved contact resistivity with Ti direct or MIS contact on Si-high P with laser anneal
Liner/barrier optimization, able to fill 22nm half pitch trench with good contact resistance
•
Local Interconnect + Trench Contact Fin S/D Epi
N10 via chains metallized W = 23nm
300 250 ( /um)
•
Low k
Metallization
Contact
200 150 100 50
D02
D03
D04
D05
POR
N10 metallization schemes benchmark
•
Demonstrated k=2.2 integrated; improved yield with UV treatment post deposition
C u
k=2.2
PATTERNING CHALLENGES EUV
Advanced patterning readiness 193i Multi patterning ▸
N10 BEOl SE EUV NXE3300 process (P=45nm)
Design
▸
N7 Fin SAQP 11nm L/S
Various alternative resist materials under evaluation
Fin Etch
M1 design flow for N7 (M1H+M1V)
▸
▸
Defectivity
Spacer 2 transfer
▸
Spacer 2 + Core 2 removal
Resist
Cut litho
Core 2 etch
9x pattern frequency multiplication for holes resulting in post-DSA 15nm hp
Post-trim 45nm hp
Mask
Process
Core 1 + spacer 1
▸
Process
N7 SAQP Process (FP=22nm))
▸
DSA
EUV pellicle development: membrane materials, primary mounting options, lifetime testing of integrated pellicle solutions
▸
Implementation
Process
Resolution
N10 BEOl LE^3 process (P=45nm)
▸
EUV lithography
Post-DSA 15nm hp
Defect reducton from >200 to 24/cm2
~24 defects /cm2 2.5 hr anneal (Oct “14)
Surface conditioning leading to better placement accuracy
LOGIC BEYOND 10nm FINFET
VERTICAL NANOWIRES, 2DMATERIALS.... THE NEXT SWITCH?
InAs Nano wire on <111> Si
FINDING THE NEXT SWITCH 101 NAND2 Benchmark: Praveen Raghavan (Imec) After Nikonov & Young (Intel 2012)
CMOSFET continues to be more efficient with scaling
100
Energy, fJ
MTJ Logic InAs TFET
10-1
Graphene Logic All Spin Logic
10-2
Ultimate Logic
Spin wave devices: no transport of electric charge, low energy and power, potentially slow (low wave velocity)
Spin Wave
10-3 10-1
100
101
102
103
104
Delay, ps Tunnel FET allows for Ultra Low Power (at cost of performance?) Spin Wave Computing adds functionality to or could replace existing CMOS technologies
Example: 1-bit full adder in CMOS and wave computing technology CMOS circuit 25 transistors > 100 interconnect vias
Wave computing circuit 5 transducers, 4 wave-guides and 5 vias
I1 C O I2
Process integration : 3D stacking on CMOS
CI
O
I = Input O = Output CI/CO = Carry in/out Transducer
Waveguide Power / Performance comparison
M2 M1 CMOS level
Circuit simplification leads to smaller circuits despite larger CD • Simplified process integration IMEC benchmarking indicates about 100× lower power for large arithmetic circuits •
•
The potential gain of Near Threshold Operation Power 500 Watt (mains level)
Ideal scaling ≈ VDD2 Actual scaling due to variability 1 MHz
100 Watt
1Watt (battery level)
40nm imec SOC chip reduced Vdd, T. Gemmeke, DATE 2015
100mWatt (battery level)
Scaling down to FinFET: Improved electrostatics allows better low Vdd operation
100mW (ambient level) 10Mop/s
10 Gop/s
100Gop/s
1Top/s
1Pop/s
Performance
System applications requirements 10 Mbp/s
1Mbp/s
1Gbp/s
100Gbp/s
1Tbp/s
I/O bandwidth
Power 500 Watt (mains level)
Performance: Operations per second (Ops)
Core
I/O bandwidth: Bits per second (bp/s) Off Chip Memory
Memory: # Bits
100 Watt
1Watt (battery level)
2.
100mWatt (battery level)
More data per Watt: 1. Technology: memory improvement System: e.g. more on chip memory (reduce off-chip BW)
100mW (ambient level) 10Mop/s
10 Gop/s
100Gop/s
1Top/s
1Pop/s
Performance
Need for new memory technologies Existing technologies challenged beyond 18nm
Cost/bit
Speed
Cache On Chip
6T
SRAM
1T1C
Working memory
DRAM
1T
Mass storage
Capacity
FLASH
MEMORY: STT RAMBEYOND 20nm
3D SONOS
STT MRAM
Re RAM
Flash
DRAM
Flash
replacement to 10nm
Non-volatile Memory
memory
cells implemented in vertical plugs consisting of 8,16,32 ... stacks
replacement beyond 20nm
<20 nm
Non-volatile
memory for both embedded and stand-alone applications
replacement beyond 10nm
Non-volatile High
memory
speed, low energy, superior scalability, CMOS compatible
Emerging Memory Benchmarking HDD
SRAM DRAM STT RAM FeRAM PCRAM RRAM
NOR
NAND
STT-MRAM has the best combination of speed/endurance for SRAM/DRAM replacement. RRAM has potential for e-NVM and IOT devices in cost tradeoff
Likely industry memory roadmap 2013
2012
2015
2014
2019
2017
eSTT-RAM
SRAM
Cache
2021
eDRAM NOR
eNVM
4Gb
8Gb
Planar FG
DRAM
RRAM, STT, PCM?
16Gb
DRAM: MIMCAP scaling with high-k optimization
Increasing need for nonvolatile embedded low-voltage memories (reduces off-chip BW). Path to ultra-low standby power systems.
STT-MRAM
STORAGE CLASS MEMORY
RRAM/CBRAM / PCM
128Gb
64Gb FLASH
STT-MRAM
16Gb CBRAM ISSCC 2014
FG
Conventional wrap Floating Gate
256Gb
512Gb
1Tb
20nm FG Micron
Planar Floating Gate Planar FG
3D NAND
3D NAND Samsung
E-NVM: 2B$ by 2018 Automotive, smart cards, New apps, IOT device...
3D & OPTICAL IO
Optical IO: extension of 3D stacking
Further performance boosting, extreme high-bandwidth
Optical interconnects using silicon photonics instead of electrical interconnects
Fabrication of optical components by using CMOS processing techniques and equipment
Need for best-in-class optical components
3D STACKING
MEMORY / LOGIC / 3D ENABLED SCALABLE I/O
Wide I/O memory on SOC logic
DRAM
Logic
Multi-die Memory stack - Combined with logic I/O circuit
DRAM
Logic
I/O
High performance devices: 3D integration using a Si Interposer
3D Technology Landscape 3D-SIC Wiring level
Global
3D-SOC Semi-global
Intermediate
Local
FEOL
2nd FEOL after stacking
2-tier stack
TSV Pitch
10 7 5 µm
Contact Pitch: Rel. density:
µbump pitch: 4020105µm 1 41664 Cu TSV –Cu pad: 10 7 5 µm 16 33 64
Stacking Method
3D-IC
D2D, D2W (W2W) Stacked die B2F / F2F
10 7 5 µm
5 64
1 µm 1600
“ TSV” after stack
2 µm 800
0.5 µm 6400
(Overlay 2nd tier defined by W2W alignment/bonding) W2W (D2W) Contact at bond interface F2F
W2W Contact after stacking F2F
“TSV” after stack
200 4 104
100 nm 1.6 105
Multi-tier FEOL
No TSV
< 100 nm > 1.6 105
(Overlay 2nd tier defined by litho scanner alignment) W2W Si layer-to-wafer stacking 2nd Tier Device fab. after stacking
Monolithic Device-level stacking
3D Advanced process integration TSV Scaling
Micro-bump and stacking
•
Via middle: successful integration 3x50um via middle TSV using WN barrier / ELD NiB seed and ECD Cu fill, resulting in champion reliability data
•
Via last on carrier: successful 5x50 &10x50um integration
•
Via last on bonded Si wafers: 2x20um TSV demonstrated Via middle Via last
•
ubump scalability towards 10um pitch using ELD coating
•
Cu-Cu bonding using ELD Au to enable Sn wetting
Si Au
2×20µm
5×50µm
10×50µm
3×50µm
Si •
Au
C u C u
Oxide-oxide bonding with bond strength >1.5mJ/m2, W2W overlay <1um
Thermo-mechanical impact •
Electrical: Estimation impact TSV and ubump stacking on N7 devices.
•
Micro-bump mechanical strain impact on high mobility channel devices
Package I/O Requirements
Optical I/O: system scaling projection CMOS tech node
20-28nm
14nm
10nm
7nm
5nm
I/O Bandwidth
2.5Tbps
5Tbps
10Tbps
25Tbps
50Tbps
I/O Energy
10pJ/bit
5pJ/bit
1-2pJ/bit
0.1-1pJ/bit
50-500fJ/bit
Channel Rate
up to 35Gb/s
up to 50Gb/s
up to 70Gb/s
up to 100Gb/s
up to 140Gb/s
Cost Target
$$$$/Tbps
$$$/Tbps
$$$/Tbps
$$/Tbps
$/Tbps
Optical I/O Distance & Appl.
5m to 2km Network
1m to 2km Backplane
5cm to 2km Board
5mm to 2km Interposer
1mm to 2km Chip
Source: LightCounting
Backplane/Board Package-to-package: 5cm-5m Logic-to-DRAM, logic-to-logic, ... Source: Intel
Chip/Interposer 1mm-5cm, interposer interconnects Logic-to-logic, logic-to-memory, ...
Datacenter Network Rack-to-rack:5m-500m+ Datacenter switch/router interconnect
Source: nVidia
Increasing system requirements for I/O drive Optical interconnects to ever shorter link distances
Optical I/O Technology Options
Package I/O Requirements
Optical I/O: Technology Roadmap CMOS tech node
20-28nm
14nm
10nm
7nm
5nm
I/O Bandwidth
2.5Tbps
5Tbps
10Tbps
25Tbps
50Tbps
I/O Energy
10pJ/bit
5pJ/bit
1-2pJ/bit
0.1-1pJ/bit
50-500fJ/bit
Channel Rate
up to 35Gb/s
up to 50Gb/s
up to 70Gb/s
up to 100Gb/s
up to 140Gb/s
Cost Target
$$$$/Tbps
$$$/Tbps
$$$/Tbps
$$/Tbps
$/Tbps
Optical I/O Distance & Appl.
5m to 2km Network
1m to 2km Backplane
5cm to 2km Board
5mm to 2km Interposer
1mm to 2km Chip
Packaging & Assembly
Optical Module on Board Optical
Optical Module on Package Optical
Optical Module Optical on Interposer Logic die
Optical Interposer
PCB
Optical PCB
Logic die
module
Logic die module
PCB
module
Logic die
Optical interposer
Wafer-bonded Optical Layer Logic layer
Optical PCB
Optical layer
Optical PCB
Lasers
Flip-chip III-V die
Flip-chip III-V die
Flip-chip III-V die
Flip-chip III-V die Monolithic Ge or III-V
Flip-chip III-V die Monolithic Ge or III-V
Modulators
Si Mach-Zehnder
Si Mach-Zehnder Ge EAM
Si SL-MZ or Ring Ge EAM
Si SL-MZ or Ring Ge or III-V EAM
Ge or III-V EAM Graphene/BTO
Detectors
Ge p-i-n PD
Ge p-i-n PD
Ge APD
Ge APD or III-V (A)PD
Graphene PD Ge APD or III-V (A)PD
WDM Multiplexing
CWDM-4
CWDM-4 DWDM-8
CWDM-4 DWDM-16
CWDM-4 DWDM-32
CWDM-4 DWDM-64
Optical Channel
SingleMode Fiber
SingleMode Fiber
SingleMode Fiber MultiCore Fiber Optical PCB
SingleMode Fiber MultiCore Fiber Optical PCB
SingleMode Fiber MultiCore Fiber Optical PCB
Stringent requirements for optical I/O (BW density, ernergy, cost) drives: • Optical module integration closer to the host IC • Development of a low-power, high density Silicon Photonics Technology
SMART APPLICATIONS
EMERGENCY & SECURITY
SMART LIVING
RETAIL & SHOPPING
INTERACTIVE GAMING
ENVIRONMENTAL MONITORING
AUTOMOTIVE
SPORTS
UTILITIES
AGRICULTURE
CONSUMER ELECTRONICS
HEALTHCARE
CONSTRUCTION
imec develops solutions for the
SENSOR MODULES WIRELESS CONNECTIVITY
FLEX TECHNOLOGIES
MULTI GAS SENSOR
AIR QUALITY MONITORING
ION SENSOR PLATFORM FOR FLUIDIC ANALYSIS WATER QUALITY MONITORING
HYPERSPECTRAL IMAGING UNIQUE SPECTRAL FINGERPRINT
HYPERSPECTRAL IMAGER
LOW-POWER - PORTABLE - AFFORDABLE
AGRICULTURE
CAMERAS ON DRONES INSPECT FOOD ON THE FIELD
Image courtesy of Volt Robotics
AGRICULTURE
CAMERAS ON DRONES INSPECT FOOD ON THE FIELD
RGB
HYPERSPECTRAL
FOOD QUALITY INSPECTION
automotive smart mobility
FOOD
MEDICAL GRADE CONSUMER DEVICE SKIN CARE MONITORING
low-power radio for personal area networks
RECORD LOW POWER 5mW: 2X BETTER THAN OFF THE SHELF STATE-OF-THE-ART PERFORMANCE: -95dBm SENSITIVITY MULTI-STANDARD
low-power radio for smart infrastructure
RECORD LOW POWER 4mW RX: 10X BETTER THAN OFF THE SHELF BEST IN CLASS PERFORMANCE: -120dBm SENSITIVITY MULTI-STANDARD HIGH LEVEL OF INTEGRATION
wifi for sensors smart buildings
LOWEST POWER: ACTIVE & DEEP SLEEP > 1KM DISTANCE PRE-STANDARD COMPLIANT SYSTEM: IEEE 802.11ah
SHORT DISTANCE - HIGH DATA RATE mm-WAVE : 60GHz PHASED ARRAY RADIO
© Panasonic
AUTONOMOUS DRIVING & ACTIVE SAFETY 79GHz RADIOS
© VOLVO
THIN-FILM ELECTRONICS RFIDS - NFC TAGS - MEMORIES - ANTENNAS - DISPLAYS - SENSORS
SMART RFID TAGS
BRAND AUTHENTICITY - ADVICE
SMART RFID TAGS
AUTHENTICITY - CORRECT USE
HIGH-RESOLUTION FLEXIBLE DISPLAYS
VERY THIN <25 MICRON - VERY FLEXIBLE - LOW COST
improved (chronic/acute) disease management
© CLEMSON UNIVERSITY
MEDICAL QUALITY DATA & SOLUTIONS IN EVERYONE’S REACH
empower people for disease prevention & healthier lifestyle
IMEC WEARABLE HEALTH AND LIFESTYLE MULTI-SENSOR PLATFORM
ULTRA-LOW POWER MULTI-SENSOR PLATFORM MEDICAL QUALITY DATA
ECG PATCH
ULTRA-LOW POWER EMBEDDED ARTEFACT REDUCTION ACTIVITY TRACKING & ENERGY EXPENDITURE
SAMSUNG DIGITAL HEALTH PLATFORM EMPOWERED BY IMEC MULTI-SENSOR PLATFORM
imec generic EEG development platform
FROM PLATFORM TO PRODUCT FOR CLINICAL RESEARCH
BASED ON IMEC TECHNOLOGY
nanoelectronics enable disruptive innovation in healthcare
CELL SORTING CHIP
MILLIONS OF CELLS/MINUTE
SINGLE CELL ANALYSIS
POWERFUL INSTRUMENTATION - LOW COST
DNA ANALYSIS SPECIFIC MARKERS
RESPONSE TO DRUGS ALLERGIES FOOD SENSITIVITY RISK TO DEVELOP CERTAIN DISEASE
TESTS TO GIVE BEST COMBINATION OF DRUGS CHEAP - FAST - POINT OF CARE
TOWARDS PERSONALIZED DRUGS
AUTOMATED TESTING OF THOUSANDS OF CANDIDATE DRUGS ON CULTURED TISSUES
NEED FOR ENERGY EVERYWHERE
SAFETY - FAST CHARGING - LOW VOLUME & WEIGHT - RELIABLE
© TEXAS INSTRUMENTS
ENERGY STORAGE
3D SOLID-STATE BATTERIES: HIGH POWER & HIGH SPEED & ENERGY DENSITY
imec global collaboration platform
75
Lam RESEARCH
76
IMEC CORE CMOS PROGRAM: BUILDING A ‘LAYERED ECOSYSTEM’...
.... OF WORLDWIDE PARTNERSHIPS
IMEC CORE CMOS PROGRAM: BUILDING A ‘LAYERED ECOSYSTEM’...
.... OF WORLDWIDE PARTNERSHIPS
SUPPLIER HUB NEUTRAL PLATFORM FOR EARLY AND STRONG INVOLVEMENT OF EQUIPMENT AND MATERIAL SUPPLIERS IN PROCESS DEVELOPMENT
Patterning SUPPLIERScenter HUB motivation Increasing R&D challenges Increasing R&D cost Consolidating industry
Cost sharing Risk mitigation
Maximum leveraging of full eco-system
Increased supplier involvement & commitment = Patterning Center
Increased supplier involvement & commitment
Increased critical mass on unit process development Most advanced equipment at affordable conditions
Increased critical mass on unit process development Most advanced equipment at affordable conditions
MAXIMISED VALUE CHAIN LEVERAGING
Core partner fees are minimized through maximized leveraging of other key players in value chain: Imec has successfully attracted increased participation of leading edge fabless companies Imec is successfully engaging increased participation and commitment of leading edge equipment and material suppliers 81
300mm
R&D Pilot Line
FAB expansion
Fab3 project
SEPTEMBER 2015
NOVEMBER 2015
MARCH 2015
MAY 2015
SUMMARY
• •
The IoT information universe demands an increase for data / bandwidth / low power. Innovation is needed at device technology, circuit and architecture level to find solutions to serve this wide spectrum of applications.
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LOGIC BEYOND 5nm 2D MATERIALS
