Transcript
Electronics, Inc. 2590 North First Street, San Jose, CA 95131, U.S.A.
Tel: 408-732-5000 Fax: 408-732-5055 http://www.atpinc.com
Rev. Date: Jun. 30, 2015
ATP AW56P64B8BKK0M 2GB DDR3-1600 UNBUFFERED NON-ECC SODIMM DESCRIPTION The ATP AW56P64B8BKK0M is a high performance 2GB DDR3-1600 Unbuffered NON-ECC SODIMM SDRAM memory module. It is organized as 256M x 64 in a 204-pin Small Outline Dual-In-Line Memory Module (SODIMM) package. The module utilizes eight 256Mx8 DDR3 SDRAMs in FBGA package. The module consists of a 256-byte serial EEPROM, which contains the module configuration information.
KEY FEATURES High Density: 2GB (256M x 64) DIMM Rank: 1 Rank Cycle Time: 1.25ns (800MHz) CAS Latency: 11 Power supply: 1.35V (1.28V~1.45V) Backward compatible to 1.5V ±0.075V Internal self calibration through ZQ Burst lengths: 8 Auto & Self refresh Asynchronous Reset
Part No. AW56P64B8BKK0M
Minimum Thickness of Golden Finger: 30 Micro-inch 7.8 s refresh interval at lower than TCASE 85°C, 3.9s refresh interval at 85°C < TCASE < 95 °C Dynamic On Die Termination Fly-by topology PCB Height: 1.18 inches RoHS compliant
Max Freq 800MHz (1.25ns@CL=11) x2
Interface SSTL_15
PIN DESCRIPTION Pin Name
Description
Pin Name
Description
A0~A9, A11~A14 A10/AP BA0~BA2
Address Inputs Address Input/Auto precharge SDRAM Bank Address Column Address Strobe Clock Inputs, positive line Clock Inputs, negative line Clock Enables Data Masks Data Input/Output Data strobes Data strobes, negative line
ODT0 RAS CS0 SA0~SA1 SCL SDA VDD VDDSPD VSS RESET WE
On die termination control Row Address Strobe Chip Selects SPD address Serial Presence Detect (SPD) Clock Input SPD Data Input/Output Core Power SPD Power Ground This signal resets the DDR3 SDRAM Write Enable
TEST
Logic Analyzer specific test pin (No connect on SO-DIMM)
NC
No Connect
CAS CK0~CK1 CK0 ~ CK1 CKE0 DM0~DM7 DQ0~DQ63 DQS0~DQS7 DQS0 ~ DQS7 VREFDQ VREFCA
A12/ BC VTT
Input/Output Reference Address Input/Burst chop Termination voltage
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ATP AW56P64B8BKK0M PIN ASSIGNMENT No.
Designation
No.
Designation
No.
Designation
No.
Designation
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
VREFDQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
VSS DQ4 DQ5 VSS DQS0 DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1
VDD A10/AP BA0 VDD
WE CAS VDD A13 NC VDD TEST VSS DQ32 DQ33 VSS
106 108 110 112 114 116 118 120 122 124 126 128 130 132 134
VDD BA1 RAS VDD CS0 ODT0 VDD NC NC VDD VREFCA VSS DQ36 DQ37 VSS
31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS
32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
RESET VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS
105 107 109 111 113 115 117 119 121 123 125 127 129 131 133
CKE0 VDD NC BA2 VDD A12/ BC
74 76 78 80 82 84
NC VDD 1 A15 1 A14 VDD A11
DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS
136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190
DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS
73 75 77 79 81 83
135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189
85 87 89 91 93 95 97 99 101 103
A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0
86 88 90 92 94 96 98 100 102 104
A7 VDD A6 A4 VDD A2 A0 VDD CK1
191 193 195 197 199 201 203
DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT
192 194 196 198 200 202 204
DQ62 DQ63 VSS NC SDA SCL VTT
DQS5 DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS
CK1
Notes:1. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055
Page 2 of 7
ATP AW56P64B8BKK0M
CS0 CAS RAS WE ODT0 CK0 CK0 CKE0 A[13:0]/BA[2:0]
FUNCTIONAL BLOCK DIAGRAM
DQS DQS DM
U1
CS CAS RAS WE ODT CK CK CKE A[13:0]/BA[2:0]
DQ0~7
DQS4 DQS4 DM4
DQ0~7
ZQ
DQ32~39
DQS DQS DM
U8
CS CAS RAS WE ODT CK CK CKE A[13:0]/BA[2:0]
DQS0 DQS0 DM0
DQ0~7
ZQ
Serial PD SCL
DQ0~7
ZQ
DQS2 DQS2 DM2
DQS DQS DM
DQS3 DQS3 DM3
U3
CS CAS RAS WE ODT CK CK CKE A[13:0]/BA[2:0]
DQ16~23
DQ0~7
ZQ
DQS DQS DM
U4
CS CAS RAS WE ODT CK CK CKE A[13:0]/BA[2:0]
DQ24~31
DQ0~7
ZQ
DQ40~47
DQS6 DQS6 DM6 DQ48~55
DQ0~7
ZQ
DQ56~63
A1
SA0
SA1
DQ0~7
U6
DQS DQS DM DQ0~7
ZQ
A2
U7
DQS DQS DM
ZQ
DQS7 DQS7 DM7
SDA WP A0
DQS DQS DM
CS CAS RAS WE ODT CK CK CKE A[13:0]/BA[2:0]
U2
CS CAS RAS WE ODT CK CK CKE A[13:0]/BA[2:0]
DQ8~15
DQS5 DQS5 DM5
CS CAS RAS WE ODT CK CK CKE A[13:0]/BA[2:0]
DQS DQS DM
U5
CS CAS RAS WE ODT CK CK CKE A[13:0]/BA[2:0]
DQS1 DQS1 DM1
VDDSPD VDD
SDRAMS U1-U8
VREFDQ
SDRAMS U1-U8
VREFCA
SDRAMS U1-U8
VTT
SDRAMS U1-U8
VSS
SDRAMS U1-U8
BA0-BA2
SDRAMS U1-U8
A0-A14 RAS
SDRAMS U1-U8
CAS
SDRAMS U1-U8
WE
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SDRAMS U1-U8 SDRAMS U1-U8
CK0
SDRAMS U1-U8
CK0
SDRAMS U1-U8
CK1
VTT
SDRAMS U1-U8
RESET
CK1
VDD
SPD
ATP AW56P64B8BKK0M ABSOLUTE MAXIMUM DC RATINGS Item Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Operating Temperature
Symbol
Rating
Units
Notes
VDD VDDQ VIN, VOUT TSTG TCASE
-0.4V ~ 1.975V -0.4V ~ 1.975V -0.4V ~ 1.975V -55 to +100 0 to +95
V V V o C o C
1 1 1 1 1,2,3
Note: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. It is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. At 85 - 95 oC operation temperature range, doubling refresh commands in frequency to a 32ms period ( Refresh interval =3.9 µs ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
AC & DC OPERATING CONDITIONS (SSTL- 15) Recommended operating conditions
Item
Symbol
Min.
Typical
Max.
Units
VDD VDDQ I/O I/O VIH (DC) VIH (AC) VIL (DC) VIL (AC)
1.283 1.283 0.49 * VDD 0.49 * VDD VREF + 0.090 VREF + 0.135 VSS -
1.35 1.35 0.50 * VDD 0.50 * VDD -
1.45 1.45 0.51 * VDD 0.51 * VDD VDD VREF - 0.090 VREF - 0.135
V V V V V V V V
Supply Voltage Supply Voltage for Output4 1,2 VREFCA(DC) 1,2 VREFDQ(DC) Input High Voltage (DC) Input High Voltage (AC) Input Low Voltage (DC) Input Low Voltage (AC)
Note: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
RELIABILITY o
o
o
o
MTBF @25 C (Hours) 1
FIT @ 25 C 2
MTBF @40 C (Hours) 1
FIT @ 40 C2
12,137,000
82
6,471,000
154
Note: 1. The Mean Time between Failures (MTBF) is calculated using a prediction methodology, Bellcore Prediction, which based on reliability data of the individual components in the module. It assumes nominal voltage, with all other parameters within specified range. 2. Failures per Billion Device-Hours
Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055
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ATP AW56P64B8BKK0M IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (IDD values are for full operating range of Voltage and Temperature)
Symbol
Proposed Conditions
Value
Units
310
mA
420
mA
96
mA
110
mA
170
mA
250
mA
160
mA
170
mA
260
mA
750
mA
780
mA
880
mA
96
mA
1,250
mA
1,190
mW
Operating one bank active-precharge current; IDD0
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Timing table ; BL: 8; AL: 0;/ CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Operating one bank active-read-precharge current; IDD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Timing table ; BL: 8; AL: 0; /CS: High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Precharge Power-Down Current Slow Exit IDD2P0
CKE: Low; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pre-charge Power Down Mode: Slow Exit
Precharge Power-Down Current Fast Exit IDD2P1
CKE: Low; External clock: On; tCK, CL: see Timing table; BL: 81); AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Pre-charge Power Down Mode: Fast Exit
Precharge standby current; IDD2N
CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Precharge Standby ODT Current IDD2NT
CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
Precharge quiet standby current; IDD2Q
CKE: High; External clock: On; tCK, CL: see Timing table; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Active Power-Down Current IDD3P
CKE: Low; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Active Standby Current IDD3N
CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Operating Burst Read Current IDD4R
CKE: High; External clock: On; tCK, CL: see Timing table; BL: 8; AL: 0; /CS: High between RD; Command, Address, Bank Address Inputs: par-tially toggling ; Data IO: seamless read data burst with different data between one burst and the next one; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Operating Burst Write Current IDD4W
CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: par-tially toggling ; Data IO: seamless write data burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at HIGH;
Burst Refresh Current IDD5B
CKE: High; External clock: On; tCK, CL, nRFC: see Timing table ; BL: 8; AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Self Refresh Current: Normal Temperature Range TCASE: 0 - 85°C; IDD6
Auto Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW ; CL: see Timing table ; BL: 8; AL: 0; /CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self- Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING
Operating Bank Interleave Read Current IDD7
PDIMM
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW , CL: see Timing table ; BL: 8; AL: CL-1; /CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Power Consumption per DIMM System is operating at 800 MHz clock with VDD = 1.35V. This parameter is calculated at a common loading.
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ATP AW56P64B8BKK0M TIMING PARAMETER Parameter
Symbol
Clock cycle time at CL=11, CWL=8 Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACTIVE to PRECHARGE command period Average high pulse width Average low pulse width DQS, DQS to DQ skew, per group, per access DQ output hold time from DQS, DQS DQ low-impedance time from CK, CK DQ high-impedance time from CK, CK Data setup time to DQS, DQS referenced to Vih(ac)Vil(ac) levels Data hold time to DQS, DQS referenced to Vih(ac)Vil(ac) levels DQS, DQS READ Preamble DQS, DQS differential READ Postamble DQS, DQS output high time DQS, DQS output low time DQS, DQS WRITE Preamble DQS, DQS WRITE Postamble
tCK tAA tRCD tRP tRC tRAS tCH(avg) tCL(avg) tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) tDH(base) tRPRE tRPST tQSH tQSL tW PRE tW PST
DQS, DQS rising edge output access time from rising CK， CK
tDQSCK
DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from RL+BL/2) DQS, DQS differential input low pulse width DQS, DQS differential input high pulse width DQS, DQS rising edge to CK, CK rising edge DQS, DQS falling edge setup time to CK, CK rising edge DQS, DQS falling edge hold time to CK, CK rising edge DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay CAS to CAS command delay Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to ACTIVE command period for 1KB page size Four activate window for 1KB page size Command and Address setup time to CK, CK referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK referenced to Vih(ac) / Vil(ac) levels Power-up and RESET calibration time Normal operation Full calibration time Normal operation short calibration time Exit Reset from CKE HIGH to a valid command Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) ODT turn-on RTT_NOM and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew 2Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval Average periodic refresh interval (0°C ≤ TCASE ≤ 85 °C) Average periodic refresh interval (85°C ≤ TCASE ≤ 95 °C) Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Power Down Entry to Exit Timing Write leveling output delay Write leveling output error
tLZ(DQS) tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH tDLLK tRTP tW TR tW R tMRD tMOD tCCD tDAL tMPRR tRRD tFAW tIS(base) tIH(base) tZQinitI tZQoper tZQCS tXPR
1:Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
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tXP tAONPD tAOFPD tAON tAOF tADC tRFC tREFI tREFI tXS tXSDLL tPD tW LO tW LOE
DDR3-1600 min 1.25 2 13.75(13.125 ) 2 13.75(13.125 ) 2 13.75(13.125 ) 2 48.75(48.125 ) 35 0.47 0.47 0.38 -450 10 45 0.9 0.3 0.4 0.4 0.9 0.3 -225
Max <1.5 20
9*tREFI 0.53 0.53 100 225 225
225
-450 225 225 0.45 0.55 0.45 0.55 -0.27 0.27 0.18 0.18 512 max(4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max(12nCK,15ns) 4 tWR + roundup (tRP / tCK) 1 max(4nCK,6ns) 30 45 120 512 256 64 max(5nCK, tRFC+ 10ns)
Units ns ns ns ns ns ns tCK tCK ps tCK ps ps ps ps tCK tCK tCK tCK tCK tCK ps ps ps tCK tCK tCK tCK tCK 1 nCK
ns 1 nCK 1
nCK 1 nCK 1 nCK ns ps ps 1 nCK 1 nCK 1 nCK
max(3nCK,6ns) 2 2 -225 0.3 0.3 160 7.8 3.9 max(5nCK,tRFC+10ns) tDLLK(min) tCK(min) 0 0
8.5 8.5 225 0.7 0.7 7.8 3.9
ns ns ps tCK tCK ns us us
60ms 7.5 2
nCK1 tCK ns ns
ATP AW56P64B8BKK0M PHYSICAL DIMENSIONS (UNITS IN INCHES) (Drawing not to scale)
204-pin DIMM Front
Back
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