Ccd / Cmos Hybrid Fpa For Low Light Level Imaging

Transcript

CCD / CMOS Hybrid FPA for Low Light Level Imaging Xinqiao (Chiao) Liu*, Boyd A. Fowler, Steve K. Onishi, Paul Vu, David D. Wen, Hung Do, and Stuart Horna Fairchild Imaging, Inc., 1801 McCarthy Boulevard, Milpitas, CA 95035 a U.S. Army Night Vision and Electronic Sensors Directorate, 10221 Burbeck Rd., Fort Belvoir, VA 22060-5806 Abstract We present a CCD / CMOS hybrid focal plane array (FPA) for low light level imaging applications. The hybrid approach combines the best of CCD imaging characteristics (e.g. high quantum efficiency, low dark current, excellent uniformity, and low pixel cross talk) with the high speed, low power and ultra-low read noise of CMOS readout technology. The FPA is comprised of two CMOS readout integrated circuits (ROIC) that are bump bonded to a CCD imaging substrate. Each ROIC is an array of Capacitive Transimpedence Amplifiers (CTIA) that connect to the CCD columns via indium bumps. The proposed column parallel readout architecture eliminates the slow speed, high noise, and high power limitations of a conventional CCD. This results in a compact, low power, ultra-sensitive solid-state FPA that can be used in low light level applications such as live-cell microscopy and security cameras at room temperature operation. The prototype FPA has a 1280 x 1024 format with 12-um square pixels. Measured dark current is less than 5.8 pA/cm2 at room temperature and the overall read noise is as low as 2.9e at 30 frames/sec. Keywords: CCD, CMOS, hybrid, CCD/CMOS hybrid, FPA, low light level, ROIC, read noise I. INTRODUCTION Many scientific, medical and defense imaging applications demand low-light solid-state focal plane sensors that have photon counting sensitivity, megapixel or higher resolution, and hundreds or even thousands of frames per second speed. Some examples include wavefront sensing for Adaptive Optics (AO), real time x-ray imaging for next generation synchrotron sources, security surveillance, and live-cell fluorescence microscopy. Current state-of-the-art CCDs are capable of delivering near ideal imaging performance with quantum efficiency (QE) approaching 100%, low dark current (3-20 pA/cm2 at room temperature), high linearity and uniformity [1]. However, the serial readout nature of a conventional CCD limits its readout speed. In addition, the finite number of on-chip output amplifiers need to be operated at high speed, and therefore, the CCD read noise could not be easily reduced [2]. This level of read noise seriously compromises the CCD sensitivity at low light level. Initial efforts to address the noise issue centered upon achieving sufficient electron gain before noise is added down the signal path. Intensified CCDs (ICCD) achieve high signal gain by optically coupling an image intensifier (I2) tube to a conventional CCD. Electron bombarded CCD / CMOS (EBCCD / EBCMOS) sensors eliminate the intensifier phosphor screen and capture the accelerated electrons using the silicon sensor directly. Neither approach is pure solid-state, and all suffer from the inherited limitations of I2 technology that include high excess noise factor, limited lifetime, halo and potential damage from over-exposure, etc. Alternately, monolithic CCDs utilizing impact ionization to achieve electron multiplication (e.g. Impactron CCD from TI [3] and EMCCD from e2v [4]) show great promise. The impact ionization technique provides a large electric field in a special gain shift register to create charge multiplication wherein a single signal electron can create hundreds of • Email: [email protected] , Phone: 408-433-2605, Fax: 408-433-2604, Web: http://www.fairchildimaging.com. This work was supported in part by US Army SBIR No. W15P7T-05-C-E004 and No. W15P7T-05-C-P424. additional signal electrons before they are read out by the output amplifier. In order to provide the multiplication, the camera must provide well-regulated, large clock voltage swings. This requires large amounts of power. EMCCDs are sensitive to clocking induced charge (CIC). At high gain levels, even a small amount of spurious charge can be seen as sharp spikes in the image. In addition, the dark current is amplified along with the signal, effectively lowering the dynamic range of the device. The sensor must be cooled to eliminate any dark signal [4]. The performance of CMOS image sensors has drastically improved over the past decade (see, e.g. [5][6]). Monolithic CMOS image sensors with camera-on-a-chip integration have the potential of providing the ideal size, weight and power solution for man portable imaging applications. CMOS sensor technology advancements are backed by a vertically integrated industry driven by a much larger consumer market. However, state-of-the-art CMOS image sensors cannot meet the requirements for most low light imaging applications [7]. In this paper, we present a CCD / CMOS hybrid focal plane array for low light level imaging applications. The hybrid approach combines the best of CCD imaging characteristics (e.g. high quantum efficiency, low dark current, excellent uniformity, and low cross talk) with the high speed, low power and ultra-low read noise of CMOS readout technology. The FPA is comprised of two CMOS readout integrated circuits (ROIC) that are bump bonded to a CCD imaging substrate. Each ROIC is an array of Capacitive Transimpedence Amplifiers (CTIA) [8] that connect to the CCD columns via indium bumps. By eliminating the conventional serial shift register and output amplifiers, the hybrid CCD is read out noiselessly by shifting charge directly onto the ROIC while maintaining excellent imaging performance. The column parallel readout architecture reduces the effective output bandwidth and provides sufficient silicon real estate on the ROIC to implement sophisticated amplifier circuits that dramatically reduce read noise. The CCD power consumption is also reduced due to the elimination of high-speed serial clocking and high current output amplifiers. The advantages of the hybrid approach were also discussed in [7] [9]. The rest of the paper is organized as follows: In Section II, we present our hybrid CCD / CMOS architecture, and show how our new architecture solves the limitations of conventional CCDs. In Section III, theoretical analysis of the proposed FPA performance at low light level will be presented. Finally in Section IV, we present some measurement results of a prototype hybrid CCD / CMOS FPA and low light level camera system. II. DESCRIPTION OF HYBRID CCD / CMOS ARCHITECTURE Current state-of-the-art CCDs are capable of delivering near ideal imaging performance with quantum efficiency (QE) approaching 100%, low dark current (3-20 pA/cm2 at room temperature), high linearity and uniformity [1]. Fundamentally, charge transfer in the CCD is a noiseless process, and read noise is only added at the final output amplifier. The additive noise power is proportional to the amplifier bandwidth, and read noise as low as 1 e- RMS has been repeatedly achieved when the amplifier is band-limited to around 10 kHz. For high definition video applications, however, the finite number of on-chip output amplifiers must be operated at high speed (around 30MHz) to support the video rate; and the read noise is increased to 20 to 30 electrons [2]. This high level of noise seriously compromises the CCD sensitivity at low light level. In addition, the serial readout nature of a conventional CCD limits its maximum frame rate, and the high-speed serial shift registers and the output amplifiers contribute to high power consumption. Figure 1 shows a conventional CCD architecture with 4 output amplifiers. If, on the other hand, the charge signal is shifted off the CCD without being converted into a voltage signal (and hence no output amplifier), then the whole CCD readout becomes noiseless (assuming the CCD transfer noise in a buried channel device is negligible [10]). Further, if charge is shifted off the CCD at the end of each column, then the serial shift register can be eliminated and the speed bottleneck is removed. For a megapixel sensor, the proposed column parallel readout architecture results in 3 orders of magnitude bandwidth reduction, promising substantial noise and power reduction. OUTPUT Serial Shift Register OUTPUT CCD active area OUTPUT Serial Shift Register OUTPUT Figure 1. Conventional CCD architecture Digital Output CMOS ROIC Shielded Storage 1280 Columns 1024 Rows Charge Coupled Device Shielded Storage Indium Bump CMOS ROIC Digital Output Figure 2. Proposed CCD/CMOS hybrid architecture Figure 2 shows the hybrid architecture. The FPA is comprised of two CMOS ROICs that are bump bonded to a CCD imaging substrate. Each ROIC is an array of Capacitive Transimpedence Amplifiers (CTIA) that connect to the CCD columns via indium bumps. The CCD sensor does not have any on chip amplifiers; instead the charge signal from each column is transferred across the indium bump bonds and onto the CMOS ROIC. Once transferred there, it is converted to a voltage and amplified by the CTIA. The CMOS chip contains additional circuitry to perform correlated double sampling (CDS) and multiplexing operations. On-chip analog to digital conversion (ADC), timing generation, digital control and signal processing can also be integrated on the ROIC. This results in a compact camera-on-a-chip solution. As mentioned above, the CCD in this architecture is free of read noise while maintaining superior imaging performance. Different types of CCDs can be utilized in the FPA including front illuminated frame transfer (FT), front illuminated interline transfer (IT), back-thinned back illuminated, as well as fully depleted [11]. The CTIA in the CMOS ROIC only needs to be operated at a line rate that is several orders of magnitude slower than conventional CCD output amplifiers, which results in much lower read noise. In addition, the column parallel layout of the CTIA provides essentially unlimited silicon real estate in the column direction. This allows more sophisticated amplifier design and hence better performance than CTIAs arranged in a 2D-array architecture. In summary, the CCD / CMOS hybrid architecture allows us to select only the best features from what had heretofore been competing technologies. As a result, the imaging performance and noise performance can be optimized separately. III. THEORETICAL NOISE ANALYSIS Since there are no on-chip amplifiers on the CCD, the dominant noise source in the proposed hybrid FPA is the CTIA. Figure 3 shows the CTIA noise model used in the analysis. In this model, Cin is the input capacitance that includes CTIA input transistor gate capacitance, CCD output node parasitic capacitance, and any parasitic capacitance associated with the indium bump; Cfb is the CTIA feedback capacitor; Cload is the CTIA band limiting capacitor. The total output noise power is given by: ∞ 2 2 2 Vout = ∫ df ( Vn ( f ) ⋅ H cds ⋅ H loop ) 2 (1) 0 where Vn(f) is the lumped noise power spectral density for all the transistors in the amplifier, Hcds is the CDS transfer function, and Hloop is the CTIA close loop transfer function. The distributions of above components are depicted in Figure 4. Vn(f) is dominated by 1/f noise at low frequency and by thermal noise at high frequency; Hloop works as a lowpass filter that rejects the high frequency noise while Hcds works as a high-pass filter that eliminates most of the 1/f noise. Cfb Vn ~ C in A Vout Figure 3. CTIA noise model C load (a) Noise power spectral density (b) Amplifier transfer function (c) CDS transfer function Figure 4. CTIA noise power and transfer functions Assuming that most of the 1/f noise is eliminated by the CDS operation, a closed form solution can be derived by modeling Vn(f) as thermal noise only and neglecting Hcds. The input referred noise, (N) in e- RMS is approximated N≈ 2kTC fb q 2 (C in + C fb ) 2 C load (C fb + C in ) + C fb C in . (2) Note that the input referred noise increases with the feedback capacitor Cfb, i.e., the higher conversion gain (q/Cfb), the lower noise. The noise decreases with the band limiting capacitor Cload, which is determined by the CTIA speed requirement. Also note that the noise increases with the input capacitance Cin, hence it is critical to keep the parasitic capacitance at the CCD output node and indium bump as small as possible. For a 1K x 1K FPA running at 30 frames/sec, the CTIA closed loop bandwidth can be set at around 20 kHz. Assuming the input capacitance Cin of 56 fF, the feedback capacitance Cfb of 1 fF, and the band limiting capacitance Cload of 2.6 pF, the input referred noise is estimated to be 2.7 e- RMS with an equivalent overall pixel rate of 30MHz. Further reduction of input capacitance to 28 fF will result in a read noise of less than 2 e-. Finally, we estimate the signal to noise ratio (SNR) of the proposed hybrid FPA, and compare that to the performance of an EMCCD. Here we assume that both CCDs have the identical imaging performance, i.e., QE, dark current, CTE etc.; therefore, they will generate the same number of photoelectrons under the same light level. We assume 2 electrons of dark charge for both CCDs, and zero read noise for EMCCD due to its high front end gain. EMCCD has an excess noise factor of 1.4 due to the statistical nature of the avalanching multiplication [12]. For the EMCCD, the SNR is calculated as: SNR = N sig 1.4 N sig + N dark _ sig . (3) . (4) For the hybrid FPA, the SNR is calculated as: SNR = N sig 2 N sig + N dark _ sig + N read Figure 5 plots the calculated SNR for the EMCCD and the hybrid FPA with read noise of 1.4 e-, 3e-, and 5erespectively. It can be seen that the SNR of the proposed hybrid FPA surpasses that of the EMCCD at different signal level depending on its read noise, and the hybrid FPA always has higher SNR at high light level. Note that significant cooling is required for the EMCCD, which results in high system power consumption. SNR 10.0 1.0 EMCCD Hybrid 1.4e Hybrid 3e Hybrid 5e 0.1 1 10 100 Photoelectrons (e) Figure 5. SNR vs. photoelectrons for EMCCD and the proposed hybrid FPA IV. EXPERIMENTAL RESULTS We have designed and fabricated a split frame transfer (SFT) CCD that is customized for this hybrid sensor architecture. Unlike conventional CCDs, no output amplifiers and high speed serial shift registers are implemented on the CCD, and the charge signal is directly transferred to the CMOS ROIC via indium bumps at end of CCD columns. The CCD has a 1280 x 1024 format with 12-um square pixels. The CMOS ROIC was designed and fabricated using a standard 1P4M 0.35um digital CMOS process. It consists of an array of CTIAs, analog bias, digital timing generation, and analog multiplexing circuits. The ROIC has two analog output ports that can be operated at up to 40Mpixels/sec to readout the CCD. The CCD and ROICs are hybridized via indium bump bonds and the FPA is packaged in a custom header. The low light camera consists of a sensor board, a driver/digitization board, and a digital board with a FPGA for camera control and micro controller for Cameralink operation. Figure 6 shows the prototype CCD/CMOS hybrid FPA and the prototype camera. No cooling mechanism was used in the camera. Dark current of 5.8 pA/cm2 at room temperature was measured when the CCD was operated in MPP mode. Average read noise of the whole camera system is less than 5 e- RMS at 30 frame/sec, while noise as low as 2.9 e- RMS has been measured. Figure 7 shows a poster image captured at 30 frames/sec under room light, and Figure 8 shows a sample image captured at 30 frames/sec where the brightest region has less than 200 photoelectrons. For high speed applications, the camera can be operated up to 200 frames/sec. The design is currently being updated to a frame interline transfer (FIT) CCD together with a new CMOS amplifier design to improve the conversion gain. The newer hybrid FPA is expected to have higher QE, significantly reduced smear, and less than 2 e- read noise. CMOS ROIC CCD imaging section CCD storage section Figure 6. Prototype CCD/CMOS hybrid FPA and low light level camera Figure 7. Poster images captured at 30 frames/sec under room light Figure 8. Sample image captured at 30 frames/sec, the brightest region has less than 200 photoelectrons V. SUMMARY We have presented a CCD / CMOS hybrid FPA for low light level imaging applications. The proposed CCD / CMOS hybrid approach allows us to select the best features from what had heretofore been competing technologies, enables the imaging performance and noise performance to be optimized separately. Further, the proposed column parallel readout architecture eliminates the slow speed, high noise, high power limitations of a conventional CCD, results in a compact, low power, ultra-sensitive all solid-state FPA that can be used in low light level applications at room temperature operation. ACKNOWLEDGMENTS We acknowledge the technical support of our colleagues at Fairchild Imaging and NVESD. The authors especially thank Dan Laxson, David Reaves, and Kumar Joshi for their contributions. REFERENCES 1. 2. 3. Janesick, Scientific Charge-Coupled Devices, SPIE Press, Bellingham, Washington, 2001 Kozlowski, et al, “Performance limits in visible and infrared imager sensors”, IEEE IEDM Digest, 1999 Hynecek , “Impactron-a new solid state image intensifier”, IEEE Trans. on Electron Devices, Vol. 48, Issue 10, Oct. 2001 Page(s):2238 - 2241 4. Spencer, et al, “Low Light Level Solid State TV Imaging”, http://www.e2v.com/technologies/l3vision.htm 5. El Gamal, “Trends in CMOS image sensor technology and design," IEEE IEDM Digest, 2002 6. El Gamal, et al, “CMOS image sensors”, IEEE Circuits and Devices Magazine, Vol 21, Issue 3, May-June 2005 7. Janesick, “Charge coupled CMOS and hybrid detector arrays”, Proc. SPIE Vol. 5167, 2003 8. Fowler, et al, "Low Noise Readout using Active Reset for CMOS APS," Proc. SPIE Vol. 3965, p. 126-135, 2000 9. Atlas, et al, “Hybrid imaging: a quantum leap in scientific imaging”, Proc. SPIE Vol. 5167, p. 121-126, 2004 10. Mohsen, et al, “Noise measurements in Charge-Coupled Devices,” IEEE Trans. on Electron Devices, Vol. ED-22 No. 10, May 1975 Page(s):209-218 11. Holland, et al, "Fully Depleted, Back-Illuminated Charge-Coupled Devices Fabricated on High-Resisitivity Silicon," IEEE Trans. on Electron Devices, Vol. 50, Issue 3, 225—238, January 2003 12. Van Vliet, et al, “Theory of Carrier Multiplication and Noise in Avalanche Devices”, IEEE Trans. on Electron Devices, Vol. 26, May, 1979