Transcript
Circuit Note
CN-0143
Devices Connected/Referenced Circuits from the Lab® reference designs are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0143.
AD8042
Dual, 160 MHz Rail-to-Rail Op Amp
AD5620
Single, 12-Bit Buffered Voltage Output DAC
AD5443
High Bandwidth 12-Bit CMOS Current Output DAC
ADR444
Precision 4.096 V Low Noise Reference
Single-Ended-to-Differential Converters for Voltage Output and Current Output DACs Using the AD8042 Op Amp CIRCUIT FUNCTION AND BENEFITS
With differential signaling, two signal wires run from the signal source to the data acquisition interface. This can solve both of the problems caused by single-ended connections. Noise between the sending and receiving ground planes acts as a common-mode signal and is, therefore, greatly attenuated. The use of twisted pair wire causes noise pickup to appear as a common-mode signal, which is also greatly attenuated at the receiver. Another advantage of differential transmission is that the differential signal has twice the amplitude of the equivalent single-ended signal, therefore giving greater noise immunity.
With single-ended signaling, one wire from the signal source is routed throughout the system to the data acquisition interface. The voltage measured is the difference between the signal and the ground. Unfortunately, “ground” can be a different level in different places because the ground impedance can never be zero. This can lead to errors when using single-ended inputs, especially where the signal trace is long and grounds currents contain large digital transients. Single-ended signal runs are sensitive to noise pickup because they act as an antenna, picking up electrical activity. With single-ended inputs there is no way of distinguishing between the signal and the interfering noise. Most of the ground and noise problems are solved by differential signaling. 5V U1 8
DIN
7
VDD
GND
DIN
VREFOUT
1
2
5V
5V
2.5V
2.5V
R2
0V VIN
U2-A
5V
R1
3
8
10kΩ
2
AD5620 SCLK
SYNC_BF
6 5
SCLK
SYNC
VFB VOUT
0V
10kΩ
3
V+
1
4
AD8042 2.5V
R3 2.21kΩ R5 2.21kΩ
R6 2.21kΩ 5V 2.5V R4
0V
2.21kΩ 6
V–
AD8042
4 C5
U2-B
0.1µF
08806-001
7 5
Figure 1. Differential Driver for the AD5620 Voltage Output DAC
Rev. A Circuits from the Lab® reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due toanycausewhatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage)
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CN-0143
Circuit Note voltage of +2.5 V. The feedback network and U2-B force the voltage at V+ to be 180° out of phase with respect to V−. Waveforms for the input and output of the driver are shown in Figure 2. The differential outputs will only go to within about 30 mV of each rail; therefore, there will be some clipping if the DAC is operated in these regions.
Here we describe a differential driver that can be adapted to either a voltage or current output DAC. The driver is based on the dual AD8042 op amp configured as a cross-coupled differential driver. The AD8042 has a rail-to-rail output stage that operates within 30 mV of either rail and an input stage that can operate 200 mV below the negative supply (ground in this circuit) and within 1 V of the positive supply. In addition, the AD8042 has 160 MHz bandwidth and fast settling time, making it an ideal choice for the output driver.
VIN
The voltage output DAC is the 12-bit AD5620, a member of the nanoDAC® family. The DAC contains an on-chip 5 ppm/°C reference and is available in an 8-lead SOT-23 or MSOP package. The current output DAC is the 12-bit AD5443, which is available in a 10-lead MSOP package.
1
V+
2
The two circuits represent a cost effective, low power, and small board area solution for generating differential signals from industrial CMOS DACs. Both circuits operate on a single +5 V supply.
V–
CH1 2V CH3 2V
CIRCUIT DESCRIPTION
CH2 2V
M50.0µs
CH1
08806-002
3
2.61V
Figure 2. VIN, V+, and V− for Figure 1 Circuit at 100 kSPS Update Rate
The circuit shown in Figure 1 operates on a single +5 V supply and utilizes the AD5620 voltage output DAC. The input to the DAC is controlled by an SPI port. The output of the DAC swings between 0 V and +5 V. The on-chip DAC reference (+2.5 V) is used to set the common-mode voltage of the AD8042 differential driver circuit. This reference has a temperature coefficient of 5 ppm/°C. The output at V− is the inverted DAC output centered around a common-mode
The circuit shown in Figure 3 also operates on a single +5 V supply and utilizes the AD5443 current output DAC in a mode where the IOUT2 pin is connected to +2.5 V, and the VREF pin is grounded. The ADR444 precision 4.096 V reference and a divider network are used to generate the +2.5 V for the IOUT2 pin of the DAC and the +3.75 V common-mode voltage for the output driver stage.
5V
5V
3.75V 2.5V
SCLK
4
SCLK
AD5443 DIN
SYNC_BF
VDD
5
SDIN
6
RFB
SDO
SDO
1.5pF C1
10
5V
3
R2 10kΩ
VIN 1
R1
3
10kΩ
2
U2-A
TP
U4
5V
0.1µF C3
R3 2.21kΩ 2.21kΩ R6
3 NC
ADR444
6 VOUT 5
GND
TRIM
2.5V
2.5V R4
NC
4
3.75V
V–
8 7
VIN
1
U3-A
TP
2
V+
AD8042
2.21kΩ R5 1
8
AD8042
3 9
VREF
2.5V
5V
8
2
2
IOUT2 GND
7
3.75V
1
IOUT1
SYNC
5V
C2 0.1µF
8
C4 0.1µF
R7 3.32kΩ R8 12kΩ R9 24kΩ
2.21kΩ
3.75V 6
AD8042 6
U2-B
7
4
5 C5
0.1µF
R10 2.21kΩ
Figure 3. Differential Driver for the AD5443 Current Output DAC
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U3-B
5
7 4
AD8042
08806-003
U1
Circuit Note
CN-0143
Under these conditions the output of U2-A swings between +2.5 V and +5 V. The differential outputs of the driver will only go to within about 30 mV of the positive rail; therefore, there will be some clipping if the DAC is operated in this region. Figure 4 shows the corresponding input and output waveforms for the output driver stage of Figure 3.
LEARN MORE Kester, Walt. The Data Conversion Handbook. Chapter 3, 7. Analog Devices. 2005. MT-015 Tutorial, Basic DAC Architectures II: Binary DACs. Analog Devices. MT-031 Tutorial, Grounding Data Converters and Solving the Mystery of AGND and DGND. Analog Devices.
VIN
MT-101 Tutorial, Decoupling Techniques. Analog Devices. Voltage Reference Wizard Design Tool, Analog Devices.
1
V+
Data Sheets and Evaluation Boards 2
AD5443 Data Sheet
V–
AD5443 Evaluation Board AD5620 Data Sheet 3
CH2 2V
M50.0µs
CH1
3.81V
AD5620 Evaluation Board
08806-004
CH1 2V CH3 2V
AD8042 Data Sheet ADR444 Data Sheet
Figure 4. VIN, V+, and V− for Figure 3 Circuit at 100 kSPS Update Rate
The single-ended-to-differential converter stage has a bandwidth of typically 10 MHz. However, the maximum output frequency is controlled by a DAC update rate, which is 125 kSPS for the AD5620 and 2.5 MSPS for the AD5443. Sampling theory limits the maximum output frequency to about onethird the maximum update rate. Excellent layout, grounding, and decoupling techniques must be utilized to achieve the desired performance from the circuits discussed (see Tutorial MT-031 and Tutorial MT-101).
REVISION HISTORY 2/14—Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Figure 2 .......................................................................... 2 3/10—Revision 0: Initial Version
COMMON VARIATIONS The AD5640 and AD5660 are 14-bit and 16-bit versions of the AD5620. The AD5446 is a 14-bit version of the AD5443.
(Continued from first page) Circuits from the Lab reference designs are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may use the Circuits from the Lab reference designs in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the Circuits from the Lab reference designs. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab reference designs are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any Circuits from the Lab reference designs at any time without notice but is under no obligation to do so. ©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CN08806-0-2/14(A)
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