Copyright By Joel Thomas Williams 2010

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Copyright by Joel Thomas Williams 2010 The Report Committee for Joel Thomas Williams Certifies that this is the approved version of the following report: Prototyping of MP3 Decoding and Playback on an ARM-based FPGA Development Board APPROVED BY SUPERVISING COMMITTEE: Supervisor: Andreas Gerstlauer Mark McDermott Prototyping of MP3 Decoding and Playback on an ARM-based FPGA Development Board by Joel Thomas Williams, B.S. Report Presented to the Faculty of the Graduate School of The University of Texas at Austin in Partial Fulfillment of the Requirements for the Degree of Master of Science in Engineering The University of Texas at Austin May 2010 Abstract Prototyping of MP3 Decoding and Playback on an ARM-based FPGA Development Board Joel Thomas Williams, M.S.E. The University of Texas at Austin, 2010 Supervisor: Andreas Gerstlauer MP3, or MPEG-1 Layer 3, is the most widely-used format for storing compressed audio. MP3 is more advantageous than uncompressed audio (PCM), offering a much smaller size but without a noticeable loss in audio quality. This report will demonstrate decoding and playback of MP3 audio using a TLL5000 FPGA board. iv Table of Contents List of Tables ................................................................................................ vi List of Figures.............................................................................................. vii 1. INTRODUCTION 1 1.1. MP3 Decoder .........................................................................................2 1.2. PCM Buffer ...........................................................................................2 1.3. Digital-to-Analog Converter..................................................................2 2. SOFTWARE IMPLEMENTATION 3 3. HARDWARE/SOFTWARE INTERFACE 5 4. AUDIO CODEC ’97 (AC97) CONTROLLER IMPLEMENTATION 7 4.1. AC97 Input Frame Description .............................................................9 4.2. AC97 Output Frame Description.........................................................13 4.3. Setting up the AC97 ............................................................................17 4.3.1. Reset Register (0x00) ........................................................17 4.3.2. Master Volume Register (0x02) ........................................17 4.3.3. Extended Audio Status and Control Register (0x2A) .......18 4.3.4. PCM Front DAC Rate Register (0x2C) ............................19 4.4. RTL Implementation of AC97 Controller ...........................................20 5. 4.4.1. Receiving Data from the Codec ........................................21 4.4.2. Sending Data to the Codec ................................................23 TESTING AND RESULTS 5.1. Testing 27 ...........................................................................................27 5.2. FPGA Synthesis Results ......................................................................28 REFERENCES 31 VITA 32 v List of Tables Table 2.1 MP3 File Structure...................................................................................3 Table 3.1 FIFO Signal Description..........................................................................5 Table 4.1 AC97 Signal Detail..................................................................................8 Table 4.2 AC97 Input Frame Slot Detail ...............................................................10 Table 4.3 AC97 Input Slot 0 Detail .......................................................................11 Table 4.4 AC97 Input Slot 1 Detail .......................................................................12 Table 4.5 AC97 Input Slot 2 Detail .......................................................................12 Table 4.6 AC97 Output Frame Slot Detail ............................................................14 Table 4.7 AC97 Output Slot 0 Detail.....................................................................15 Table 4.8 AC97 Output Slot 1 Detail.....................................................................16 Table 4.9 Master Volume Register Detail .............................................................17 Table 4.10 Extended Audio Status and Control Register Detail ...........................18 Table 4.11 PCM Front DAC Rate Register Detail ................................................19 Table 4.12 FPGA to AC97 Interface .....................................................................20 Table 4.13 AC97 Frame Summary ........................................................................21 Table 5.1 Device Utilization Summary .................................................................28 Table 5.2 Component Summary ............................................................................29 Table 5.3 Clock Summary .....................................................................................30 vi List of Figures Figure 1.1 System Overview....................................................................................1 Figure 2.1 Software Architecture.............................................................................4 Figure 3.1 SW/HW Timing Diagram.......................................................................6 Figure 4.1 AC97 Block Diagram .............................................................................7 Figure 4.2 AC97 Input Frame..................................................................................9 Figure 4.3 AC97 Output Frame .............................................................................13 Figure 4.4 AC97 Controller Input State Machine..................................................23 Figure 4.5 AC97 Controller Output State Machine ...............................................26 vii 1. INTRODUCTION This project encompasses an MP3 decoding and playback system. A TLL5000 Electronic System Design demonstration board is the foundation of the MP3 playback hardware. This board is similar to a PC’s motherboard, with numerous audio, video, and I/O ports, but includes a Xilinx Spartan-3 FPGA rather than a CPU. [4] The board I/O, including the audio signals used for audio playback, is accessed via the FPGA. Audio playback capability on the TLL5000 is provided by an Analog Devices AC ’97 Codec chip. [6] This report will document the procedure for configuring the TLL5000 board to function as an MP3 player. This playback system will have three components: an MP3 decoder, an audio buffer, and a digital-to-analog converter. These are explained in greater detail below. ARM Processor FPGA Audio Codec FS i.MX21 ─ MP3 Decoder Xilinx Spartan-3 ─ PCM Buffer AC97 Controller AD1981BL ─ D-A Conv. TLL 6219 TLL 5000 Figure 1.1 System Overview 1 audio out 1.1. MP3 Decoder MP3 decoding is performed by the i-MX21 processor on the TLL 6219 daughter card. This card provides a Linux shell for program execution. 1.2. PCM Buffer The inputs to the audio codec chip on the TLL5000 are only accessible via the Spartan-3 FPGA. The FPGA acts as a buffer, receiving the decompressed audio data (PCM format) from the TLL 6219 and then sending the data to the audio codec along with the correct timing signals the codec requires. In so doing, the FPGA is configured to act as the audio codec controller. 1.3. Digital-to-Analog Converter The TLL5000 board includes an Analog Devices AD1981BL AC ’97 Codec chip. AC ’97 is a standard developed by Intel which encompasses both audio playback and recording. [6] Included in the AD1981BL chip is an analog-to-digital converter for audio recording and a digital-to-analog converter for audio playback. For this application, only the audio playback capability is used. 2 2. SOFTWARE IMPLEMENTATION MPEG-1 Layer 3 (MP3) compression is not lossless. Some information will be lost in the compression process, but the algorithm attempts to limit such losses to frequencies normally outside the range of human hearing. This allows for a very faithful reproduction of the original audio when the MP3 is decoded. An MP3 file consists of multiple frames of audio data with tag information at the beginning and end of the file. The older tag format (ID3v1) is located at the end of the file. The newer tag format (ID3v2) is located at the beginning of the file. ID3v2 is more commonly used, but ID3v1 is maintained for backwards compatibility. Contained in the tag is information about the audio data such as artist, album, and song title. Tag (ID3v2) Frame 1 Frame 2 … Frame N Tag (ID3v1) Table 2.1 MP3 File Structure Each frame of audio data is preceded with a header containing information about the frame. Each frame represents approximately 26 ms of audio. Using a bit rate of 128kbps, the frame size will typically contain 417 bytes. The software architecture of the MP3 decoder is shown in Figure 2.1 [2]. A constant stream of MP3 data is fed to the decoder, which produces pulse-code modulated 3 (PCM) samples at its output. After synchronization and error checking, Huffman coding, requantization, and reordering are performed. The resulting frequency coefficients are fed into an inverse modified discrete cosine transform (IMDCT) for each stereo channel. Finally, the polyphase filter transforms the data into PCM samples. Figure 2.1 Software Architecture The implementation of the MP3 decoder software used in this application is taken from [3]. For this project, the automatically synthesized C code obtained from [3] was adopted in largely unmodified form. The I/O routines and interrupt handlers for interface with the hardware were replaced with an implementation using a Linux kernel module driver. 4 3. HARDWARE/SOFTWARE INTERFACE The data rate for transferring PCM samples from the ARM board to the FPGA is much faster than the rate for transferring data from the FPGA to the AC97 codec. To account for this, the FPGA is configured to act as a buffer, storing the incoming data and sending it to the codec. Two buffers will be used, one each for the left and right audio channels. A first-in-first-out (FIFO) queue will serve as the buffer architecture. Since read and write accesses to the FIFOs occur in different clock domains, the FIFOs are setup to use separate read and write clocks. Valid for Write Clock Valid for Read Clock Data In (20-bit bus) Data Out (20-bit bus) Write Enable Read Enable Full Empty Almost Full Almost Empty Table 3.1 FIFO Signal Description A single frame of PCM data contains 1152 32-bit samples (16-bits each for left and right channels). The FIFO depth is chosen to allow 2 complete frames (2 x 1152 = 2304 samples) to be stored. The Xilinx CORE Generator used to automatically generate the Verilog code for the FIFO only allows FIFO depths in powers of 2. However, the capability exists to create a FIFO with a programmable full threshold. [8] In this case a FIFO with size 4096 is generated and the full threshold is set to 2304. The PCM Buffer is setup to automatically store incoming PCM samples into the FIFOs. The buffer does not perform any handshaking with the ARM. 5 Synchronization with the ARM is performed by the AC97 Controller (see Section 4). The controller will signal the ARM to send PCM data via a hardware interrupt. Figure 3.1 shows the timing diagram of the software and hardware interface. The software (ARM) will begin decoding MP3 data immediately but will wait to send the decoded PCM samples to the FGPA until signaled via an interrupt from the FPGA. Upon receiving the interrupt the ARM will transmit a frame of PCM data to the FPGA and the FPGA will immediately begin sending those samples to the audio codec. While those samples are being sent to the codec, the ARM will resume decoding the next MP3 frames. This process will repeat until there are no more MP3 frames to decode. Figure 3.1 SW/HW Timing Diagram 6 4. AUDIO CODEC ’97 (AC97) CONTROLLER IMPLEMENTATION AC97 is an audio playback and recording standard created by Intel. [7] Figure 4.1 AC97 Block Diagram 7 Table 4.1 lists the AC97 signals used in this application. Signal Direction† Description SDATA_IN Out Serial Data to AC97 Controller (Recorded Data) BIT_CLK Out 12.288 MHz Clock to Controller SDATA_OUT In Serial Data from AC97 Controller (Playback Data) SYNC In Frame Sync RESET In Master Reset ID0 In Chip Select 0 ID1 In Chip Select 1 XTL_IN In 24.576 MHz from external oscillator LINE_OUT_L Out Analog Output (Left Channel) LINE_OUT_R Out Analog Output (Right Channel) †Relative to AC97 Codec Table 4.1 AC97 Signal Detail The Xilinx Spartan-3 FPGA is configured to act as the AC97 controller. Data is sent serially from the controller to the codec (SDATA_OUT). Data sent to the codec is made active on the rising edge of BIT_CLK and then sampled by the codec on the falling edge. The serial data is not limited to PCM audio data. Frame header information and commands to configure codec registers are also sent in the bit stream. The controller receives data from the codec on SDATA_IN, but samples this data on the falling edge of BIT_CLK. The SYNC signal is used to define frame boundaries. 8 4.1. AC97 Input Frame Description The AC97 input frame is sent from the controller to the codec. The frame sync signal is used to signal the start of each frame of data sent to the codec. Figure 4.2 AC97 Input Frame Each input frame consists of 13 slots, shown below. Slot 0 is a frame header and is used to specify which of the remaining slots contain valid data. The SYNC signal is high while Slot 0 is being transmitted. The SYNC signal is raised one BIT_CLK period prior to the start of Slot 0 and is lowered during the final BIT_CLK period of Slot 0, as indicated in Figure 4.2. Commands can be issued to the codec by writing values to codec registers. Codec register values can also be read back. Commands to read or write codec registers use slots 1 and 2. (If a read command is issued, the readback data will appear in Slot 2 of the following codec output frame.) The audio data for playback is sent in slots 3 and 4. Additional audio channels are available in Slots 5-12, but are not used in this application. PCM Playback Left and Right Data are the only audio channels used in this example. 9 Slot Size Description Notes 0 16 Frame TAG / Codec ID Specified which slots contain valid data 1 20 Command Address Codec command register address 2 20 Command Data Codec command register data 3 20 PCM Playback Left Data 4 20 PCM Playback Right Data 5 20 Modem Line 1 Output Channel Not used 6 20 PCM Center Data Not used 7 20 PCM Surround Left Data Not used 8 20 PCM Surround Right Data Not used 9 20 PCM LFE Data Not used 10 20 Modem Line 2 Output Channel Not used 11 20 Modem Handset Output Channel Not used 12 20 Modem GPIO Control Channel Not used Table 4.2 AC97 Input Frame Slot Detail The total number of bits transmitted in a frame is 256. The BIT_CLK frequency, 12.288 MHz, divided by 256, is 48 kHz, which is the codec’s default audio sampling rate and is the frequency of the frame sync signal. Different sampling rates (e.g. 44.1 kHz) may be used, but the codec must be set up accordingly. If a 44.1 kHz-sample rate PCM data is fed to the codec without proper setup, the sound will appear to play “too fast.” A 48 kHz PCM signal sends 480 samples using 480 frames. Each frame will contain data. However, in the same span of time, a 44.1 kHz PCM signal will send 441 samples in 480 frames. 39 frames will not contain data. The codec takes an “on-demand” approach to 10 signal the controller when to send data through the use of slot request bits. These are described in further detail in the next section. Slot 0 is the frame header and is used to specify if data in Slots 1-12 is valid. Bit Description Default Value 15 Frame Valid 1 14 Slot 1 Valid 1 if command is to be sent 13 Slot 2 Valid 1 if command is to be sent 12 Slot 3 Valid 1 if audio data is to be sent 11 Slot 4 Valid 1 if audio data is to be sent 10 Slot 5 Valid 0 9 Slot 6 Valid 0 8 Slot 7 Valid 0 7 Slot 8 Valid 0 6 Slot 9 Valid 0 5 Slot 10 Valid 0 4 Slot 11 Valid 0 3 Slot 12 Valid 0 2 Reserved 0 1-0 Codec ID Field 00 Table 4.3 AC97 Input Slot 0 Detail 11 If a command is to be sent to the codec, Slot 1 is used to specify the command address. Bits Description Notes 19 Read/Write 1 = read, 0 = write 18 – 12 Register Index Command Address 11 – 0 Reserved 0 Table 4.4 AC97 Input Slot 1 Detail Slot 2 is used to specify the command data. Bits Description Notes 19 – 4 Register Data Command Data 3–0 Reserved 0 Table 4.5 AC97 Input Slot 2 Detail 12 4.2. AC97 Output Frame Description The AC97 output frame is data sent from the codec to the controller. This data consists of recorded audio, codec register readback data, and slot request bits. Figure 4.3 AC97 Output Frame Each output frame consists of 13 slots, shown below. Slot 1 contains two items. First is an echo of the command register address if a read command was requested in the previous input frame to the codec. The second item is the slot request bits which notify the controller to send audio data to the codec in the following frame. Codec register readback data is returned in slot 2. Captured audio data is sent in slots 3-12, but will not be used. 13 Slot Size Description Notes 0 16 Frame TAG Codec Ready Flag; flags to specify which slots contain valid data 1 20 Command Readback Address / Codec register address SLOTREQ bits 2 20 Command Readback Data Codec register status 3 20 PCM Record Left Data Not used 4 20 PCM Record Right Data Not used 5 20 Modem Line 1 ADC Not used 6 20 Dedicated Microphone Record Not used Data 7 20 Reserved Not used 8 20 Reserved Not used 9 20 Reserved Not used 10 20 Modem Line 2 ADC Not used 11 20 Modem Handset ADC Not used 12 20 Modem GPIO Status Not used Table 4.6 AC97 Output Frame Slot Detail 14 Slot 0 is the frame header and is used to specify if data in Slots 1-12 is valid. Bit Description Notes 15 Codec Ready 1 = Ready 14 Slot 1 Valid 1 = Valid, 0 = Not Valid 13 Slot 2 Valid 12 Slot 3 Valid 0 11 Slot 4 Valid 0 10 Slot 5 Valid 0 9 Slot 6 Valid 0 8 Slot 7 Valid 0 7 Slot 8 Valid 0 6 Slot 9 Valid 0 5 Slot 10 Valid 0 4 Slot 11 Valid 0 3 Slot 12 Valid 0 2–0 Reserved 000 Table 4.7 AC97 Output Slot 0 Detail Slot 1 contains the Control Register Index Echo as well as the slot request bits. When a slot request is sent from the codec, the controller must send the next audio sample in the following input frame. 15 Bits Description Notes 19 Reserved 0 18 – 12 Control Register Index Echo Echo of register address for readback data 11 Slot 3 Request (PCM Left Channel) 0 = send data, 1 = don’t send 10 Slot 4 Request (PCM Right Channel) 0 = send data, 1 = don’t send 9 Slot 5 Request (Modem Line 1) “ 8 Slot 6 Request (PCM Center) “ 7 Slot 7 Request (PCM Left Surround) “ 6 Slot 8 Request (PCM Right Surround) “ 5 Slot 9 Request (PCM LFE) “ 4 Slot 10 Request (Modem Line 2 or “ PCM Left [n+1]) 3 Slot 11 Request (Modem Handset or “ PCM Right [n+1]) 2 Slot 12 Request (PCM Center [n+1]) “ 1-0 Reserved 00 Table 4.8 AC97 Output Slot 1 Detail 16 4.3. Setting up the AC97 Setting up the AC97 device for playback requires writing values to several registers on the codec. 4.3.1. RESET REGISTER (0X00) The reset register is used to perform a master reset of the device. All written registers will be initialized to defaults. The reset register address is 0x00. Writing any value to the register will perform the reset. 4.3.2. MASTER VOLUME REGISTER (0X02) This register is used to control the master volume levels for the left and right audio channels. Left and right channels can be configured separately, though this is unnecessary for this application. Bits Description Notes Value Used 15 Master Volume Mute 1 = Mute 0 14 – 13 Reserved 00 00 12 – 8 Left Master Volume Control 1.5 dB resolution 10101 = 21 x 1.5 = 31.5 dB 7 Right Channel Mute 1 = Mute 0 6–5 Reserved 00 00 4–0 Right Master Volume Control 1.5 dB resolution 10101 = 21 x 1.5 = 31.5 dB Table 4.9 Master Volume Register Detail 17 The dB values used for the left and right volume are used to specify attenuation levels. Thus, a value of 0 dB (0) represents maximum volume while 46.5 dB (31) represents minimum volume. Attenuation can be set in increments of 1.5 dB. A fixed level of 31.5 dB was chosen for this application. 4.3.3. EXTENDED AUDIO STATUS AND CONTROL REGISTER (0X2A) This register is used for SPDIF configuration and also for enabling variable audio rates. For this application, only the variable audio enable bit in this register is used. The default audio rate is 48 kHz, but this application required 44.1 kHz, so this bit will be enabled. The bit rate is set in the PCM Front DAC Rate Register. Bits Description Notes Value Used 15 Validity Force 0 0 14 – 11 Reserved 0000 0000 10 SPDIF Configuration Valid Read Only n/a 9–6 Reserved 0000 0000 5–4 SPDIF Slot Assignment 00 00 3 Reserved 0 0 2 SPDIF Transmitter Subsystem 0 = disable 0 Enable 1 Reserved 0 0 0 Variable Rate Enable 0 = fixed rate 1 1 = variable rate Table 4.10 Extended Audio Status and Control Register Detail 18 4.3.4. PCM FRONT DAC RATE REGISTER (0X2C) This register is used to set the audio sample rate. A rate of 44.1 kHz is used. Bits Description Notes Value Used 15 – 0 Sample Rate 1 Hz resolution 44100 Hz Table 4.11 PCM Front DAC Rate Register Detail 19 4.4. RTL Implementation of AC97 Controller The Xilinx Spartan-3 FPGA is configured to act as the AC97 controller. Net Name Signal Name FPGA Pin AC97_IO0 SDATA_IN P7 AC97_IO1 BIT_CLK P6 AC97_IO2 SDATA_OUT P5 AC97_IO3 ID0 P4 AC97_IO4 ID1 P3 AC97_IO5 SYNC P2 AC97_IO6 RESET P1 Table 4.12 FPGA to AC97 Interface As described in the previous section, data received by the controller is sampled on the negative edge of the clock, while data sent from the controller is made active on the positive edge of the clock. This allows the controller to sample incoming data at the same time it is transmitting data. Table 4.13 lists the data that will be sent and received in each frame. The configuration of the codec occurs first, followed by the sending of audio data. 20 Frame To Codec (pos BIT_CLK) From Codec (neg BIT_CLK) 0 Apply Reset n/a 1 Read Status Register (0x26) n/a 2 None Status Register Response (0x26) 3 Write Master Volume (0x02) n/a 4 Write Status and Control (0x2A) n/a 5 Write Audio Frequency (0x2C) n/a 6 None Read Slot Request 1 7 Send Audio 1 Read Slot Request 2 8 Send Audio 2 Read Slot Request 3 … … … N Send Audio M n/a Table 4.13 AC97 Frame Summary The Verilog contains two always blocks. One block operates on the negative edge of BIT_CLK and is used to process the incoming data from the codec. The data processed in this block is either codec register readback data or slot requests. The second always block operates on the positive edge of BIT_CLK and either writes data to codec registers or sends audio data to the codec. 4.4.1. RECEIVING DATA FROM THE CODEC The function of the “posedge” always block is to receive data from the codec. A frame boundary is defined by the SYNC signal. The block is setup to operate in two states. 21 4.4.1.1. State 0 (Idle State) The block will wait in state 0 for the assertion of the SYNC signal to indicate the start of a frame. When SYNC is detected, execution will proceed to State 1. 4.4.1.2. State 1 (Receive Data) In State 1 the incoming data from the codec is processed. The first bit in a frame indicates the codec ready status. If this bit is high the codec is ready to receive audio data. However, if the codec is not ready, the processing of all the remaining incoming slot data from the codec is skipped for the current frame. When the codec indicates it is ready, the remaining data from the codec will be captured. The tag header (slot 0), indicating which of the remaining slots contains valid data, is captured next. The code will immediately examine the just-received slot 1 and slot2 valid bits and if valid, will latch the slot1 and slot2 data into registers. If slot1 or 2 are not indicated as valid, the slot 1 or 2 data will be ignored. Under “normal” operations (all expected validity bits valid) the code will store the codec readback register address and data and the slot request bits in separate registers. When the end of the frame is reached, PCM left and right channel request flags are set based on the values in the slot request register. These are set at the end of the input frame and are used by the output frame that immediately follows. Having the output frame use these separate slot request flags rather than the values in the slot request register directly ensures that an output frame will only send audio data if a slot request was made during the previous input frame. 22 Figure 4.4 AC97 Controller Input State Machine 4.4.2. SENDING DATA TO THE CODEC 4.4.2.1. State 0 (Initial State) In this the code will wait until the application of an external DIP switch before asserting the interrupt to the ARM requesting it to begin transferring PCM samples to the FPGA. Execution will next proceed to state 1. 4.4.2.2. State 1 (Idle State) In this state the code checks the empty flags of both FIFOs. If the FIFOs contain data execution will proceed to state 2. 4.4.2.3. State 2 (Send Slot 0: Frame Header) In state 2 the frame header (slot 0) is sent. This data indicates which of the remaining slots (1-12) are valid. Table 4.13 shows which type of data will be sent in each successive frame. A frame counter is maintained so that the correct type of data will be sent for each frame. (Certain frames are register writes, while others are audio data.) When the last bit of the header is sent, SYNC will be lowered. 23 4.4.2.4. State 3 (Send Slots 1-2: Commands and Data) In state 3 the codec commands and data (slots 1 and 2) are sent. If a read command is issued then slot 2 will be filled with zeros. If no audio data is being sent in this frame then the command and data slots will be filled with zeros. Execution will then proceed to state 6 (where empty data is sent, on account of slots 3-12 being unused), with the BIT CLK counter value set to 200 (indicating that 200 more BIT CLKs make up the slot 3-12 portion of the frame). If audio data is to be sent execution will proceed to state 4. If a left or right channel slot request has been made by the codec, indicating that audio data may be sent, the program will read the next PCM sample from the appropriate FIFO in preparation for sending the data during states 4 and 5. 4.4.2.5. State 4 (Send Slot 3: PCM Left Data) In state 4 the PCM Left data (Slot 3) is sent if the PCM Left Slot Request flag is enabled. (The audio data having been loaded into a local register during state 3.) 4.4.2.6. State 5 (Send Slot 4: PCM Right Data) In state 5 the PCM Right data (Slot 4) is sent if the PCM Right Slot Request flag is enabled. (The audio data having been loaded in to a local register during state 3.) 4.4.2.7. State 6 (Send Slots 5-12: Empty) Slots 5-12 are not used in this application. The BIT CLK counter will be set to 160 to count down the remaining BIT CLKs during these unused slots. Only zeros will be sent to the codec in this state. If during the current frame no audio was sent the BIT CLK counter will be set to 200 indicating that slots 3-12 are unused. When the BIT CLK counter reaches 1 the program will check the FIFO almost empty flags. If either FIFO is almost empty, the ARM will be signaled via interrupt to transfer more PCM samples. At the end of state 6, the program is ready to send the next AC97 frame, so execution will 24 return to state 2. If at the end of state 6, if both FIFOs are empty it is an indication that there are no additional PCM samples to be transferred from the ARM and execution will return to state 0, the initial state. 25 Figure 4.5 AC97 Controller Output State Machine 26 5. TESTING AND RESULTS 5.1. Testing Several methods to aid testing and debug were employed. A row of 8 LEDs is included on the TLL5000 board. LEDs[2:0] are configured to display the current state in the AC97 output state machine. LED[3] is configured to show when an interrupt occurred. LEDs[4:5] are configured to show the state of each FIFO. (The LED is wired to the compliment of the FIFO empty flag, so a lit LED is an indication that the FIFO contains data.) LEDs[6:7] are configured to indicate if a L or R channel slot request was sent from the AC97. The DIP switches on the board were also utilized to hold the execution in a particular state and to verify correct state transitions. The “weak link” in the debugging process was the ability to examine the serial data stream to and from the codec. Ideally a logic analyzer would be used to examine all the signals at once data. A logic analyzer would allow the capturing of an entire input and output frame to allow for more rapid debugging. 27 5.2. FPGA Synthesis Results The following table shows the device utilization summary after generating the RTL for the AC97 Controller with the Xilinx ISE tool. Logic Utilization Used Available Utilization Number of Slice Flip Flops 494 26624 1% Number of 4 input LUTs 456 26624 1% Number of occupied Slices 427 13312 2% Number of Slices containing only related logic 427 427 100% Number of Slices containing unrelated logic 0 427 0% Total Number of 4 input LUTs 511 26624 1% Number used as logic 456 Number used a route-thru 55 Number of bonded IOBs 77 487 15% Number of bonded IOB Flip Flops 32 Number of RAMB16s 10 32 31% Number of BUFGMUXs 2 8 25% Logic Distribution Table 5.1 Device Utilization Summary 28 The following table summarizes the components used. Component Number Component Number ROMs 1 Comparators 10 8x16-bit ROM 1 3-bit comparator less 1 Adders/Subtractors 4 8-bit comparator greatequal 1 3-bit adder 1 8-bit comparator greater 4 8-bit subtractor 1 8-bit comparator less 3 9-bit adder 1 8-bit comparator lessequal 1 9-bit subtractor 1 Multiplexers 7 Counters 1 1-bit 16-to-1 multiplexer 3 8-bit up counter 1 1-bit 20-to-1 multiplexer 2 Registers 42 3-bit 8-to-1 multiplexer 1 1-bit registers 32 8-bit 8-to-1 multiplexer 1 16-bit registers 3 Tristates 1 20-bit registers 4 32-bit tristate buffer 1 3-bit registers 2 8-bit registers 1 Table 5.2 Component Summary 29 The following table summarizes the clock characteristics. Clock Net Net Skew Max Delay (ns) (ns) BUFGMUX2 180 0.341 1.115 MZ_CPLD_CLKO_BUFGP BUFGMUX1 158 0.311 1.115 AC_BIT_CLK_BUFGP Resource Fanout Table 5.3 Clock Summary 30 REFERENCES [1] Analog Devices. AC ’97 SoundMAX® Codec. Revision A. 2005. [2] Pramod Chandraiah and Rainer Dömer. Specification and Design of a MP3 Decoder. Center for Embedded Computer Systems, University of California, Irvine. . May 2005. [3] Andreas Gerstlauer, Dogwan Shin, Samar Abdi, Pramod Chandraiah, Daniel Gajski. Design of a MP3 Decoder using the System-On-Chip Environment (SCE). Center for Embedded Computer Systems, University of California, Irvine. November 2007 [4] The Learning Labs. TLL5000 Electronic System Design Base Module User Guide. Version 1.3. 2008. [5] The Learning Labs. TLL6219 Embedded Systems Design Module User Guide. Version 2.0. 2008. [6] The Learning Labs. AC 97 Audio Codec. 2007. [7] Intel. Audio Codec ’97. Revision 2.3. April 2002. [8] Xilinx. LogicCore™ IP FIFO Generator v4.3 User Guide. Revision 8.0. March 2008. [9] Xilinx. Spartan-3 Generation FPGA User Guide. Revision 1.5. January 2009. 31 VITA The author is a 2001 graduate of Lehigh University with a degree in computer engineering. He has worked for Northrop Grumman, AAI Test Systems (formerly Symtx), and now Motorola as a test engineer. Permanent email: [email protected] This report was typed by Joel Thomas Williams. 32