Transcript
cPCI-EK01
Multifunction data acquisition board INTRODUCTION This product is specially designed for Compact PCI master and target logic development and an analog data acquisition board. Also it can be used for multi-purpose applications, for example waveform generator, high current driver and high speed analog data logger.
GENERAL DESCRIPTION ♦ ♦ ♦ ♦ ♦ ♦ ♦
Multi-function Data acquisition board PCI target 32bit/33Mhz 12bit 8 channel A/D input 12bit 4 channel D/A output 24 General Purpose I/O 32bit Timer/Counter 8M bit(4M bit with Type A) High speed (12nSEC) SRAM
APPLICATION ♦ ♦ ♦ ♦ ♦
Compact PCI Development and Evaluation Digital Data Acquisition Laboratory Instrumentation Process Control Systems Factory Automation
SOFTWARE ▣ Operating System ▪ Windows 2000/XP ▣ Application Programming Interface ▪ Direct control through WDM driver ▪ Windows DLL API
▣ Software Development Kits ▪ User who have strong interest in developing PCI DAQ board can buy SDK. ▪ SDK contents Basic VHDL source WDM Driver source DLL source ▪ Test Application(Waveform generator/ Waveform Display)
PHYSICAL/ENVIRONMENTAL ▣ Dimensions ▪ Standard 3U Compact PCI 32bit Form-Factor (160mm x 100mm) ▣ Temperature ▪ 0 to 70℃, Operating ▪ -20 to 80℃ Storage ▣ Relative Humidity ▪ 20 to 80 Percent, Non-condensing ▣ Power Requirement ▪ +5VDC(±5%) at max. 1A
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SPECIFICATION
▣ Analog output
▣ Flexible Board
▪ 12bit resolution
▪ PCI Target 32bit/33Mhz
▪ 4 channel output
▪ PCI 5V/3.3V Compatible
▪ 0 to +5V output range
▪ Full 33Mhz burst read/write operation
▪ MAX 1M (1uSEC) update rate
▪ Average data rate is 30MB data to, 8MB
▪ Can change update interval in waveform
data from the board without DMA.
generation mode by 1uSEC increment
▪ Very flexible to upgrade because of FPGA
▪ Simultaneous update of outputs
is used as PCI bridge and overall board
▪ ±16 (LSB) INL
control.
▪ ±1 (LSB) DNL
▪ Spartan 3 (XC3S200)
▪ ±3 (LSB) Offset error
▪ 8Mbit(256K x 16) fast SRAM
▪ ±1 (LSB) Gain error
▪ 2 User input tact switch
▪ Slew Rate 0.7V/usec
▪ 6 User definable output LED indication
▪ On-board 1024 x 16 waveform generation
▪ User expandable local memory through
dual-port RAM
64pin header connector.(3.3V operation)
▪ In waveform generation mode, user can
▪ user selectable oscillator ▪ Video interface (TBD)
select any channel order. ▣ Digital I/O(Rear I/O Option)
▪ UART interface (TBD)
▪ On-board 82C55 chip ▪ 24bit general purpose I/O
▣ Analog input
▪ Three 8bit group(Port A/B/C)
▪ 12bit resolution
▪ 3.3V CMOS logic level
▪ 8 Single ended or 4 Differential Input ▪ 0 to +5V, ±2.5V Input Range
▪ Power on floating or logic low ▣ Timer/Counter
▪ Max. 200Ksps(5uSEC) conversion time
▪ Three 32-bit Timer
▪ Can change sampling interval in auto
▪ Three 32-bit Counter
scanning mode by 2.5uSEC increment
▪ Input Frequency max. 60Mhz
▪ Power on auto-calibration
▪ 25n Timer Resolution
▪ ±1 (LSB) INL/DNL
▪ One-shot or alternate timer output mode
▪ ±1uA analog input leakage current
▪ 3.3V CMOS logic level I/O interface
▪ 20pF analog input capacitance ▪ On-board 1024 x 16 data FIFO
5V tolerant. ▣ External connection
▪ On-board 512K(type B) x 16 data SRAM
▪ 37pin D-sub(Analog in-out, timer/counter)
▪ User can select ADC data storage, FIFO or
▪ 64pin Box-header(Local memory bus)
SRAM
▪ 10pin Header(Video signal) --- Future
▪ In auto scanning mode, user can select
Upgrade
any channel order.
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37pin D-sub(Analog in-out, timer/counter)
VDD(+3.3V)
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2
VDD(+3.3V)
ADDRESS 00
3
4
DATA 0
ADDRESS 01
5
6
DATA 1
ADDRESS 02
7
8
DATA 2
ADDRESS 03
9
10
DATA 3
ADDRESS 04
11
12
DATA 4
ADDRESS 05
13
14
DATA 5
ADDRESS 06
15
16
DATA 6
ADDRESS 07
17
18
DATA 7
ADDRESS 08
19
20
DATA 8
ADDRESS 09
21
22
DATA 9
ADDRESS 10
23
24
DATA 10
ADDRESS 11
25
26
DATA 11
ADDRESS 12
27
28
DATA 12
ADDRESS 13
29
30
DATA 13
ADDRESS 14
31
32
DATA 14
ADDRESS 15
33
34
DATA 15
ADDRESS 16
35
36
BYTE EN1 LOW#
ADDRESS 17
37
38
BYTE EN1 HIGH#
Digital Ground
39
40
OE#
DATA 16
41
42
WE#
DATA 17
43
44
CE1#
DATA 18
45
46
Digital Ground
DATA 19
47
48
DATA 27
DATA 20
49
50
DATA 28
DATA 21
51
52
DATA 29
DATA 22
53
54
DATA 30
DATA 23
55
56
DATA 31
DATA 24
57
58
BYTE EN2 LOW#
DATA 25
59
60
BYTE EN2 HIGH#
DATA 26
61
62
CE2#
Digital Ground
63
64
Digital Ground
64pin Box-header(Local memory bus)
BLOCK DIAGRAM USER I/O
Switch & LED I/O
PCI BUS
SRAM Core control T/Rx
UART
ADC
FIFO
DAC
DPRAM
LEVEL SHIFTER
TARGET PCI INTERFACE
TIMER COUNTER
POWER DISTRIBUTION
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