Transcript
cPCI6U64-24DSI20C500K Multi-Range 24-Bit, 20-Channel, 500KSPS cPCI 6U Analog Input Module With 20 Multirange Delta-Sigma Input Channels
Features Include:
20 Multirange differential 24-Bit simultaneously-sampled analog input channels.
Input sample rates from 2 to 500 Kilosamples per second per channel.
Software-selectable analog input ranges of ±10V, ±5V, ±2.5V and ±1.25V.
Delta-Sigma input conversion minimizes or eliminates the need for antialias filtering.
256K-sample analog input FIFO buffer.
Continuous and Burst (One-shot) sampling modes.
Sample clock source selected as internal or external.
Supports multiboard synchronization of analog inputs.
Auxiliary internal connector provides clock and sync I/O capability within the enclosure.
On-demand internal offset and gain autocalibration of all analog inputs.
4-Bit bi-directional digital port.
Software-controlled master-clock frequency fine-adjustment.
cPCI 6U form factor. (Contact factory for availability in PCI and PCI-Express form factors).
Front-Panel system I/O connector.
66MHz 64-bit PCI support, with universal 5V/3.3V signaling and DMA support. PCI burst rates to 400MB/sec.
Applications: Sonar Arrays Analog Inputs
Voltage Acquisition Acoustic Research
Phase Comparison Audio Waveform Analysis
PRELIMINARY REV 092310A
Overview: The 20-channel cPCI6U64-24DSI20C500K analog input module provides high-density 24-bit analog input resources on an industry-standard module. Optimized for flexibility and performance, the board is ideal for a wide variety of applications, ranging from simple precision voltage measurements, to the analysis of complex audio signals and waveforms.
Functional Description: Each of 20 analog input channels contains a lowpass analog image filter and a delta-sigma A/D converter that provides inherent antialias suppression and sharp cutoff lowpass filtering. An internal voltage reference can be applied to all channels to support selftest operations and autocalibration. Gain and offset trimming is performed by applying correction values that are determined during on-demand autocalibration. A linear-phase digital antialiasing filter rejects out-of-band signals, and a lowpass analog filter rejects those interference signals that fall within the harmonic images of the digital filter. An internal sample-rate generator is adjustable over a 2:1 frequency range, and is divided down within the local controller to provide individual channel sample rates from 2KSPS to 500KSPS. Conversion data from all active channels is transferred to the PCI bus through a 256K-sample data buffer that is supported by two DMA channels. Multiple channels can be synchronized to perform sampling in "lockstep", either by a software command, or by external hardware sync and clock input signals.
I/O Conn Analog Inputs (20 Diff)
Input Configuration Switches
Scaling & Filters
24-Bit ADC’s (20)
Input Control
Voltage Reference
Input Data
External Sync I/O, Digital I/O Sample-Rate Generator Local Controller Control Conn Bus Interface Adapter
Local Bus
Figure 1. cPCI6U64-24DSI20C500K; Functional Organization This product is functionally compatible with the IEEE PCI local bus specification Revision 2.3. System input/output connections are made at the front panel through a high-density 100-Pin I/O connector. Power requirements consist of +5 VDC, in compliance with the PCI specification, and operation over the specified temperature range is achieved with conventional air cooling.
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ELECTRICAL SPECIFICATIONS At +25 OC, with specified operating conditions.
Input Characteristics: Configuration:
20 two-wire differential input channels. 12, 8 and 4-channel configurations also available.
Voltage Range:
Software-configurable as ±10V, ±5V, ±2.5V or ±1.25V
Input Impedance:
1.0 Megohm typical, in parallel with 20 pF.
Common Mode Rejection:
80dB to 15kHz on ±10V range; 85dB on lower ranges; typical
Common Mode Range:
±11 Volts with zero normal-mode input
Overvoltage Protection:
±25-Volt transients with power applied; ±12 Volts with power removed
2.0 Megohms line-line.
Transfer Characteristics: Conversion Architecture:
24-Bit Delta-Sigma
Sample Rate:
2-500 kilosamples per second per channel.
Oversampling Factor:
x32 (16-500KSPS), x64 (8-250KSPS), x256 (2-62.5KSPS)
DC Accuracy: (Mean composite error after autocalibration)
Input Range ±10V ±5V ±2.5V ±1.25V
Passband:
DC to 40%t of the sample rate at -0.1dB, or 41% at -3dB; Typical.
Passband Ripple:
±0.05dB maximum
Stopband threshold:
Typically 50 percent of the selected sample rate.
Stopband Attenuation:
110dB Typical
Integral Nonlinearity (INL)
0.001 percent of fullscale range; typical.
No Missing Codes
24 Bits.
Dynamic Range:
110dB typical with oversampling at x256; 105dB at x32. ±10V range
SINAD:
104dB typical with oversampling at x256; 101dB at x32. ±10V range
Interchannel Crosstalk:
-96dB typical to 40kHz
Phase Skew:
Typically less than 100ns (0.1-Degree for Fsig = 5kHz), with Fsig/Fsamp <0.35; channel-channel (board-board for multiboard configurations), excluding noise.
Antialias Filtering:
Each ADC provides linear-phase digital lowpass filtering as indicated for "passband" and "stopband". In addition to the digital filter, a 2nd-order Butterworth lowpass analog image filter in each channel provides a -3dB cutoff frequency of approximately 2MHz to suppress images from the digital filter. Optional alternative image filter frequencies are available, and should be selected to be well above the expected passband.
Midrange (Zero) Accuracy ±1.5mv ±1.0mv ±0.6mv ±0.4mv
±Fullscale Accuracy . ±6.0mv ±3.8mv ±2.2mv ±1.5mv
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Operating Modes and Controls: Organization:
All input channels operate at the same sample rate, controlled by division of an internal or external rate generator frequency.
Sampling Clock I/O:
The sampling clock can be derived either from an internal rate generator, or from a TTL or LVDS external hardware input. Multiple boards can be locked to a common clock by daisy-chaining the output clock from each board to the input clock of the next board in the chain. Any number of boards can be daisy-chained together, with a typical propagation delay of 10ns introduced per board. The 'star-configuration' also is supported.
Internal Rate Generator:
An internal PLL rate generator provide sample rates from 2 KSPS to 500 KSPS. The frequency of the generator is controlled by the ratio of two 10-Bit integers, and a 6-Bit divisor, with a setting accuracy of 25 PPM.
Synchronization:
Daisy-chained or 'star-configuration' hardware sync inputs and outputs can be used to synchronize sampling among multiple boards.
Burst Timing:
Triggered burst sampling can be timed either internally or externally.
Data Format:
Software-selectable as either offset binary or two's complement. Width of the data field is selectable as 16, 18, 20 or 24 bits.
Channel Tags:
A 4-bit channel tag is appended to each input data value.
Buffer Access:
The input buffer FIFO is accessed through either of two DMA channels, with both block-mode and demand-mode transfers supported.
Master Clock Adjustment:
Master-clock frequency software-adjustable around center frequency.
Auxiliary External Sync I/O:
A 6-pin internal connector provides TTL clock and sync I/O capability within the enclosure.
Digital I/O
Four general-purpose TTL digital I/O lines are individually selectable as either inputs or outputs. Maximum output loading is ±8mA. Input loading consists of 33K-ohms resistors to +3.3V
approximately
±100PPM
PCI Compatibility: Conforms to PCI Specification 2.3: D32, 33/66MHz, 64-bit universal (3.3V/5V) signaling. Two-Channel DMA as bus master in block and demand modes.
Power Requirements: +5.0 VDC ±0.25 VDC at: 20-Channel Configuration: 4.3 Amps typical, 4.8 Amps, maximum 4-Channel Configuration: 1.4 Amps typical, 1.8 Amps, maximum
Mechanical Characteristic: Dimensions (HxWxD):
160 mm (6.30 in) x 21.6 mm (0.85 in) x 233.3 mm (9.19 in)
(Mechanical dimensions are shown for the cPCI 6U form factor. See Ordering Information.)
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Environmental Specifications: Ambient Temperature Range: Standard Temperature:
Operating: 0 to +70 Degrees Celsius * Storage: -40 to +85 Degrees Celsius
Extended Temperature:
Operating: -40 to +80 Degrees Celsius * Storage: -40 to +85 Degrees Celsius * Air temperature at board surface.
Relative Humidity:
0 to 95%, non-condensing
Altitude:
Operation to 10,000 ft.
Cooling:
Conventional air cooling; 150 LFPM
Ordering Information: Specify the basic product model number followed by an option suffix "-A-B-C", as indicated below. For example, model number cPCI64-24DSI20C500K-20-SF-0 describes a 6U cPCI module with 20 input channels, standard image filter frequency, and no custom features. For industrial (extended) temperature operation, add "-I" at the end of the model number.
Optional Parameter Number of Input Channels
Image Filter -3dB Frequency
Custom Features 1
Value
Specify Option As:
4 Channels
A=4
8 Channels
A=8
12 Channels
A = 12
20 Channels
A = 20
Standard 2.0MHz (-0.1dB at 300kHz)
B = SF
Custom Frequencies:
B = CFx
No Filter:
B = NF
No custom features
C=0
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"x" = Filter frequency. ±15% frequency accuracy, 100kHz-4.0kHz. Contact factory for availability of specific frequencies.
(Contact factory for availability in PCI and PCI-Express form factors).
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SYSTEM I/O CONNECTIONS Table 1. System I/O Connector PIN 1
CLOCK INPUT LO
2
CLOCK INPUT HI
3
SYNC INPUT LO
1
1
1
1
PIN 1
ROW-B FUNCTION CLOCK OUTPUT LO
2
CLOCK OUTPUT HI
3
SYNC OUTPUT LO
SYNC INPUT HI DIGITAL RETURN DIGITAL RETURN INPUT RETURN
4
5 6 7 8 9
INPUT RETURN INPUT CH 00 LO
8 9
10 11
INPUT CH 00 HI INPUT RETURN
10 11
DIGITAL RETURN
12 13
INPUT RETURN INPUT CH 01 LO
12 13
DIGITAL RETURN
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
INPUT CH 01 HI INPUT RETURN INPUT RETURN INPUT CH 02 LO INPUT CH 02 HI INPUT RETURN INPUT RETURN INPUT CH 03 LO INPUT CH 03 HI INPUT RETURN INPUT RETURN INPUT CH 04 LO INPUT CH 04 HI INPUT RETURN INPUT RETURN INPUT CH 05 LO INPUT CH 05 HI INPUT RETURN INPUT RETURN INPUT CH 06 LO INPUT CH 06 HI INPUT RETURN INPUT RETURN INPUT CH 07 LO INPUT CH 07 HI INPUT RETURN INPUT RETURN INPUT CH 08 LO INPUT CH 08 HI INPUT RETURN INPUT RETURN INPUT CH 09 LO INPUT CH 09 HI INPUT RETURN INPUT RETURN INPUT CH 10 LO INPUT CH 10 HI
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DIGITAL RETURN INPUT RETURN INPUT RETURN INPUT CH 11 LO INPUT CH 11 HI INPUT RETURN INPUT RETURN INPUT CH 12 LO INPUT CH 12 HI INPUT RETURN INPUT RETURN INPUT CH 13 LO INPUT CH 13 HI INPUT RETURN INPUT RETURN INPUT CH 14 LO INPUT CH 14 HI INPUT RETURN INPUT RETURN INPUT CH 15 LO INPUT CH 15 HI INPUT RETURN INPUT RETURN INPUT CH 16 LO INPUT CH 16 HI INPUT RETURN INPUT RETURN INPUT CH 17 LO INPUT CH 17 HI INPUT RETURN INPUT RETURN INPUT CH 18 LO INPUT CH 18 HI INPUT RETURN INPUT RETURN INPUT CH 19 LO INPUT CH 19 HI
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1
ROW-A FUNCTION
5 6 7
SYNC OUTPUT HI DIGITAL RETURN DIGITAL RETURN
1
1
1
1
DIO_00 DIGITAL RETURN
DIO_01 DIO_02 DIO_03
TTL signal levels on HI pins when TTL sync I/O is selected. Otherwise LVDS. Leave LO inputs disconnected in TTL mode.
Figure 2. System I/O Connections System Cable Mating Connector: 100-Pin 2-row 0.050" dual ribbon-cable connector: AMP # 749621-9. I/O Connector Installed on Board (For reference): AMP # 787170-9
Table 2. Aux Sync I/O Connector PIN 1
SIGNAL DIGITAL RTN
2
AUX CLOCK I/O
3
DIGITAL RTN
4
AUX SYNC I/O
5
DIGITAL RTN
6
Reserved. Ground or leave disconnected.
General Standards Corporation assumes no responsibility for the use of any circuits in this product. No circuit patent licenses are implied. Information included herein supersedes previously published specifications on this product and is subject to change without notice.
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