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D2X533BW-X256 PDRB-29998-X117-01 DATA SHEET Memory Module Part Number D2X533BW-X256 BUFFALO INC. (1/8) D2X533BW-X256 PDRB-29998-X117-01 1. Description DDR2-533 144pin 32bit DIMM EP2-2100/CL=4,tRCD=4,tRP=4 2. Module Specification Item Capacity Physical Bank(s) Module Organization Module Type Speed Grade Interface Power Supply Voltage Burst Lengths DRAM Organization PCB Part No. PCB Layer Contact Tab Serial PD Specification 256MByte 1 64M x 32bit Unbuffered NonECC EP2-2100/CL=4, tRCD=4, tRP=4 (266MHz Double Data Rate) EP2-1600/CL=3, tRCD=3, tRP=3 (200MHz Double Data Rate) SSTL_18 1.8V±0.1V 4,8 64M x 16bit DDR2 SDRAM 2DXA2GF-A 6 Layers 144pin GOLD Flash Plating Ni : min 2.00µm / Au : min 0.05µm Support 3. Mechanical Design Item Mechanical Design Reference standard Mechanical Design and Pinout DDR2 144Pin 32bit DIMM (PDRB-29998-X086-**) Y(PCB Height) Z1 Z2 : 30.00 ± 0.15mm : 3.60mm : Undefined 4. Block Diagram Item Block Diagram Reference standard Block Diagram DDR2 Unbuffered 32bit DIMM(x16bitDRAM 1Bank) (PDRB-29998-X082-**) BUFFALO INC. (2/8) D2X533BW-X256 PDRB-29998-X117-01 5. Electrical Specifications 5.1 Absolute Maximum Ratings Parameter Symbol Power supply voltage Power supply voltage for Output Input and output voltage Operating case surface temperature Storage temperature Value -1.0～2.3 -0.5～2.3 -0.5～2.3 0～85 -55～100 VCC VCCQ VIN,VOUT TC TSTG Unit V V V °C °C 5.2 Recommended Operating Conditions Parameter Symbol MIN MAX Unit VCC,VCCQ VCCSPD VREF VTT VIH(dc) VIL(dc) VIH(ac) VIL(ac) VID(ac) VIX(ac) VOX(ac) 1.7 1.7 0.49x VCCQ VREF-0.04 VREF+0.125 -0.3 VREF+0.250 —— 0.5 0.5*VCCQ-0.175 0.5*VCCQ-0.125 1.9 3.6 0.51x VCCQ VREF+0.04 VCCQ+0.3 VREF-0.125 —— VREF-0.250 VCCQ+0.6 0.5*VCCQ+0.175 0.5*VCCQ+0.125 V V V V V V V V V V V Symbol Maximum Pin Capacitance CICK0 CICK1 8 8 pF CK1, /CK1 /S Input Pin Capacitance /S0 /S1 CIS0 CIS1 4 —— pF pF CKE Input Pin Capacitance CKE0 CKE1 CICKE0 CICKE1 4 —— pF pF ODT Input Pin Capacitance ODT0 ODT1 CIODT0 CIODT1 4 —— pF pF DQS0~DQS3 CIDQS 4 pF /DQS0~/DQS3 DM0~DM3 CIDQSN CIDQS 4 4 pF pF Power supply voltage Power supply voltage for SPD Reference Voltage Termination Voltage DC input logic high voltage DC input logic low voltage AC input logic high voltage AC input logic low voltage AC differential input voltage AC differential cross point voltage (input) AC differential cross point voltage (output) 5.3 Pin Capacitances Parameter CK Input Pin Capacitance DQS,/DQS Input,Output Pin Capacitance CK0, /CK0 DQ Input,Output Pin Capacitance DQ0~DQ31 Other Input Pin Capacitance A,BA,/RAS,/CAS,/WE Unit pF COUT 4 pF CIN 7 pF BUFFALO INC. (3/8) D2X533BW-X256 PDRB-29998-X117-01 5.4 D.C. Characters Parameter Symbol Value Unit Operationg Current for One Bank Active-precharge ICC0 MAX 520 * mA Operationg Current for One Bank Operation ICC1 MAX 680 * mA Precharge Power-down Standby Current ICC2P MAX 60 * mA Precharge Quiet Standby Current ICC2Q MAX 180 * mA Precharge Standby Current ICC2N MAX 200 * mA ICC3P-F MAX 160 * mA ICC3P-S MAX 100 * mA Active Power-down Standby Current Test Condition Operating one bank active precharge current : CKE=high Operating one bank active read-precharge current : CKE=high, BL4, AL0 Precharge power-down current : All banks idle, CKE=low Precharge quiet standby current : All banks idle, CKE=high Precharge standby current : All banks idle, CKE=high Active power down current (Fast PDN Exit) : All banks open, CKE=low, MRS(12)=0 Active power down current (Slow PDN Exit) : All banks open, CKE=low, MRS(12)=1 Active standby current : All bank open, CKE=high Operating burst write current : All banks open, Continuous burst writes, CKE=high, BL4, AL0 Operating burst read current : All banks open, Continuous burst reads, CKE=high, BL4, AL0 Burst refresh current : CKE=high Self refresh current : CK=0V, /CK=0V, CKE ≤ 0.2V Operating bank interleave read current : All bank interleaving reads, BL4, AL=tRCD-1tCK Active Standby Current ICC3N MAX 340 * mA Operating Current for Burst Write ICC4W MAX 1240 * mA Operating Current for Burst Read ICC4R MAX 1220 * mA Auto Refresh Current ICC5 MAX 1280 * mA Self Refresh Current ICC6 MAX 60 * mA Operating Current for Four Bank Operation ICC7 MAX 2000 * mA MIN MAX MIN MIN -20 20 -13.4 13.4 * * * * µA VSS ≤ VIN ≤ VCC µA mA VOH = 1,420mV mA VOL = 280mV Input Leakage Current ILI Output High Current Output Low Current IOH IOL * : No guarantee against this value. BUFFALO INC. (4/8) D2X533BW-X256 PDRB-29998-X117-01 5.5 A.C. Timing Characters Parameter Clock cycle time /CAS Latency = 3 /CAS Latency = 4 Clock high level width Clock low level width DQ output access time from CK Symbol tCK tCH tCL /CAS Latency = 3 /CAS Latency = 4 DQ DM input setup time relative to DQS DQ DM input hold time relative to DQS Data hold skew factor DQS output access time from CK , /CK DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge to CK hold time DQS-DQ skew for DQS and associated DQ signals Read preamble Read postamble Write preamble Write postamble Write command to first DQS latching transition Address,command input setup time Address,command input hold time Active to read or write delay Precharge command period Active to precharge command (tCK<5,000ps) (tCK>=5,000ps) Active-active/auto refresh clock period (tCK<5,000ps) (tCK>=5,000ps) Active to active command period Cas to cas command delay Write recovery time Mode register set command cycle time Minimum time clocks remains ON after CKE asynchronously drops low Average periodic refresh interval Refresh to active/refresh command time Exit self refresh to a non-read command Exit self refresh to a read command Exit prechatge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on tAC tDS tDH tQHS tDQSCK tDQSH tDQSL tDSS tDSH tDQSQ tRPRE tRPST tWPRE tWPST tDQSS tIS tIH tRCD tRP tRAS tRC tRRD tCCD tWR tMRD MIN MAX 5,000 8,000 3,750 8,000 0.45 0.55 0.45 0.55 -600 600 -500 500 100 —— 225 —— —— 400 -450 450 0.35 —— 0.35 —— 0.2 —— 0.2 —— —— 300 0.9 1.1 0.4 0.6 0.35 —— 0.4 0.6 WL-0.25 (*1) WL+0.25 (*1) 250 —— 375 —— 15 —— 15 —— 45 70k 40 70k 60 —— 55 —— 10 —— 2 —— 15 —— 2 —— Unit ps ck ck ps ps ps ps ps ck ck ck ck ps ck ck ck ck ck ps ps ns ns ns ns ns ck ns ck tDELAY tIS+tCK+tIH —— ns tREFI tRFC tXSNR tXSRD tXP tXARD —— 127.5 tRFC +10 200 2 2 7.8 70k —— —— —— —— µs ns ns ck ck ck tXARDS 6-AL (*2) —— ck tCKE tAOND tAON 3 —— ck ck ns ODT turn-on (Power-Down mode) tAONPD ODT turn-off delay ODT turn-off tAOFD tAOF ODT turn-off (Power-Down mode) tAOFPD ODT to power down entry latency ODT power down exit latency tANPD tAXPD 2 tAC(Min) tAC(Max)+1 2tCK tAC(Min)+2 +tAC(Max)+1 2.5 tAC(Min) tAC(Max)+0.6 2.5tCK tAC(Min)+2 +tAC(Max)+1 3 —— 8 —— *1 : WL=Write Latency *2 : AL=Additive Latency ns ck ns ns ck ck BUFFALO INC. (5/8) D2X533BW-X256 PDRB-29998-X117-01 6. Serial Presence Detect (SPD) Data Structure Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47-61 62 63 64-66 67 68-71 72 73-90 91-92 93-94 95-98 99-127 128+ Function Defines # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM..) # of row addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly Reserved Voltage interface standard of this assembly SDRAM Cycle time (highest CAS latency) SDRAM Access from Clock (highest CAS latency) DIMM Configuration type (non-parity, ECC) Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM width Reserved Burst Lengths Supported # of Banks on Each SDRAM Device CAS# Latency Reserved DIMM Type Information SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle time (2nd highest CAS latency) SDRAM Access from Clock (2nd highest CAS latency) SDRAM Cycle time (3rd highest CAS latency) SDRAM Access from Clock (3rd highest CAS latency) Minimum Row Precharge Time (tRP) Row Activate to Row Activate Min. (tRRD) RAS to CAS Delay Min (tRCD) Minimum RAS Pulse Width (tRASmin) Density of each bank on module Command and Address signal input setup time Command and Address signal input hold time Data signal input setup time Data signal input hold time Write recovery time (tWR) Internal Write to Read command delay (tWTR) Internal Read to Precharge command delay (tRTP) Memory Analysis Probe charactristics Extension of Byte41 tRC and Byte42 tRFC SDRAM Device Minimum Active to Active/Auto Refresh Time(tRC) SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh(tRFC) SDRAM Device Maximum device cycle time(tCKmax) SDRAM Device Maximum skew between DQS and DQ signals(tDQSQ) DDR SDRAM Device Maximum Read DataHold Skew Factor(tQHS) PLL Relock Time Superset Information (may be used in future) SPD Data Revision Code Checksum for bytes 0-62 Manufacturer’s JEDEC ID code per JEP-106 Manufacturing Location Manufacturer’s Part Number Revision Code Manufacturing Date Assembly Serial Number Manufacturer Specific Data Unused storage locations Hex Value Function Supported 80 08 08 0D 0A 60 20 00 05 3D 50 00 82 10 00 00 0C 08 18 00 00 00 01 50 60 00 00 3C 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 06 3C 7F 80 1E 28 00 00 10 D2 7F 83 00 01 20 00 ―― ―― ―― ―― 128 Bytes 256 Bytes DDR2-SDRAM 13 10 1Bank 32bits Undefined SSTL-18 3,750ps (CL=4) 500ps (CL=4) NON-ECC 7.8µs x16 bit Non Use Undefined Burst Lengths (4,8) 8Bank CAS Latency =4,3 Undefined Non Support Normal Weak drive support 5,000ps(CL=3) 600ps(CL=3) N/A (CL=2) N/A (CL=2) 15 ns 10 ns 15 ns 45ns 256MB 250ps 375ps 100ps 225ps 15ns 7.5ns 7.5ns TBD Extension of Byte41,42 60ns 127.5ns 8,000ps 300ps 400ps Undefined Undefined Rev.1.0 Checksum BUFFALO BLANK Undefined Undefined Undefined Undefined Undefined BUFFALO INC. (6/8) D2X533BW-X256 PDRB-29998-X117-01 7. Packing/Label Specification Item Packing/Label Specification Reference standard Packing/Label Specification –for SO-DIMM (PDRB-28998-X063-xx) BUFFALO INC. (7/8) D2X533BW-X256 PDRB-29998-X117-01 8. Revision History Rev. 01 Date Jun.13.2007 Changes ------------- Issued M.Goto(D05) BUFFALO INC. (8/8)