Transcript
AMMP-6120
8-24 GHz x2 Frequency Multiplier
Data Sheet
Description
Features
Avago Technologies’ AMMP-6120 is an easy-to-use integrated frequency multiplier (x2) in a surface mount package designed for commercial communication systems. The MMIC takes a 4 to 12 GHz input signal and doubles it to 8 to 24 GHz. It has integrated amplification, matching, harmonic suppression, and bias networks. The input/output are matched to 50 Ω and fully DC blocked. The MMIC is fabricated using PHEMT technology.
• 5x5mm Surface Mount Package
The backside of the package is both RF and DC ground. This helps simplify the assembly process and reduces assembly related performance variations and costs. The surface mount package allows elimination of “chip & wire” assembly for lower cost. This MMIC is a cost effective alternative to hybrid (discrete-FET), passive, and diode doublers that require complex tuning and assembly processes.
• Frequency Range : 8-24 GHz output (Useable to 26 GHz) • Broad input power range: -11 to +5 dBm • Output Power : +16 to +18 dBm • Harmonic Suppression : 20 dBc (Fundamental) • DC requirements : -1.4V and 5V, 112 mA @ Pin= +3dBm
Applications • Microwave Radio systems • Satellite VSAT and DBS systems • Commercial grade military • 802.16 & 802.20 WiMax BWA systems • WLL and MMDS loops
Vd 1
Vg 2
3 Pin
Function
1
Vd
2
Vg
3 X2
RFin 8
4 RFout
4
RF Out
5 6 7 7
6 5 top view package base: RF and DC GND
8
RF In
Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) ESD Human Body Model (Class 1A) Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control.
AMMP-6120 Absolute Maximum Ratings[1] Symbol
Parameters/Conditions
Unit
Minimum
Maximum
Vd
Positive Drain Voltage
V
Vg
Gate Supply Voltage
V
Id
Drain Current
mA
120
Pin
CW Input Power
dBm
15
Tch
Operating Channel Temp.
°C
+150
Tstg
Storage Case Temp.
°C
Tmax
Maximum Assembly Temp.(60 sec. max.)
°C
7 -3.0
-65
+0.5
+150 +300
Note: 1. Operation in excess of any one of these conditions may result in permanent damage to this device.
AMMP-6120 DC Specifications/Physical Properties [1] Symbol
Parameters and Test Conditions
Units
Typ.
Maximum
Id
Drain Supply Current (under any RF power drive and temperature) (Vd=5V)
mA
85
110
Ig
Gate Current
mA
9
qch-b
Thermal Resistance [2] (Backside temperature, Tb = 25°C)
°C/W
34
Notes: 1. Ambient operational temperature TA=25°C unless otherwise noted. 2. Channel-to-backside Thermal Resistance (Tchannel (Tc) = 34°C) as measured using infrared microscopy. Thermal Resistance at backside temperature (Tb) = 25°C calculated from measured data.
RF Specifications (3,4) (TA=25°C, Vd=5V, Vg=-1.4V, Id(Q)=85mA, Zin=Zout=50Ω) Symbol
Parameters and Test Conditions
Units
Minimum
Typ.
Pout
Output Power [5]
dBm
13
16
Rlin
Input Return Loss
dB
-15
RLout
Output Return Loss
dB
-10
IP-1dB
Input Power @ 1dB Gain Comp
dBm
2
Sup
Fundamental Suppresion [5]
dBc
Sup3
3rd Harmonic Suppression
dBc
25
Sup4
4th Harmonic Suppression
dBc
35
SSBPN
Single Side Band Phase Noise (@100kHz offset)
dBc Hz
18
25
-140 (fout=15.6GHz)
Notes: 3. Small/Large -signal data measured in a fully de-embedded test fixture form TA = 25°C. 4. Pre-assembly into package performance verified 100% on-wafer. 5. This final package part performance is verified by a functional test correlated to actual performance at Fout=10GHz output, Pin=+3dBm. 6. All tested parameters guaranteed with measurement accuracy ±0.5dBm for Pout and ±3dBc for FS.
AMMP-6120 Typical Performances 20 15 10 5 0 -5 -10 -15 -20 -25 -30
2H 1H 3H 4H
8
10
12
14
16
Output Power (dBm)
Output Power (dBm)
(TA = 25°C,Zin = Zout = 50 Ω, Vd=5V, Vg=-1.4V)
18
20
22
24
26
20 15 10 5 0 -5 -10 -15 -20 -25 -30
Output Frequency (GHz)
Figure 1. Output Power vs. Output Freq. @ Pin=+3dBm
Suppression [1H] (dBc)
Output Power [2H] (dBm)
12
14 16 18 20 22 Output Frequency (GHz)
24
26
15
17 16 15 14 13 Pin=-2dBm Pin= 0dBm Pin=+2dBm Pin=+4dBm
12 11 8
10
12
14 16 18 20 Output Frequency (GHz)
22
24
-5
150 Total Drain Current [Id] (mA)
160
-10 -15 -20
-30
S11 S22
4
6
8
10
12
14 16 18 Frequncy (GHz)
Figure 5. Input and Output Return Loss
20
22
25 30
Pin=-2dBm Pin= 0dBm Pin=+2dBm Pin=+4dBm
35
8
10
12
14 16 18 20 Output Frequency [GHz]
22
24
Figure 4. Fundamental Suppression at variable Pin
0
-25
20
40
26
Figure 3. Output Power [2H] vs. Output Freq. at variable Pin
I/P & O/P Return Loss (dB)
10
10
18
8
Figure 2. Output Power vs. Output Freq. over temp @ Pin=+3dBm
19
10
-40˚C [2H] +25˚C [2H] +85˚C [2H] -40˚C [1H] +25˚C [1H] +85˚C [1H]
24
26
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
140 130 120 110 100 90 80 -11
-9
-7
-5
-3 -1 1 3 5 Input Power [1H] (dBm)
Figure 6. Variation of total drain current with input power
7
9
11
26
20
20
18
Fout=8GHz
14 12 10 8 6
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
4 2 0 -11
-9
-7
-5 -3 -1 1 3 Input Power [1H] (dBm)
5
7
9
Suppression [1H] (dBc)
Output Power [2H] (dBm)
14 12 10 8 6 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
4 2 -9
-7
Fout=8GHz
40
-9
-7
-5
-5
-3 -1 1 3 5 Input Power [1H] (dBm)
7
9
35 Fout=10GHz
40
-9
-7
-5 -3 -1 1 3 5 Input Power [1H] (dBm)
Fout=14GHz
Suppression [1H] (dBc)
Output Power [2H] (dBm)
7
9
11
10
12 10 8 6
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
-9
-7
-5 -3 -1 1 3 5 Input Power [1H] (dBm)
Figure 11. 2H Output Power Vs Input Power @ Fout=14GHz
11
30
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
18
4 2 0 -11
9
Figure 10. Fundamental Supp. Vs Input Power @ Fout=10GHz
20
14
7
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
25
45 -11
11
Figure 9. 2H Output Power Vs Input Power @ Fout=10GHz
16
-3 -1 1 3 5 Input Power [1H] (dBm)
20
16
0 -11
35
Figure 8. Fundamental Supp. Vs Input Power @ Fout=8GHz
Fout=10GHz
18
30
45 -11
11
Figure 7. 2H Output Power Vs Input Power @ Fout=8GHz
20
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
25 Suppression [1H] (dBc)
Output Power [2H] (dBm)
16
7
9
11
15 20 25 30
Fout=14GHz
35 -11
-9
-7
-5
-3 -1 1 3 5 Input Power [1H] (dBm)
7
Figure 12. Fundamental Supp. Vs Input Power @ Fout=14GHz
9
11
10
20 18 Suppression [1H] (dBc)
Output Power [2H] (dBm)
16 14 12
Fout=16GHz
10 8 6
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
4 2 0 -11
-9
-7
-5
-3 -1 1 3 5 Input Power [1H] (dBm)
7
9
20
Suppression [1H] (dBc)
Output Power [2H] (dBm)
14 12 10 8
Fout=20GHz
6 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
4 2 -9
-7
-5
-3 -1 1 3 5 Input Power [1H] (dBm)
7
9
-7
-5 -3 -1 1 3 Input Power [1H] (dBm)
5
7
9
11
10 15 20 25
5
18 16
10 Suppression [1H] (dBc)
14 12 Fout=22GHz
6
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
4 2 -9
-7
-5
-3 -1 1 3 5 Input Power [1H] (dBm)
Figure 17. 2H Output Power Vs Input Power @ Fout=22GHz
-9
-7
-5
-3 -1 1 3 5 Input Power [1H] (dBm)
7
9
11
Figure 16. Fundamental Supp. Vs Input Power @ Fout=20GHz
20
10 8
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
30 35 -11
11
Figure 15. 2H Output Power Vs Input Power @ Fout=20GHz
Output Power [2H] (dBm)
-9
Fout=20GHz
16
0 -11
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
30
5
18
25
Figure 14. Fundamental Supp. Vs Input Power @ Fout=16GHz
Figure 13. 2H Output Power Vs Input Power @ Fout=16GHz
0 -11
20
35 -11
11
Fout=16GH
15
7
9
11
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
15 20 25 Fout=22GHz 30 35 -11
-9
-7
-5 -3 -1 1 3 5 Input Power [1H] (dBm)
7
Figure 18. Fundamental Supp. Vs Input Power @ Fout=22GHz
9
11
5 Fout=26GHz Vd=4.5V, Vg=-1.2V
Fout=26GHz Suppression [1H] (-dBc)
Output Power [2H] (dBm)
20 18 16 14 12 10 8 6 4 2 0
Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V -11 -9
-7
-5
-3
-1
1
3
5
7
9
11
Input Power [1H] (dBm)
SSB Phase Noise (dBc/Hz)
Figure. 19 2H Output Power Vs Input Power @ Fout=26GHz -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 1.E+02
10 15 20 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V
25 30 35 -11
-9
-7
-5
-3 -1 1 3 5 Input Power [1H] (dBm)
7
9
11
Figure. 20 Fundamental Supp. Vs Input Power @ Fout=26GHz
Fout=15.6GHz
F1 M/N @ fo
Active Balun
S
Filter @ 2fo
Amp
F2
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Offset Frequency [Hz]
Figure.21 SSB Phase Noise of frequency doubler (Pin=+2dBm, fout=15.6GHz)
Figure 22. Top Level Schematic of Frequency doubler
Biasing and Operation The frequency doubler MMIC consists of a balun. The outputs of this balun feed the gates of balanced FETs and the drains are connected to form the single-ended output. This results in fundamental frequency & odd harmonics cancellation. The even harmonic drain currents are in phase and thus add in phase. The input matching network (M/N) is designed to provide good match at fundamental frequencies and produces high impedance mismatch to higher harmonics. The AMMP-6120 is biased with a single positive drain supply Vdd and a single negative gate supply using separate bypass capacitors. It is normally biased with the drain supply connected to Vd and the gate supply connected to Vg. For most applications it is recommended to use a Vg =-1.2V to -1.4V and Vd=4.5V to 5.0V. The RF input and output ports are AC coupled thus no DC voltage is present at either port. The ground connection is made via the package base.”
The AMMP-6120 performance changes with Drain Voltage (Vd) and Gate bias (Vg) as shown in the previous graphs. Improvements in output power or fundamental suppression performance are possible by optimizing the Vg from -1.2V to -1.4V and/or Vd from 4.5 to 5.0V. A simplified schematic of the frequency multiplier is shown in figure 22. The active balun circuit and the output amplifier of the circuit are self biased. The Vg negative bias (below pinch off ) is only applied to FETs ‘F1’ and ‘F2’. FETs ‘F1’ and ‘F2’ have no significant contribution to total drain current therefore Vg cannot be used to set drain current. It should only be used to optimize the output power and fundamental & higher harmonics suppression of the doubler. Refer to the Absolute Maximum Ratings table for allowed DC and thermal conditions.
Outline Drawing 1
A
8
Recommended SMT Attachment 2
The AMMP Packaged Devices are compatible with high volume surface mount PCB assembly processes.
3
AMMP XXXX YWWDNN 7
3
The PCB material and mounting pattern, as defined in the data sheet, optimizes RF performance and is strongly recommended. An electronic drawing of the land pattern is available from www.Avago.com/view/rf or upon request from Avago Application Engineering.
4
5
B
A Front View
Side View
Evaluation Test Circuit (Demo Board)
Symbol
Min
Max
A
0.198 (5.03)
0.213 (5.4)
B
0.0685 (1.74)
0.088 (2.25)
(Available to customer on qualified request)
Dimensions are in inches (mm) .011 [0.28] .018 [0.46]
.114 [2.9] .014 [0.365] 3 2
1 .016 [0.40]
.126 [3.2] .059 [1.5]
4
8
.100 [2.54]
.012 [0.30]
.029 [0.75] .100 [2.54]
5
6
7 .028 [0.70]
.016 [0.40] .093 [2.36] Back View
Dimensional Tolerance for back view: 0.002” (0.05mm) Notes: 1. * Indicates Pin 1 2. Dimensions are in inches [millimeters] 3. All Grounds must be soldered to PCB RF Ground
Suggested PCB Material and Land Pattern 0.093 (2.36) 0.010 (0.25) 0.011 (0.28)
0.016(0.40) 0.0095 (0.24)
0.126 0.059 0.020 (3.20) (1.50) (0.50)
0.016 (0.40) 0.012 (0.30) GROUND VIAS SHOULD BE SOLDER FILLED
0.018 (0.46) 0.018 (0.46) 0.114 (2.90) INCHES (MILLIMETERS). MATERIAL IS ROGERS RO4350, 0.010-INCH THICK.
0.0095 (0.024)
Manual Assembly
Stencil Design Guidelines
1. Follow ESD precautions while handling packages.
A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown in Figure 24. The stencil has a solder paste deposition opening approximately 70% to 90% of the PCB pad. Reducing stencil opening can potentially generate more voids underneath. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads. Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use a laser cut stencil composed of 0.127 mm (5 mils) thick stainless steel which is capable of producing the required fine stencil outline.
2. Handling should be along the edges with tweezers. 3. Recommended attachment is conductive solder paste. Please see recommended solder reflow profile. Conductive epoxy is not recommended. Hand soldering is not recommended. 4. Apply solder paste using a stencil printer or dot placement. The volume of solder paste will be dependent on PCB and component layout and should be controlled to ensure consistent mechanical and electrical performance. 5. Follow solder paste and vendor’s recommendations when developing a solder reflow profile. A standard profile will have a steady ramp up from room temperature to the pre-heat temperature to avoid damage due to thermal shock.
The combined PCB and stencil layout is shown in below.
6. Packages have been qualified to withstand a peak temperature of 260°C for 20 seconds. Verify that the profile will not expose device beyond these limits.
0.70 0.60
Solder Reflow Profile The most commonly used solder reflow method is accomplished in a belt furnace using convection heat transfer. The suggested reflow profile for automated reflow processes is shown in Figure 23. This profile is designed to ensure reliable finished joints. However, the profile indicated in Figure 1 will vary among different solder pastes from different manufacturers and is shown here for reference only.
0.9550
1.60 0.95
0.36 0.36
0.36 0.40 4x - R0.14
Recommended solder reflow profile 300
0.27
1.80
Figure 24. Stencil outline drawing (mm).
Peak = 250˚C
250
Temp (˚C)
Melting point = 218˚C
0.40
200
0.46
150
0.60
0.67
100 0.36 0.40
50 0
Ramp 1 Preheat 0
50
Ramp 2
100
Reflow
150
200
Cooling 250
300
Seconds
3.20 1.80 0.40
0.27
0.36
Figure 23. Suggested lead-free reflow profile for SnAgCu solder paste.
0.30 1.60
2.90
Figure 25. Combined PCB and stencil layouts (mm).
Stencil Opening
AMMP-6120 Part Number Ordering Information Part Number
Devices Per Container
Container
AMMP-6120-BLK
10
Antistatic bag
AMMP-6120-TR1
100
7” Reel
AMMP-6120-TR2
500
7” Reel
Device Orientation (Top View) 4mm
12mm
• AMMP XXXX
• AMMP XXXX
• AMMP XXXX
Carrier Tape and Pocket Dimensions
Notes: 1. Ao & Bo measure at 0.3mm above base of pocket 2. 10 pitches cumulative tol. ±0.2mm
For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0119EN AV02-0441EN - May 16, 2007
