Datasheet For 2gsplus Adc By Iaf Gmbh

Transcript

IAF GmbH Phone: ++49 531 379 88-0 Berliner Straße 52j Fax: ++49 531 37988-30 38104 Braunschweig e-mail: [email protected] Germany www.iaf-bs.de 2GSPlus-ADC-Board (Rev. 1.0) (Data Sheet Rev. 1.0 October 2009) 1. Overview The 2GSPlus-ADC-Board is designed for A/D conversion from 1GSamples up to 3GSamples. The board includes four National Semiconductor A/D converter chips ADC08300 and a Xilinx CPLD chip XC2C512 for configuration and control of the connected analog RF circuits. The complete clock generation and power supply is integrated on board (see Figure 2). The 2GSPlus-ADC-Board is designed to works with FPGA board FFP Basic+, but it also can operate standalone. The Xilinx CPLD chip can either be configured directly via JTAG-Interface. This data sheet describes the hardware and function of the 2GSPlus-ADC-Board. Figure 1. 2GSPlus-ADC-Board. 2GSPlus-ADC-Board (Rev. 1.0) Page 1 of 4 2GSPlus-ADC-Board Rev.1 Overview to FFP Basic Plus Board or to another Hardware J8 J9 J13 8xLVDS 8xLVDS 8xLVDS Clk_Out Ext. Clk Ref. Clk 8xLVDS Connector ADC3_CLK 8xLVDS J7 ADC1_CLK 8xLVDS 8xLVDS 8xLVDS to FFP Basic Plus Board or to another Hardware J12 Connector J1 J3 ADC1_IN ADC1 ADC083000 Config Config PLL & Clock Distribution ADC1_CLK ADC3_CLK ADC4_CLK DIP(3:0) ADC2_IN ADC2 ADC083000 ADC4 ADC083000 ADC4_IN DIP Switch J4 CPLD XC2C512 Config ADC3_IN Config ADC2_CLK J2 ADC3 ADC083000 Config Reset Power Connector J10 8xLVDS Connector to FFP Basic Plus Board or to another Hardware +5V JTAG Connector J11 8xLVDS Oscillator 8xLVDS SW1 Power Supply +1.8V ADC4_CLK +1.9V 8xLVDS 8xLVDS 8xLVDS 8xLVDS 8xLVDS J15 ADC1_CLK +3.3V Connector J14 to FFP Basic Plus Board or to another Hardware Figure 2: Overview 2. Power Section. The 2GSPlus-ADC-Board includes the complete power generation on board and needs only +5V voltage input. The supply voltage is generated with linear voltage regulators (see Figure 2). The input voltage can be on two ways provided to board: from connector J10 or from power pins of connectors J12, J13 ,J14 and J15. The last case is recommended to use with FFP-Plus board. Figure 3: Power Section 2GSPlus-ADC-Board (Rev. 1.0) Page 2 of 4 3. PLL and clock distribution. The board includes the complete clock generation and distribution. The PLL can generate clocks in range from 500MHz to 2.725GHz. The output frequency range depends on the onboard placed chip (see Table1 and ADF4360-x datasheet). The AD4360-x works with input reference clock from 10 to 250MHz. The LED4 indicated PLL is locked. The SY5802U works as clock distributor and SY8987 as clock divider for FPGA clock. The PLL is programmable from CPLD via SPI interface (see Table2). Figure 4: Clock generation and distribution. Chip ADF4360-0 ADF4360-1 ADF4360-2 ADF4360-3 ADF4360-4 ADF4360-5 ADF4360-6 Frequency range 2400-2725MHz 2050-2450MHz 1850-2150MHz 1600-1950MHz 1450-1750MHz 1200-1400MHz 1050-1250MHz Table 1: Frequency range. 2GSPlus-ADC-Board (Rev. 1.0) Page 3 of 4 4. DC-Specification: Power Supply Voltage Range Min Typ Max +4,5 V +5 V +5,5 V Power Supply Current 5.1A 5. AC-Specification. Min Typ Max Reference input frequency range 10 MHz - 250MHz Analog input range - - 870mVpp/50Ohm 97mm 6. Board Dimensions. 123mm 2GSPlus-ADC-Board (Rev. 1.0) Page 4 of 4