Transcript
TMS320VC5502 EVM Technical Reference
2003
DSP Development Systems
TMS320VC5502 EVM Technical Reference
506665-0001 Rev. A May 2003
SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310
[email protected] www.spectrumdigital.com
IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference.
Copyright © 2003 Spectrum Digital, Inc.
Contents
1
Introduction to the TMS320VC5502 EVM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides you with a description of the TMS320VC5502 EVM Module, key features, and block diagram. 1.1 Key Features .......................................................... 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Power Supply ......................................................... 2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the operation of the major board components on the TMS320VC5502 EVM. 2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 CPLD Overview .................................................... 2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 USER_REG Register .............................................. 2.1.4 DC_REG Register .................................................. 2.1.5 Version Register .................................................. 2.1.6 MISC Register ..................................................... 2.1.7 LCD Interface ..................................................... 2.1.8 VC5502 EVM Interface Register ..................................... 2.2 AIC23 Codec ..................................................... 2.3 Sychronous Memory ............................................... 2.4 Flash ROM Interface ............................................... 2.5 SBRAM Memory ................................................ 2.6 LEDs and DIP Switches ............................................. 2.7 Daughter Card Interface ............................................. 3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the physical layout of the TMS320VC5502 EVM and its connectors. 3.1 TMS320VC5502 EVM Board Layout ..................................... 3.1.1 Keypad/display Module Layout ........................................ 3.2 Connector Index .................................................... 3.3 Expansion Connectors ................................................ 3.3.1 P1, Memory Expansion ............................................. 3.3.2 P2, Peripheral Expansion ............................................ 3.3.3 P3, HPI Expansion Connector ........................................ 3.4 Audio Connectors ..................................................... 3.4.1 J1, Microphone Connector ........................................... 3.4.2 J2, Audio Line In Connector .......................................... 3.4.3 J3, Audio Line Out Connector ........................................ 3.4.4 J4, Headphone Connector ............................................
1-1
1-2 1-3 1-4 1-5 1-6 1-8 2-1 2-2 2-2 2-3 2-4 2-4 2-5 2-5 2-7 2-8 2-9 2-10 2-10 2-10 2-10 2-11 3-1 3-2 3-3 3-4 3-4 3-5 3-6 3-7 3-8 3-8 3-8 3-9 3-9
A
B
3.5 Power Connectors .................................................... 3.5.1 J5, +5V Main Power Connector ...................................... 3.5.2 J6, Alternate Power Connector ........................................ 3.6. Miscellaneous Connectors ........................................... 3.6.1 J8, RS-232 Connector .............................................. 3.6.2 J7, External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 JP1, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 System LEDs ....................................................... 3.8 Reset Circuitry ..................................................... Schematics .............................................................. Contains the schematics for the TMS320VC5502 EVM and Keypad/display Module A.1 TMS320VC5502 EVM Schematics ..................................... A.2 Keypad/display Module Schematics .................................... Mechanical Information .................................................. Contains the mechanical information about the TMS320VC5502 EVM and Keypad/display Module B.1 TMS320VC5502 EVM Mechanical Information ........................... B.2 Keypad/display Module Mechanical Information ...........................
3-10 3-10 3-10 3-11 3-11 3-11 3-12 3-12 3-12 A-1 A-2 A-23 B-1
B-2 B-3
About This Manual This document describes the board level operations of the TMS320VC5502 Evaluation Module (EVM). The EVM is based on the Texas Instruments TMS320VC5502 Digital Signal Processor. The TMS320VC5502 EVM is a table top card to allow engineers and software developers to evaluate certain characteristics of the TMS320VC5502 DSP to determine if the processor meets the designers application requirements. Evaluators can create software to execute onboard or expand the system in a variety of ways. Notational Conventions
This document uses the following conventions. The TMS320VC5502 will sometimes be referred to as the C55XX. The TMS320VC5502 EVM will sometimes be referred to as the EVM. Program listings, program examples, and interactive displays are shown is a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;
Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents Texas Instruments TMS320VC55XX DSP CPU Reference Guide Texas Instruments TMS320VC55XX DSP Peripherals Reference Guide
Table 1: Hardware History Revision A
History Alpha Release
Table 2: Manual History Revision A
History Alpha Release
Chapter 1 Introduction to the TMS320VC5502 EVM
Chapter One provides a description of the TMS320VC5502 EVM along with the key features and a block diagram of the circuit board.
Topic 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Page Key Features Functional Overview Display/Keypad Overview Basic Operation Memory Map Jumper Settings Emif Clock Select Power Supply
1-2 1-3 1-4 1-4 1-5 1-6 1-7 1-8
1-1
Spectrum Digital, Inc 1.0 Key Features
HP OUT
Display Interface McBSPs
Voltage Reg
5502 DSP
Ext. JTAG
HPI
Peripheral Exp
PWR
EMIFCLK GPIO7 GPIO2 GPIO1 GPIO0
JP2 +5V
Host Port Int
JP3 +1.2V +3.3V
SDRAM SBRAM
MUX
Memory Exp EMIF CPLD
AIC23 Codec
Flash
LINE OUT
MIC IN
LINE IN
The 5502 EVM is a standalone development platform that enables users to evaluate and develop applications for the TI C55XX DSP family. The EVM also serves as a hardware reference design for the TMS320VC5502 DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market.
LED
DIP
0123
0123
Figure 1-1, Block Diagram VC5502 EVM The EVM comes with a full compliment of on-board devices that suit a wide variety of application environments. Key features include: • A Texas Instruments 5502 DSP operating at 300MHz • An TLC320AIC23 stereo codec • 8 Mbytes of synchronous DRAM • 1 Mbyte of synchronous Burst RAM • 512 Kbytes of non-volatile Flash memory • I2C and SPI serial ROMs • RS-232 UART • 4 user accessible LEDs and DIP switches • Software board configuration through registers implemented in CPLD 1-2
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc • 128 LCD display and keypad • Jumper selectable boot options • Standard expansion connectors for daughter card use • JTAG emulation via external emulator • Single voltage power supply (+5V) 1.2 Functional Overview of the TMS320VC5502 EVM The DSP interfaces to external SDRAM, SBRAM, Flash memory and an expansion memory interface connector through its 32-bit External Memory Interface (EMIF). The SDRAM accesses are in 32-bit mode in chip enable 0 memory space. The EMIF provides the necessary refresh signals. The Flash accesses are in 16-bit asynchronous mode in the bottom half of chip enable 1 space. The SBRAM is accessed on chip enable 3 if it is not routed to the expansion connector via the CPLD control register. The EMIF signals are brought out to the daughter card expansion connectors which use chip enables 2 and 3. An on-board AIC23 codec allows the DSP to transmit and receive analog signals. The I2C bus is used for the codec control interface and McBSP1 is used for data. Analog I/O is done through four 3.5mm audio jacks that correspond to microphone input, line input, line output and headphone output. The codec input is software selectable between the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP1 can be re-routed to the expansion connectors in software. A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to the CPLD registers. The registers reside in the upper half of chip enable 1. The EVM includes 4 LEDs and 4 position DIP switch as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers. A separate Keypad/LCD display card is interfaced via CPLD registers and I2C addresses An included 5V external power supply is used to power the board. On-board voltage regulators provide the +1.3V DSP core voltage, +3.3V digital and +3.3V analog voltages. Voltage supervisors integrated into the regulators monitor voltage regulation, and will hold the board in reset until the supplies are within operating specifications and the reset button is released.
1-3
Spectrum Digital, Inc 1.3 Display/Keypad Overview The universal display/keypad module interfaces to the EVM via a 16 pin 2mm. ribbon cable. The display module features a 128 x 64 LCD, 4 I2C A/D converters, 2 potentiometers, 9 user keys, and a jog wheel. All switches are accessed via the I2C A/Ds, while the display is accessed via an SPI interface generated internally in the CPLD Figure 1-2 below shows a block diagram of the display/keypad module.
EVM I2C
CPLD SPI
POT
POT
A/D
A/D
JOG WHEEL
A/D
SWITCHES
A/D
DISPLAY
Universal Display
Figure 1-2, BLOCK DIAGRAM OF DISPLAY/KEYPAD
1.4 Basic Operation The EVM is designed to work with TI’s Code Composer Studio development environment and is available in an optional package with the board. Code Composer communicates with the board through the JTAG emulator. To start, follow the instructions in the emulator’s Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation and drivers.
1-4
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 1.5 Memory Map The C55x family of DSPs has a unified program and data space with a separate distinct I/O space dedicated to on-chip peripheral registers. For a number of reasons (historical and technical) though, program code is addressable in 8-bit bytes while data is addressable in 16-bit words. Both programs and data can reside anywhere in the unified memory space. The address reach of the 5502 is 24 bits for a total of 16 megabytes (8 bits/byte) or alternatively 8 megawords (16 bits/word). The external memory interface controller (EMIF) divides the address space into 4 equally sized chip enable (CE) spaces when dealing with external memory. The lower 20 address bits are driven on the EMIF as address lines while the top 2 are decoded and driven as the chip enable for that particular region. Word Address
C5502 Family Memory Type
0x000000
Memory Mapped Registers
MMR
0x000030
Internal Memory (DARAM)
Internal Memory
5502 EVM
0x008000
0x008000 External CE0 0x200000 0x400000 0x600000
External CE1 External CE2 External CE3
SDRAM Flash CPLD Daughter Card SBRAM or Daughter Card
0x200000 0x380000 0x400000 0x600000
Figure 1-2, Memory Map, VC5502 EVM The figure above shows a generic memory space map for a C55x family processor and a second map specific to the components on a 5502 EVM. The SDRAM occupies chip enable 0. The Flash and memory mapped registers of the CPLD share CE1 with the Flash in the top half and the CPLD in the bottom half. CE2 is used for expansion daughter card access and CE3 is optionally mapped into SBRAM or expansion connector access.
1-5
Spectrum Digital, Inc Internal memory on the 5502 starts at address 0 and takes precedence over any external memory. The DSP’s memory mapped registers occupy the first few bytes of the address space, followed by internal DARAM. DARAM stands for Dual-Access RAM and allows two concurrent memory operations to be performed on the same block. Internal memory is divided into 4Kword blocks, each capable of supporting independent operations. Performance can be optimized by placing code and data so that instructions have their operands spread to different blocks so no stalls are introduced due to contention for one specific block. There are 8 DARAM blocks on a 5502 for a total of 32Kwords of internal memory.
1.6 Jumper Settings
EMIFCLKS GPIO7 GPIO2 GPIO1 GPIO0
The 5502 EVM has 5 on-board CPU configuration jumpers that define the DSP’s boot configuration and reset state. The figure below shows these jumpers.
Figure 1-3, JP4, DSP Boot Configuration - Default Setting The jumpers drive signals that directly correspond to the input on one of the DSP’s configuration pins. If the jumper is on, the signal is driven to a logic 0. If the jumper is off, the signal is driven to a logic 1. The 5502 has a number of boot modes that are selected at reset by sampling the GPIO[2-0] pins. These pins are also referred to as BOOTM[2-0]. These pins can be configured with the on-board jumpers. The 5502 can boot from asynchronous memory mapped in CE1 (Flash on the 5502 EVM board), serial EEPROM’s connected to McBSP0, I2C EEPROM, UART, or a standard serial port on McBSP0. To boot from a particular device such as Flash, I2C EEPROM, or SPI EEPROM you must pack the object code into a C55x bootloader formatted table and store it in the device. When you set the appropriate BOOTM jumpers and power cycle the board, the 5502 will parse the bootloader table, load the code into memory and begin execution at the entry point specified in the bootloader table.
1-6
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc The bootloader functionality is contained in on-chip ROM. At reset, the 5502 usually begins execution from the ROM and runs the appropriate bootloader based on the BOOTM pins. In the special case where BOOTM[2:0] are all 0, the internal ROM is not active and execution will begin from external memory at the reset vector (0xFFFF00). Table 1: VC5502 EVM Boot Load Options BOOTM[2:0]
BOOT PROCESS
EXECUTION START BYTE ADDRESS AFTER BOOT IS COMPLETE
000
No Boot - 16 Bit Asynch
FFFF00h (reset vector)
001
Serial SPI EPROM boot from McBSP0 supporting 24 bit addressing
Destination specified in the boot table
010
Standard Serial Boot McBSP0 (16 bit)
011 *
Parallel 16 bit EMIF
Flash CE1
010
No Boot - 32 Bit Asynch
0xFFFF00 (Reset vector)
101
HPI Boot
110
I2C Boot
Destination specified in boot table
111
UART Boot
Destination specified in downloaded boot format
Note: Jumper On = Logical 0 Jumper Off = Logical 1
* Default Boot Load Option for EVM
1.7 EMIF Clock Select The VC5502 has the option of using a separate clock to operate the external memory interface. This clock is input on the CLKIN pin and is selected at reset by the EMIFCLKS pin. The EVM provides a configuration jumper to select either the internal PLL generated clock or the external PLL generated clock which is driven into the ECLKIN pin. When EMIFCLKS is high ECLKIN is selected for EMIF output clock. When EMIFCLKS is low the internal PLL clock is selected.
1-7
Spectrum Digital, Inc 1.8 Power Supply The EVM operates from a single +5V external power supply connected to the main power input (J5). Internally, the +5V input is converted into +1.3V and +3.3V using Texas Instruments voltage regulators. The +1.3V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffers and all other chips on the board. The power connector is a 2.5mm barrel-type plug. There are two power test points on the EVM at JP2 and JP3. All board current passes through JP2 (the +5V supply). All DSP core current passes through JP3. Normally these jumpers are both closed. To measure the current passing through remove the jumpers and connect the pins with a current measuring device. The EVM also provides a separate +3.3V, 1A supply for the daughter card. The +3.3V supply is derived from the +5V power source with a separate linear regulator. It is also possible to provide the daughter card with +12V and -12V when the optional external power connector is used.
1-8
TMS320VC5502 EVM Module Technical Reference
Chapter 2 Board Components
This chapter describes the operation of the major board components on the TMS320VC5502 EVM.
Topic 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.2 2.3 2.4 2.5 2.6 2.7
Page CPLD (Programmable Logic) CPLD Overview CPLD Registers USER_REG Register DC_REG Register Version Register MISC Register LCD Interface VC5502 EVM Interface Register AIC23 Codec Sychronous DRAM Flash Memory SBRAM Memory LEDs and DIP Switches Daughter Card Interface
2-2 2-2 2-3 2-4 2-4 2-5 2-5 2-7 2-8 2-9 2-10 2-10 2-10 2-10 2-11
2-1
Spectrum Digital, Inc 2.1 CPLD (Programmable Logic) The VC5502 EVM uses an Altera EPM3128TC100-10 Complex Programmable Logic Device (CPLD) device to implement: • Memory-mapped control/status registers that allow software control of various board features. • Address decode and memory access logic. • Control of the daughter card interface and signals. • SPI for LCD serial interface. • Assorted "glue" logic that ties the board components together.
2.1.1 CPLD Overview The CPLD logic is used to implement functionality specific to the EVM. Your own hardware designs will likely implement a completely different set of functions or take advantage of the DSPs high level of integration for system design and avoid the use of external logic completely. The EMIF on the 5502 can support several heterogeneous memory types with a glueless interface. However, to reserve CE2 and CE3 for potential daughter-card use on the EVM, CE1 is split to include the Flash in its bottom half and the CPLD memory-mapped registers in its top half. The address decode logic is used to implement the split. The CPLD implements simple random logic functions that eliminate the need for additional discrete devices. In particular, the CPLD aggregates the various reset signals coming from the reset button and power supervisors and generates a global reset. The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the EVM). The CPLD source files are written in the industry standard VHDL (Hardware Design Language) and are included with the EVM on the installation CD-ROM.
2-2
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 2.1.2 CPLD Registers The multiple CPLD memory-mapped registers allows users to control CPLD functions in software. On the 5502 EVM the registers are primarily used to access the LEDs and DIP switches, provide LCD interface, and control the daughter card interface. The registers are mapped into the EMIF data space at word address 0x380000, in the upper portion of CE1. They appear as 16-bit registers with a simple 16-bit asynchronous memory interface, although only the lower 8-bits are valid. The following table gives a high level overview of the CPLD registers and their bit fields: The table below shows the bit definitions for the 7 registers in CPLD. Table 1: CPLD Register Definitions Offset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
USER_REG
USR_SW3 R
USR_SW2 R
USR_SW1 R
USR_SW0 R
USR_LED3 R/W 0(Off)
USR_LED2 R/W 0(Off)
USR_LED1 R/W 0(Off)
USR_LED0 R/W 0(Off)
1
DC_REG
DC_DET R
TIN0 DIR R/W 0(Low)
DC_STAT1 R
DC_STAT0 R
DC_RST R 0(No reset)
0
DC_CNTL1 R/W 0(low)
DC_CNTL0 R/W 0(low)
2
Reserved
3
Reserved
4
VERSION
5
Reserved
6
MISC
CPLD_VER[3.0] R
0
BOARD VERSION[2.0] R
McBSP0 On/Off R/W 0 (Onboard)
VCORE ON R/W 0
VCORE STATUS R
VCORE MONOTOR R/W 0
TIN1 IN/OUT R/W (0 INPUT)
TIN0 IN/OUT R/W (0 INPUT)
McBSP2 ON/OFF Board R/W 0 (Onboard)
McBSP1 ON/OFF Board R/W 0 (Onboard)
7
Reserved
8
LCD_REG0
SHIFT DATA7
SHIFT DATA6
SHIFT DATA5
SHIFT DATA4
SHIFT DATA3
SHIFT DATA2
SHIFT DATA1
SHIFT DATA0
9
LCD_REG1
SHIFT DATA7
SHIFT DATA6
SHIFT DATA5
SHIFT DATA4
SHIFT DATA3
SHIFT DATA2
SHIFT DATA1
SHIFT DATA0
A
BOARD
LCD Busy R 1 BUSY
LCD Reset R/W 0
Reserved R
Reserved R
SBRAM Disable R/W (0 Enabled)
Expansion I2 C R/W (0 Off)
EMIF Clock R/W (0-ECLK0)
EMIF Clock Status R
2-3
Spectrum Digital, Inc 2.1.3 USER_REG Register USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or off to allow the user to interact with the EVM. The DIP switches are read by reading the top 4 bits of the register and the LEDs are set by writing to the low 4 bits. Table 2: CPLD USER_REG Register Bit
Name
R/W
Description
7
USER_SW3
R
User DIP Switch 3(1 = Off, 0 = On)
6
USER_SW2
R
User DIP Switch 2(1 = Off, 0 = On)
5
USER_SW1
R
User DIP Switch 1(1 = Off, 0 = On)
4
USER_SW0
R
User DIP Switch 0(1 = Off, 0 = On)
3
USER_LED3
R/W
User-defined LED 3 Control (0 = Off, 1 = On)
2
USER_LED2
R/W
User-defined LED 2 Control (0 = Off, 1 = On)
1
USER_LED1
R/W
User-defined LED 1 Control (0 = Off, 1 = On)
0
USER_LED0
R/W
User-defined LED 0 Control (0 = Off, 1 = On)
2.1.4 DC_REG Register DC_REG is used to monitor and control the daughter card interface. DC_DET detects the presence of a daughter card. DC_STAT and DC_CNTL provide simple communications with the daughter card through readable status lines and writable control lines. The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset. Table 3: DC_REG Register
2-4
Bit
Name
R/W
Description
7
DC_DET
R
Daughter Card Detect (1= Board detected)
6
0
R
Always 0
5
DC_STAT1
R
Daughter Card Status 1 (0=Low, 1 = High)
4
DC_STAT0
R
Daughter Card Status 0 (0=Low, 1 = High)
3
DC_RST
R/W
2
0
R
1
DC_CNTL1
R/W
Daughter Card Control 1(0 = Low, 1 = High)
0
DC_CNTL0
R/W
Daughter Card Control 0(0 = Low, 1 = High)
Daughter Card Reset (0=No Reset, 1 = Reset) Always zero
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 2.1.5 VERSION Register The VERSION register contains two read only fields that indicate the BOARD and CPLD versions. This register will allow your software to differentiate between production releases of the EVM and account for any variances. This register is not expected to change often, if at all. Table 4: Version Register Bit Definitions Bit #
Name
R/W
Description
7
CPLD_VER3
R
Most Significant CPLD Version Bit
6
CPLD_VER2
R
CPLD Version Bit
5
CPLD_VER1
R
CPLD Version Bit
4
CPLD_VER0
R
Least Significant CPLD Version Bit
3
0
R
Always 0
2
EVM_VER2
R
Most Significant EVM Board Version Bit
1
EVM_VER1
R
EVM Board Version Bit
0
EVM_VER0
R
Least Significant EVM Board Version Bit
2.1.6 MISC Register The MISC register is used to provide software control for miscellaneous board functions. On the 5502 EVM, the MISC register controls how auxiliary signals are brought out to the daughter-card connectors. The TIN0 and TIN1 bits are used to select whether the DSP’s TIN0 and TIN1 (timer) signals are connected to the peripheral expansion connector as inputs or outputs. The expansion connector has separate pins for inputs and outputs so each signal must be routed to one of two physical pins. A 0 indicates that the signal should be connected to the input pin on the expansion connector. A 1 indicates that it should be connected to the output pin. The power supply logic monitors the core voltage for the DSP and supplies a power good signal that signifies that the core voltage is within an acceptable range. The power good signal can be read on the VCORE_STAT. If the signal is high, VCORE_STAT will read 1 indicating that the voltage is within range. A VCORE_STAT value of 0 indicates the voltage is outside of the normal operating range. The DSP reset circuit uses the power good signal as one of the many terms to hold the DSP in reset when power is first applied as well as when any unexpected voltage glitches are encountered. In certain circumstances (such as when transitioning back and forth between normal and low voltage mode) it is desirable to temporarily disable core voltage portion of the power monitor’s ability to reset the DSP. A VCORE_MON setting of 1 keeps the DSP from being reset when the core voltage changes. A VCORE_MON setting of 0 (default) leaves the reset capability enabled. 2-5
Spectrum Digital, Inc McBSP0SEL, McBSP1SEL and McBSP2SEL control the McBSP0, McBSP1 and McBSP2 respectively. Usually these ports are used to interface ports to the on-board AIC23 codec, the RS-232 UART driver, or SPI Serial ROM as examples. The power-on state of these bits (both 0s) represents that situation. Setting the corresponding bit to 1 enables the McBSP to the expansion daughter-card instead interface. Table 5: MISC Register Bit
Name
R/W
Description
7
McBSP0SEL0
R/W
6*
VCORE_SEL
R/W
McBSP0 on/off board (0 = on-board, 1 = off-board)
5
VCORE_STAT
R
4
VCORE_MON0
R/W
3
TIN1SEL
R/W
TIN1 in/out on daughter card (0 = input, 1 = output)
2
TINSEL0
R/W
TIN0 in/out on daughter card (0 = input, 1 = output)
1
MCBSP2SEL
R/W
McBSP2 on/off board (0 = on-board, 1 = off-board)
0
MCBSP1SEL
R/W
McBSP1 on/off board (0 = on-board, 1 = off-board)
Reserved Core power good indicator (0=power bad, 1= power good) Vcore voltage monitor disable (0=enabled, 1= disabled)
* Currently not implemented
2-6
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 2.1.7 LCD Interface The Liquid Crystal Display (LCD) is a write only interface. It is interfaced via an 8-bit shift register. Two locations are used when interfacing the LCD panel. Allowing the address bit of the interface to be directly programmed. The shift clock frequency is 5 megahertz. Writing register LCD0 sets the LCD address line A0 to 0. Writing register LCD1 sets the LCD address line A0 to 1. The write operation to either of these locations starts an internal shift register serializing the data into an 8-bit sequence to the displays. The shift clock frequency is 5 Mhz. The table below shows the relationship of the DSP data bits to the LCD data bits. Table 6: LCD Interface D7
D6
D5
D4
D3
D2
D1
D0
LCD D7
LCD D6
LCD D5
LCD D4
LCD D3
LCD D2
LCD D1
LCD D0
The figure below shows the LCD data transfer timing. the CPLD automatically generates this timing.
LCDCLK LCD Address LCD Data
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2-3, LCD Data Transfer Timing After any write operations the CPLD sets the LCD BUSY bit in the VC5502 EVM interface Register as the output is being serialized. The user should check this bit prior to starting another write operation. When LCD BUSY is high, the LCD shift register is busy, when is low the shift register is ready.
2-7
Spectrum Digital, Inc 2.1.8 VC5502 EVM Interface Register The VC5502 EVM Interface Register implements specific logic for the VC5502 EVM. The bits used in this register and their function are described in the table below. Table 7: VC5509 EVM Interface Register Bit
Name
R/W
Description
7
LCD Busy
R
6
LCD Reset
R/W
0 = removes reset from LCD, 1 = forces LCD into reset
5
Reserved
4
Reserved
3
SBRAM Disable
R/W
0 = SBRAM Enabled, 1 = SBRAM Disabled
2
I2C Expansion
R/W
0 = Disables I2C interface to expansion connector 1 = Enables I2C interface to expansion connector
1
EMIF ECLK01/ ECLK02
R/W
Configure ECLK01/ECLK02
EMIFCLKS
R
0
0 = busy, not ready, 1 = not busy, ready
EMIF_CLKS Pin State
LCD Busy indicates the status of the CPLD implemented shift register which interfaces to the LCD panel. A 1 logic level indicates the shift register is busy, A 0 logic level indicates the shift register is ready. LCD Reset allows the LCD Reset bit to be toggled under software control. A 1 logic level forces the LCD panel into reset. A 0 logic level removes the LCD reset to normal state. SBRAM Enable determines if Chip Enable 3 is used to interface to the on board SBRAM or the daughter card interface. The default (logic 0) is that the SBRAM is enabled. I2C Expansion bit enables/disables driving the I2C interface to the daughter card expansion bus. A 1 logic level enables the I2C bus to the daughter card interface. A 0 logic level disables the interface. Default state is disabled. EMIF CLOCK CONFIG determines if ECLK01 or ECLK02 is used to drive the EMIF clock. ECLK01 (0 logic level) is the default. Writing a logic 1 to this bit position selects ECLK2. EMIFCLKS is the state of the clock selection pin on the VC5502.
2-8
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 2.2 AIC23 Codec The EVM uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for input and output of audio signals. The codec samples analog signals on the microphone or line inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples back into analog signals on the line and headphone outputs so the user can hear the output. The codec communicates using two serial channels, one to control the codec’s internal configuration registers and one to send and receive digital audio samples. The I2C bus is used as the unidirectional control channel. The control channel is only used when configuring the codec, it is generally idle when audio data is being transmitted, McBSP1 is used as the bi-directional data channel. All audio data flows through the data channel. Many data formats are supported based on the three variables of sample width, clock signal source and serial data format. The EVM examples generally use a 16-bit sample width with the codec in master mode so it generates the frame sync and bit clocks at the correct sample rate without effort on the DSP side. The preferred serial format is DSP mode which is designed specifically to operate with the McBSP ports on TI DSPs. The codec has a 12MHz system clock. The 12MHz system clock corresponds to USB sample rate mode, named because many USB systems use a 12MHz clock and can use the same clock for both the codec and USB controller. The internal sample rate generate subdivides the 12MHz clock to generate common frequencies such as 48KHz, 44.1KHz and 8KHz. The sample rate is set by the codec’s SAMPLERATE register. The figure below shows the Coded interface on the VC5502 EVM.
AIC23 Codec
I2C
DR1 FSX1 CLKR1 CLKX1 FSR1 DX1
McBSP1 DSP Format
SCLK SDIN
DOUT LRCOUT BCLK LRCIN DIN
Control Registers
Digital
0 1 2 3 4 5 6 7 8 9 15
LEFINVOL RIGHTINVOL LEFTHPVOL RIGHTHPVOL ANAPATH DIGPATH POWER DOWN DIGIF SAMPLERATE DIGACT RESET
Analog MIC IN
LINE IN
LINE OUT MIC IN
ADC DAC
LINE IN LINE OUT HP OUT
HPOUT
Figure 2-1, TMS320VC5502 EVM CODEC INTERFACE
2-9
Spectrum Digital, Inc 2.3 Synchronous DRAM The EVM uses an industry standard 64 megabit Synchronous SDRAM. It uses a 32-bit interface and is used with up a maximum 100 MHz. memory clock. Since the DSP runs at 300 MHz, the EMIF must be programmed to use the SDRAM at a divider of the core clock rate or use the alternate EMIF Clock input. The SDRAM occupies chip enable 0. SDRAM must be constantly refreshed to maintain the integrity of its contents. This SDRAM must update one row every 15.6 microseconds to meet its minimum requirements. The EMIF can be programmed to automatically generate refresh signals based on this time period.
2.4 Flash Memory The EVM provides two devices each consisting of 256K x 16-bit words of external Flash memory. The board itself is pinned out to allow expansion to 1M 32 bit words. Typically the Flash is mapped into CE1 space because that is where the 16-bit asychronous bootloader looks for a boot image when booting from the Flash. Because the bootloader uses 16 bit mode usually only the Flash on D0-D15 is used. The CE1 space is shared by the CPLD and the Flash, but the CPLD timings are subsetted by the Flash so the Flash is the critical factor in configuring CE1. The Flash itself is a 70ns device but some additional delays are incurred in the CPLD logic that separates the Flash and CPLD registers. Because of this, the EMIF should be programmed for an access time of at least 80ns, and typically 100 ns.
2.5 SBRAM Memory The EVM has 1 megabyte of SBRAM in CE3 space. If the SBRAM is not used CE3 can be used for expansion daughter card accesses by disabling the secondary chip select on the SBRAM via the Board Register in the CPLD.
2.6 LEDs and DIP Switches The EVM includes 4 software accessible LEDs (DS1-DS4) and DIP switches (S2) that provide the user a simple form of input/output. Both are accessed through the CPLD USER_REG register.
2-10
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 2.7 Daughter Card Interface The EVM provides three expansion connectors that can be used to accept plug-in daughter cards. The daughter card allows users to build on their EVM platform to extend its capabilities and provide customer and application specific I/O. The expansion connectors are for memory, peripherals, and the Host Port Interface (HPI) The memory connector provides access to the DSP’s asynchronous EMIF signals to interface with memories and memory mapped devices. It supports byte addressing on 32 bit boundries. The peripheral connector brings out the DSP’s peripheral signals like McBSPs, timers, and clocks. Both connectors provide power and ground to the daughter card The HPI is a high speed interface that can be used to allow multiple DSPs to communicate and cooperate on a given task. The HPI connector brings out the HPI specific control signals as well as McBSP2. Most of the expansion connector signals are buffered so that the daughter card cannot directly influence the operation of the EVM board. The use of TI low voltage, 5V tolerant buffers, and CBT interface devices allows the use of either +5V or +3.3V devices to be used on the daughter card. Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET and DC_DET exist and are accessible through the CPLD DC_REG register. The EVM also multiplexes the Mc_BSP0, McBSP1, and McBSP2 of on-board or external use. This function is controlled through the CPLD MISC register. The timer signals on the peripheral expansion connector have connections for both inputs and outputs. since the VC5502 does not have separate timer inputs and outputs, the CPLD is used to select whether the input or output pin should be connected to the timer. This selection is also controlled through the CPLD MISC register.
2-11
Spectrum Digital, Inc
2-12
TMS320VC5502 EVM Module Technical Reference
Chapter 3 Physical Description
This chapter describes the physical layout of the TMS320VC5502 EVM and its connectors.
Topic 3.1 3.1.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.7 3.8
Page TMS320VC5502 EVM Board Layout Keypad/display Module Layout Connector Index Expansion Connectors P1, Memory Expansion Connector P2, Peripheral Expansion Connector P3, HPI Expansion Connector Audio Connectors J1, Microphone Connector J2, Audio Line In Connector J3, Audio Line Out Connector J4, Headphone Connector Power Connectors J5, +5 Volt Connector J6, Alternate Power Connector Miscellaneous Connectors J8, RS-232 Connector J7, External JTAG Connector JP1, PLD Programming Connector System LEDs Reset Circuitry
3-2 3-3 3-4 3-4 3-5 3-6 3-7 3-8 3-8 3-8 3-9 3-9 3-10 3-10 3-10 3-11 3-11 3-11 3-12 3-12 3-12
3-1
Spectrum Digital, Inc 3.1 TMS320VC5502 EVM Board Layout The VC5502 EVM is a 8.25 x 4.5 inch (210 x 115 mm.) multi-layer board which is powered by an external +5 volt only power supply. The figure below shows the layout of the VC5502 EVM. J4 P1 J3 J2 P3 J1 JP2
JP5
J6
JP3 S2
J5
P4
DS5 S1 DS7
J7
JP4
P2 P5
JP1
DS1-4
Figure 3-1, TMS320VC5502 EVM
3-2
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 3.2 Keypad/display Module Layout The Keypad/display Module is a 3.1 x 4.4 inch (79 x 112 mm.) multi-layer board which is powered from the EVM. The figure below shows the layout of the Keypad/display Module.
Figure 3-2, Keypad/display Module
3-3
Spectrum Digital, Inc 3.2 Connector Index The TMS320VC5502 EVM has many connectors which provide the user access to the various signals on the EVM. Table 1: TMS320VC5502 EVM Connectors Connector
# Pins
Function
P1
80
P2
80
Peripheral
P3
80
HPI
P4
9
RS-232 Port
P5
16
Display - Keypad
J1
2
Microphone
J2
2
Line In
J3
2
Line Out
J4
2
Speaker
J5
2
+5 Volt
J6 *
4
Alternate Power Connector
J7
14
External JTAG
Memory
Note: “*” Not populated 3.3 Expansion Connectors The TMS320VC5502 EVM supports three expansion connectors that follow the Texas Instruments interconnection guidelines. The expansion connector pinouts are described in the following three sections. The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profile connectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectors are designed for high speed interconnections because they have low propagation delay, capacitance, and cross talk. The connectors present a small foot print on the EVM. Each connector includes multiple ground, +5V, and +3.3V power signals so that the daughter card can obtain power directly from the EVM. The peripheral expansion connector additionally provides both +12V and -12V to the daughter card, if the alternate power supply connector is used to power the board. The recommended mating connector, whose part number is TFM-140-32-S-D-LC, is a surface mount connector that provides a 0.465” mated height. Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin
3-4
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 3.3.1 P1, Memory Expansion Connector Table 2: P1, Memory Expansion Connector Pin #
Signal Name
I/O/Z
Pin #
Signal Name
1
+5 Volts
O
2
+5 volts
I/O/Z O
3
A21
O
4
A20
O
5
A19
O
6
A18
O
7
A17
O
8
A16
O
9
A15
O
10
A14
O
11
GND
O
12
GND
O
13
A13
O
14
A12
O
15
A11
O
16
A10
O
17
A9
O
18
A8
O
19
A7
O
20
A6
O
21
+5 Volts
O
22
+5 Volts
O
23
A5
O
24
A4
O
25
A3
O
26
A2
O
27
BE3n
O
28
BE2n
O
29
BE1n
O
30
BE0n
O
31
GND
O
32
GND
O
33
D31
I/O/Z
34
D30
I/O/Z
35
D29
I/O/Z
36
D28
I/O/Z
37
D27
I/O/Z
38
D26
I/O/Z
39
D25
I/O/Z
40
D24
I/O/Z
41
+3.3 Volts
O
42
+3.3 Volts
O
43
D23
I/O/Z
44
D22
I/O/Z
45
D21
I/O/Z
46
D20
I/O/Z
47
D19
I/O/Z
48
D18
I/O/Z
49
D17
I/O/Z
50
D16
I/O/Z
51
GND
O
52
GND
O
53
D15
I/O/Z
54
D14
I/O/Z
55
D13
I/O/Z
56
D12
I/O/Z
57
D11
I/O/Z
58
D10
I/O/Z
59
D9
I/O/Z
60
D8
I/O/Z
61
GND
O
62
GND
O
63
D7
I/O/Z
64
D6
I/O/Z
65
D5
I/O/Z
66
D4
I/O/Z
67
D3
I/O/Z
68
D2
I/O/Z
69
D1
O
70
D0
O
71
GND
O
72
GND
O
73
REn
O
74
WEn
O
75
OEn
O
76
RDYn
I
77
CE3n
O
78
CE2n
O
79
GND
O
80
GND
O
3-5
Spectrum Digital, Inc 3.3.2 P2, Peripheral Expansion Connector Table 3: P2, Peripheral Expansion Connector
3-6
Pin #
Signal Name
I/O/Z
Pin #
Signal Name
I/O/Z
1
+12 Volts *
O
2
-12 Volts *
O
3
GND
O
4
GND
O
5
+5 Volts
O
6
+5 Volts
O
7
GND
O
8
GND
O
9
+5 Volts
O
10
+5 Volts
O
11
I2C SCL
O/Z
12
I2C SDA
I/O/Z
13
RESERVED
14
RESERVED
15
RESERVED
16
RESERVED
17
RESERVED
18
RESERVED
19
+3.3 Volts
O
20
+3.3 Volts
21
CLKX0
I/O/Z
22
RESERVED
23
FSX0
I/O/Z
24
DX0
O/Z
25
GND
O
26
GND
O
27
CLKR0
I/O/Z
28
RESERVED
29
FSR0
I/O/Z
30
DR0
I
31
GND
O
32
GND
O
33
CLKX1
I/O/Z
34
RESERVED
I
35
FSX1
I/O/Z
36
DX1
O/Z O
O
37
GND
O
38
GND
39
CLKR1
I/O/Z
40
RESERVED
41
FSR1
I/O/Z
42
DR1
Z
43
GND
O
44
GND
O
45
TOUT0
Z
46
TIN0
I
47
INT0n
I
48
INT2n
I
49
TOUT1
O
50
TIN1
I
51
GND
O
52
GND
O
53
INT1n
I
55
RESERVED
57
RESERVED
59
RESETn
O
61
GND
O
62
GND
O
63
DC_CNTL1
O
64
DC_CNTL0
O
65
DC_STAT1
I
66
DC_STAT0
I
67
INT3n
I
68
RESERVED
69
RESERVED
70
RESERVED
71
RESERVED
72
RESERVED
73
RESERVED
74
RESERVED
75
DETECTn
I
76
GND
O
77
GND
O
78
CLKOUT
O
79
GND
O
80
GND
O
54
IACKn
I
56
RESERVED
O
58
RESERVED
I
60
RESERVED
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 3.3.3 P3, HPI Expansion Connector Table 4: P3, HPI Expansion Connector Pin #
Signal Name
I/O/Z
Pin #
Signal Name
1
+5 Volts
O
2
+5 Volts
I/O/Z O
3
CLKX2
I/O/Z
4
CLKR2
I/O/Z
5
FSX2
I/O/Z
6
FSR2
I/O/Z
7
DX2
O/Z
8
DR2
I
9
IO4
I/O
10
RESERVED
I
11
GND
O
12
GND
O
13
HRW
I
14
HCNTL0
I
15
HPINEA
I
16
HCS
I
17
IO6
I/O
18
IO7
I/O
19
HDS2
I
20
HDS1
I
21
+5 Volts
O
22
+5 Volts
O
23
HRDY
O/Z
24
HINT
O/Z
25
IO0
I
26
IO1
I
27
Reserved
I
28
Reserved
I
29
HCI
I
30
HCO
I
31
GND
O
32
GND
O
33
Reserved
I
34
Reserved
I
35
Reserved
I
36
Reserved
I
37
Reserved
I
38
Reserved
I
39
Reserved
I
40
Reserved
I
41
+5 Volts
O
42
+5 Volts
O
43
Reserved
I
44
Reserved
I
45
Reserved
I
46
Reserved
I
47
Reserved
I
48
Reserved
I
49
HCNTL1
I
50
Reserved
I
51
GND
O
52
GND
O
53
Reserved
I/O/Z
54
Reserved
I/O/Z
55
Reserved
I/O/Z
56
Reserved
I/O/Z
57
Reserved
I/O/Z
58
Reserved
I/O/Z
59
Reserved
I/O/Z
60
Reserved
I/O/Z
61
GND
O
62
GND
O
63
HD7
I/O/Z
64
HD6
I/O/Z
65
HD5
I/O/Z
66
HD4
I/O/Z
67
HD3
I/O/Z
68
HD2
I/O/Z
69
HD1
I/O/Z
70
HD0
I/O/Z
71
GND
O
72
GND
O
73
HOLDA
O/Z
74
HOLD
I
75
NMIn
I
76
IO2
I/O
77
XF
O
78
HPI_RST
I
79
GND
O
80
GND
O
3-7
Spectrum Digital, Inc 3.4 Audio Connectors The VC5502 EVM has 4 audio connectors. They are described in the following sections. 3.4.1 J1, Microphone Connector The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is monaural. The signals on the plug are shown in the figure below.
Ground Microphone In Microphone Bias Figure 3-3, Microphone Stereo Jack 3.4.2 J2, Audio Line In Connector The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground Right Line In Left Line In Figure 3-4, Audio Line In Stereo Jack
3-8
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 3.4.3 J3, Audio Line Out Connector The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground Right Line Out Left Line Out Figure 3-5, Audio Line Out Stereo Jack
3.4.4 J4, Headphone Connector Connector J4 is a headphone/speaker jack. It can drive standard headphones or a high impedance speaker directly. The standard 3.5 mm jack is shown in the figure below .
Ground Right Headphone Left Headphone Figure 3-6, Headphone Jack
3-9
Spectrum Digital, Inc 3.5 Power Connectors The VC5502 EVM has 2 power connectors. They are described in the following sections.
3.5.1 J5, +5 Volt Connector Power (+5 volts) is brought onto the TMS320VC5502 EVM via the J5 connector. The connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. The A diagram of J5 is shown below. +5V J5
Ground PC Board
Front View Figure 3-7, TMS320VC5502 EVM Power Connector 3.5.2 J6, Alternate Power Connector Connector J6 is an alternate power connector. It will operate with the standard personal computer power supply. To populate this connector use a Molex #53109-0410. The table below shows the voltages on the respective pins. Table 5: J6, Optional Power Connector Pin #
Voltage Level
1
+12 Volts
2
-12 Volts
3
Ground
4
+5 Volts
WARNING ! Do not plug into J5 and J6 at the same time.
3-10
TMS320VC5502 EVM Module Technical Reference
Spectrum Digital, Inc 3.6 Miscellaneous Connectors The VC5502 EVM has 3 additional connectors to aid the user in developing with this product. They are described in the following sections.
3.6.1 P4, RS-232 Connector Connector P4 is a female RS-232 providing an interface to the UART. The signals on this connector are shown in the below. Table 6: P4, RS-232 Connector Pin #
Signal Name
Direction
1
Reserved
2
Transmit Data
Output
3
Receive Data
Input
4
Reserved
5
Ground
6
Reserved
7
CTS
Input
8
RTS
Output
9
Reserved
Output
3.6.2 J7, External JTAG Connector The TMS320VC5502 EVM is supplied with a 14 pin header interface, J7. This is the standard interface used by JTAG emulators to interface to Texas Instruments DSPs. The pinout for the connector is shown figure 3-6 below.
TMS TDI PD (+3.3V) TDO TCK-RET TCK EMU0
1 3 5 7 9 11 13
2 4 6 8 10 12 14
TRSTGND no pin (key) GND GND GND EMU1
Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal
Figure 3-8, JTAG INTERFACE
3-11
Spectrum Digital, Inc 3.6.3 JP1, PLD Programming Connector This connector interfaces to the Altera CPLD, U2. It is used in the in the factory for the programming of the CPLD. This connector is not intended to be used outside the factory.
3.7 System LEDs TheTMS320VC5502 EVM has two system light emitting diodes (LEDs). These LEDs indicate various conditions on the EVM. These function of each LED is shown in the table below. Table 7: System LEDs Reference Designator
Color
Function
On Signal State
DS6
Green
+5 Volt present
1
DS5
Orange
RESET Active
1
3.8 Reset Circuitry There are three resets on the TMS320VC5502 EVM. The first reset is the power on reset. This circuit waits until power is within the specified range before releasing the power on reset pin to the TMS320VC5502. External sources which control the reset are push button S1, and HPI Reset from the expansion connector.
3-12
TMS320VC5502 EVM Module Technical Reference
Appendix A Schematics
This appendix contains the schematics for the TMS320VC5502 EVM and the keypad/display module.
Topic A.1 A.2
Page TMS320VC5502 EVM Schematics Keypad/display Module Schematics
A-2 A-23
A-1
4
3
2
1
REVISIONS REV
BOOTM2
BOOTM1
BOOTM0
GPIO1
GPIO0
GPIO2
000
NO BOOT 16 BIT MODE
WHICH CHIP SELECT 0XFFFF00
001
SERIAL EEPROM SPI 24 BIT ADDRESS
MCBSP0
010
SERIAL 16 BIT
MCBSP0
D
DESCRIPTION
DATE
APPROVED
D
MODE PARALLEL EMIF
011
C
16 BIT MODE
0X200000
100
NO BOOT 32 BIT MODE
0XFFFF00
101
HPI BOOT MODE
110
I2C BOOT MODE
111
UART BOOT
C
MODE
SDRAM
CE0
FLASH AND CPLD
CE1
REGISTERS
TMS320VC5502 EVM Module Technical Reference
CE2
EXPANSION
CE3
SBRAM OR EXPANSION
B
B
REVISION STATUS OF SHEETS
A
REV
A
SH
21
DWN
DATE
CHK
DATE A
REV
A
A
A
A
A
A
A
A
A
A
SH
11
12
13
14
15
16
17
18
19
20
REV
A
A
A
A
A
A
A
A
A
A
SH
1
2
3
4
5
6
7
8
9
10
ENGR
DATE
ENGR-MGR
DATE
QA
DATE
MFG
DATE
RLSE
DATE
SPECTRUM DIGITAL Title TMS320VC5502 EVALUATION MODULE
NEXT ASSY
USED ON
Size B Date:
5
Document Number 506662
Rev A
APPLICATION 4
3
2
Monday, May 19, 2003
Sheet 1
1
of
21
Spectrum Digital, Inc
A-2
5
5
4
3
3.3V
VDD_PLL
2
8 7 6 5
8 7 6 5
A[2..21]
RN21 RN5
HINTn HDS2 HDS1
HRDY
D
R2 R1 T3 U2
HC0 HC1 HCNTL0 HCNTL1
(14)
HCS
(14)
HR/W
(14)
T1 R4
HD[0..7] 3.3V
(14)
HDS1
(14)
HDS2
(14)
HRDY
(14)
HINT
(14)
HPIENA
9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1
RPACK8-10K
(14)
R5
HDS2
T4
HRDY
T5
HR/WHDS1HDS2HRDY
T7
HINT-
HPIENA
C7
HPIENA
B3 C4 B4 C5 B5 C6 B6 D7
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7
T6
DSP_XF
E2 F3 F2 G4 G3
INT0INT1INT2INT3NMI-
(3,15) DSP_RSTn
B7
RESET-
(3,18) DSP_CLKIN
TP12 TestPoint
1
TP16 TestPoint
1
R8 P8 T11
(18) DSP_ECLKIN (4,8) DSP_BDR0 (4,8) DSP_BDX0 (4,8) DSP_BCLKX0 (8) DSP_BCLKR0 (8) DSP_BFSX0 (8) DSP_BFSR0
(8) DSP_BDR1 (8) DSP_BDX1 (8) DSP_BCLKX1 (8) DSP_BCLKR1 (8) DSP_BFSX1 (8) DSP_BFSR1
(8) DSP_BDR2 (8) DSP_BDX2 (8) DSP_BCLKX2 (8) DSP_BCLKR2 (8) DSP_BFSX2 (8) DSP_BFSR2 (4,6,21) DSP_SDA (4,6,18) DSP_SCL
B
(3) DSP_TIN/TOUT0 (3) DSP_TIN/TOUT1
RN6 DSP_BDR0 DSP_BDX0 DSP_BCLKX0 DSP_BCLKR0 DSP_BFSX0 DSP_BFSR0
C0/ARE-/SADS/SDCAS-/GPIO20 C1/AOE-/SOE-/SDRAS-/GPIO21 C2/AWE-/SWE-/SDWE-/GPIO22 C3/ARDY/GPIO23 C4/CS0-/GPIO24 C5/CS1-/GPIO25 C6/CS2-/GPIO26 C7/CS3-/GPIO27 C8/BE0-/GPIO28 C9/BE1-/GPIO29 C10/BE2-/GPIO30 C11/BE3-/GPIO31 C12/SDCKE/GPIO32 C13/SOE3-/GPIO33 C14/HOLD-/GPIO34 C15/HOLDA/GPIO35
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
X2/CLKIN X1 ECLKIN
RPACK8-33
8 7 6 5 4 3 2 1
9 10 11 12 13 14 15 16
RN10 DSP_BDR1 DSP_BDX1 DSP_BCLKX1 DSP_BCLKR1 DSP_BFSX1 DSP_BFSR1
8 7 6 5 4 3 2 1
9 10 11 12 13 14 15 16
RPACK8-33
RN9 DSP_BDR2 DSP_BDX2 DSP_BCLKX2 DSP_BCLKR2 DSP_BFSX2 DSP_BFSR2
8 7 6 5 4 3 2 1
9 10 11 12 13 14 15 16
RPACK8-33
H4 J4 H2 H1 J3 H3
K1 K4 K3 J2 L2 K2
L3 L4 N3 N2 M3 M2
DSP_SDA DSP_SCL
P3 P2
DSP_TIN/TOUT0 DSP_TIN/TOUT1
E3 D1
9 10 11 12 13 14 15 16
8 7 6 5 4 3 2 1
9 10 11 12 13 14 15 16
8 7 6 5 4 3 2 1
9 10 11 12 13 14 15 16
RN22
J16 J15 J14 K16 K15 K14 L17 L16 L15 L14 M16 M15 N16 N15 P16 P15 R16 T17 U16 T15
A2 A3 A4 A5 A6 A7
A8 A9 A10 A11 A12 A13 A14 A15
DR0 DX0 CLKX0 CLKR0 FSX0 FSR0
DR1 DX1 CLKX1 CLKR1 FSX1 FSR1
DR2 DX2 SP0/CLKX2/GPIO3 SP1/CLKR2/UARTTX SP2/FSX2/GPIO5 SP3/FSR2/UARTRX
A16 A17 A18 A19 A20 A21 4 3 2 1
CLKOUT IACK
SDCASn SDRASn SDWEn DSP_ARDY
5 6 7 8
4 3 2 1 RN7
5 6 7 8
CE0n CE1n CE2n CE3n
(4) (3) (10) (5,10)
5 6 7 8 RPACK4-33
BE0n BE1n BE2n BE3n
(4,5,10) (4,5,10) (4,5,10) (4,5,10)
(4,5,10)
AOEn
(4,5,10)
SOEn
(4,5,10)
AWEn
(4,5,10)
SWEn
(4,5,10)
(4,5,10) (4,5,10) (4,5,10) (11)
33
DSP_SDCKE
(4)
DSP_HOLDn (14) DSP_HOLDAn (14)
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
R1
SADSn
SDCASn SDRASn SDWEn DSP_ARDY
R140
R6
(4,5,10)
RPACK4-33 4 3 2 1
TP10
AREn
RPACK4-33
C
3.3V 3.3V
R74 10K
R72 4.7K
R94 10K
R95 10K
DSP_HOLDn DSP_ARDY DSP_TIN/TOUT0 DSP_TIN/TOUT1
3.3V
R150 2K
D[0..31]
SDA SCL
D
RPACK8-33
RN8
B10 C10 D10 A10 B11 C11 D11 B12 C12 B13 C13 A14 B14 C14 A15 B15 A16 B17 C16 D15 D16 D17 E15 E16 F15 F16 G14 G15 G16 H15 H14 H16
(4,5,10)
RPACK8-33
RN23
U15 R14 T14 R13 T13 R12 T12 R10 P10 T10 U10 T9 R9 P9 R7 P7
A[2..21]
RPACK8-33
RN2
XF
INT0n INT1n INT2n INT3n NMIn
(12) (12) (12) (12) (14)
E1 J1 M1 U4 U12 M17 H17 F17 A11 A6 A4
HCS-
HINTn
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7
RN4
C
HDS1
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
HC0/HAS/GPIO44 HC1/HBIL/GPIO45 HCNTL0 HCNTL1
8 7 6 5 4 3 2 1
33
DSP_CLKOUT (12)
G2
DSP_IACKn
D[0..31]
R151 2K
(5)
3.3V B
C9
(12)
TIM0 TIM1
DSP_SDA
.01uF U38A 74CBTLV3125PWR
14
(14) (14) (14) (14)
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11
VDDSHV1 VDDSHV2 VDDSHV3 VDDSHV4 VDDSHV5 VDDSHV6 VDDSHV7 VDDSHV8 VDDSHV9
4 3 2 1
RPACK4-10K 1 2 3 4
1 2 3 4
RPACK4-10K
VDDP
U3
RPACK4-10K
U7
RN3 F1 N1 U5 U13 P17 K17 E17 A13 A5
RN1
1
CVCC
5 6 7 8
3.3V
DSP_SCL
T8
(3,7) DSP_EMIFCLKS
ECLKO2 ECLKO1
R11
R138
33
P11
R137
33
U38D 74CBTLV3125PWR 12
PLLSENSE
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17
U38B 74CBTLV3125PWR 5
(4,6,21) DSP_SDA
(13)
X_SCL
(13)
U38C 74CBTLV3125PWR
TP13
A
9
(4,6,18) DSP_SCL 3.3V
X_SDA
4
TMS320VC5502GGW
C112 NO POP
6
U8
10K
11
(3) CPLD_ECLK01ONn
NO POP
G1 L1 P1 U6 U9 U11 U14 R17 N17 J17 G17 C17 A12 A9 A8 A3 U3
10K
DSP_CLKMEM (4,5)
(3) CPLD_ECLK02ONn
R98 R3
DSP_CLKMEM
3
EMIFCLKS TRSTTCK TDI TDO TMS EMU0 EMU1
3.3V
R2
2
8
A
VDD_PLL BEAD
10
L14
+
C140 0.1uF
(3) CPLD_I2CONn
C120 10uF
SPECTRUM DIGITAL
CVCC Title
3.3V
TMS320VC5502 EVALUATION MODULE GND
A-3
CVCC
3.3V
GND
Size C Date:
5
4
3
2
Document Number 506662
Rev A
Monday, May 19, 2003
Sheet 1
2
of
21
Spectrum Digital, Inc
D8 C8 B8 B9 A7 C9 D9
(17) DSP_TRST# (17) DSP_TCK (17) DSP_TDI (17) DSP_TDO (17) DSP_TMS (17) DSP_EMU0 (17) DSP_EMU1
GPIO7 GPIO6 GPIO4 GPIO2 GPIO1 GPIO0
1 7
A2 B1 C2 C1 D3 D2
DSP_GPIO7 DSP_GPIO6 DSP_GPIO4 DSP_GPIO2 DSP_GPIO1 DSP_GPIO0
13
(7,14) (7,14) (3,7,14) (3,7,14) (3,7,14) (3,7,14)
Spectrum Digital, Inc
A-4
3.3V 3.3V 3.3V
R4 R5 R6
10K 10K 10K
3.3V DSP_RSTn
JP1
R9
XCTL_OEn
R7
XDATA_OEn
R73
10K
HPI_RESETn
R91
10K
10K
1K
1 2 3 4 5 6 7 8 9 10
ISR_TCK ISR_TMS
C2
C3
C4
C5
C6
C7
C8
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C1 0.1uF
ISR_TDI ISR_TDO
PULLUP/DOWN TO KEEP LOGIC IN RESET WHEN THE CPLD IS NOT PROGRAMMED.
HEADER 5x2 ONB_D7 ONB_D6 ONB_D5 ONB_D4 ONB_D3 ONB_D2 ONB_D1 ONB_D0
ONB_D[0..31]
(9,11,15)
ONB_A[2..21]
(10,12,15)
3.3V
(7)
USER_LED4
ONB_A21
(6) LcdSI (9) ONB_XDATA_T/Rn (6) LcdA0
ONB_A3
(13) DC_STAT0 (10,11) ONB_CE2n (2,7,14) DSP_GPIO0 (13) X_TIN1 (13) DC_DETECTn (7)
PBSW_RSTn
ONB_A5
PBSW_RSTn
70 71 72 75 76 77 79 80 81 83 84 85 92 93 94 96 97 98 99 100 88 89 87 90
TP8 (10,11,15) ONB_AWEn (2,18) DSP_CLKIN
62 15 4
ISR_TCK ISR_TMS ISR_TDI R110 10K
3 18 34 51 66 82
PIN70 PIN71 PIN72 PIN75 PIN76 PIN77 PIN79 PIN80 PIN81 PIN83 PIN84 PIN85 PIN92 PIN93 PIN94 PIN96 PIN97 PIN98 PIN99 PIN100
PIN1 PIN2 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10
PIN30 PIN31 PIN32 PIN35 PIN36 PIN37
IN/OE1 IN/GCLR IN/GCLK1 IN/OE2/GCLK2 TCK TMS TDI
ONB_A21 ONB_A5 ONB_A4 ONB_A3 ONB_A2
PIN12 PIN13 PIN14 PIN16 PIN17 PIN19 PIN20 PIN21 PIN22 PIN23 PIN24 PIN25 PIN26 PIN28 PIN29
GNDIO1 GNDIO2 GNDIO3 GNDIO4 GNDIO5 GNDIO6 GNDIO7 GNDIO8 GNDIO9 GNDIO10
DSP_RSTn
(2,15) DSP_RSTn (4) SROM_CSn (8) CPLD_EXP_MCBSP0n (20) CORE_V_CTL (20) PON3.3VRSn (14) HPI_RESETn (6) LcdSCK
PIN60 PIN61 PIN63 PIN64 PIN67 PIN68 PIN69
11 26 33 43 53 59 65 74 78 95
TMS320VC5502 EVM Module Technical Reference
(8) CPLD_OB_MCBSP1n (7) USER_LED1 (8) CPLD_EXP_MCBSP1n
60 61 63 64 67 68 69
GNDINT1 GNDINT2
ONB_D0
38 86
(8) CPLD_OB_MCBSP2n (5) CPLD_SBRAM_EN (13) DC_CNTL0
PIN52 PIN54 PIN55 PIN56 PIN57 PIN58
VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6
(7) USER_LED2 (2) CPLD_I2CONn (8) CPLD_EX_MCBSP2n (13) DC_CNTL1 (15) FLASH_CEn
52 54 55 56 57 58
VCCINT1 VCCINT2
U2 ONB_D1
39 91
ONB_A[2..21]
1 2 5 6 7 8 9 10 12 13 14 16 17 19 20 21 22 23 24 25 27 28 29 30 31 32 35 36 37
PIN40 PIN41 PIN42 PIN44 PIN45 PIN46 PIN47 PIN48 PIN49 PIN50
40 41 42 44 45 46 47 48 49 50
TDO
73
USER_SW3 ONB_A2
ONB_A4
DSP_GPIO4 PONCOREn USER_SW3 ONB_AREn
(2,7,14) (20) (7) (10,11)
ONB_CE3n CE1n USER_SW0
(10,11) (2) (7)
DSP_EMIFCLKS (2,7) X_TIN0 (13) DC_PORSTn (13) USER_SW1 (7) XDATA_OEn (11) DSP_GPIO1 (2,7,14) DSP_GPIO2 (2,7,14) X_TOUT1 (13) USER_SW2 (7) ONB_XDATA_OEn (9) ONB_AOEn (10,11,15) CPLD_ECLK01ONn (2) DSP_TIN/TOUT1 (2) CPLD_ECLK02ONn (2)
ONB_D6 ONB_D2 ONB_D3
X_TOUT0 X_RESETn
(13) (13)
DSP_TIN/TOUT0 (2)
ONB_D4 TP7 TP9 ONB_D5
ONB_D7 XCTL_OEn
3.3V
DSP_RST_LEDn (7) 3.3V USER_LED3 DC_STAT1
(7) (13)
GND
GND
XCTL_OEn (11,12) DSP_KEYBD_RSn (6)
ISR_TDO
SPECTRUM DIGITAL EPM3128ATC100
Title TMS320VC5502 EVALUATION MODULE
CPLD
Size B Date:
Document Number 506662 Monday, May 19, 2003
Rev A Sheet
3
of
21
5
4
3
2
1
(5,9) RAMD[0..31]
(2,5,10)
A[2..21]
A[2..21]
D
D
3.3V U24 3.3V 3.3V 3.3V 3.3V R156 10K
R157 10K
R80 10K
R154 10K
U18 (3)
1
SROM_CSn
2 3.3V
C
R141
33
CS
VCC
SO
HOLD
3
WP
4
GND
8
3.3V
7
SCLK
6
SIN
5
C141 0.1uF
AT25F512N (2,8)
DSP_BDR0
(2,8)
DSP_BDX0
25 26 27 60 61 62 63 64 65 66 24
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
A13 A14
22 23
BA0 BA1
68 67
CLK CKE
DSP_CLKMEM
(2,5) DSP_CLKMEM (2) DSP_SDCKE
SDRAM_CEn SDWEn SDCASn SDRASn
(2) CE0n (2,5,10) SDWEn (2,5,10) SDCASn (2,5,10) SDRASn (2,5,10) (2,5,10) (2,5,10) (2,5,10)
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
20 17 18 19 BE0n BE1n BE2n BE3n
BE0n BE1n BE2n BE3n
16 71 28 59
VDD1 VDD2 VDD3 VDD4 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ87 VSS1 VSS2 VSS3 VSS4 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8
CSn W En CASn RASn DQM0 DQM1 DQM2 DQM3
1 15 29 43 3 9 35 41 49 55 75 81 44 58 72 86 C
6 12 32 38 46 52 78 84
(2,8) DSP_BCLKX0
SPI Boot Memory 3.3V C136 .1uF
B
U35 1 2 3 4
A0 A1 NC VSS
VCC WP SCL SDA
8 7 6 5
RAMD0 RAMD1 RAMD2 RAMD3 RAMD4 RAMD5 RAMD6 RAMD7
2 4 5 7 8 10 11 13
RAMD8 RAMD9 RAMD10 RAMD11 RAMD12 RAMD13 RAMD14 RAMD15
74 76 77 79 80 82 83 85
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
31 33 34 36 37 39 40 42
RAMD16 RAMD17 RAMD18 RAMD19 RAMD20 RAMD21 RAMD22 RAMD23
45 47 48 50 51 53 54 56
RAMD24 RAMD25 RAMD26 RAMD27 RAMD28 RAMD29 RAMD30 RAMD31
B
MT48LC2M32B2
3.3V 3.3V
I2C EEPROM
3.3V C10 .1uF
(2,6,21) DSP_SDA
C11 .1uF
C12 .1uF
C13 .1uF
GND
GND
(2,6,18) DSP_SCL A
A
SPECTRUM DIGITAL Title
MEMORY - SDRAM/SERIAL ROMS
TMS320VC5502 EVALUATION MODULE
A-5
Size B Date: 5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
4
of
21
Spectrum Digital, Inc
24WC256
4
3
2
3.3V
3.3V (2,4,10)
A[2..21]
A[2..21]
U17 14 15 41 65 91
D
A11 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
3.3V
R130 10K
R131 NO POP
R132 10K
R133 10K
R134 10K
R135 NO POP
R136 10K
C
(2,4,10) (2,4,10) (2,4,10)
37 36 50 47 45 44 49 48 46 43 34 33 32 99 35 100 82 81
(2,4) DSP_CLKMEM (2,4,10) BE3n (2,4,10) BE1n (2,4,10) BE0n (2,4,10) BE2n (3) CPLD_SBRAM_EN (2,10) CE3n
TMS320VC5502 EVM Module Technical Reference
83 84 85 86 87 88 89 92 93 94 95 96 97 98 31 42 64 5 10 17 21 26 40 55 60 67 71 76 90
SSADSn SSOEn SSW En SBS_GW_N_PU SBRAMCLK SBS_CE2_PD BYTE_ENABLE3 BYTE_ENABLE1 BYTE_ENABLE0 BYTE_ENABLE2 SBS_CE2_PU
SADSn SOEn SW En
SBS_MODE_PD
R125 NO POP
R121
R122
R123
R124
1K
NO POP
1K
1K
1
B
RAMD[0..31]
VDD VDD VDD VDD VDD SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 /ADV /ADSP /ADSC /OE /BWE /GW CLK /CE2 /BWA /BWB /BWC /BWD CE2 /CE MODE NF/SA ZZ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
4 11 20 27 54 61 70 77
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
23 22 29 28 18 25 19 24
RAMD16 RAMD17 RAMD18 RAMD19 RAMD20 RAMD21 RAMD22 RAMD23
DQA DQA DQA DQA DQA DQA DQA DQA
57 52 53 59 63 56 58 62
RAMD24 RAMD25 RAMD26 RAMD27 RAMD28 RAMD29 RAMD30 RAMD31
DQB DQB DQB DQB DQB DQB DQB DQB
68 78 74 72 75 79 73 69
RAMD8 RAMD9 RAMD10 RAMD11 RAMD12 RAMD13 RAMD14 RAMD15
DQC DQC DQC DQC DQC DQC DQC DQC
9 6 8 7 13 3 2 12
RAMD0 RAMD1 RAMD2 RAMD3 RAMD4 RAMD5 RAMD6 RAMD7
1 16 30 51 66 80 39 38
(4,9)
D
DQD DQD DQD DQD DQD DQD DQD DQD
NC/DQPC NC NC/DQPD NC/DQPA NC NC/DQPB DNU DNU
RAMD[0..31]
RPACK8-33 RAMD0 RAMD1 RAMD2 RAMD3 RAMD4 RAMD5 RAMD6 RAMD7 RPACK8-33 RN26 RAMD8 RAMD9 RAMD10 RAMD11 RAMD12 RAMD13 RAMD14 RAMD15 RPACK8-33 RN27 RAMD16 RAMD17 RAMD18 RAMD19 RAMD20 RAMD21 RAMD22 RAMD23 RPACK8-33 RN28 RAMD24 RAMD25 RAMD26 RAMD27 RAMD28 RAMD29 RAMD30 RAMD31
RN25 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D0 D1 D2 D3 D4 D5 D6 D7
9 10 11 12 13 14 15 16
D8 D9 D10 D11 D12 D13 D14 D15
8 7 6 5 4 3 2 1
D16 D17 D18 D19 D20 D21 D22 D23
9 10 11 12 13 14 15 16
D24 D25 D26 D27 D28 D29 D30 D31
3.3V
D[0..31]
RN24 1 2 3 4
C
D[0..31]
(2)
8 7 6 5
B
RPACK4-10K
MT58L256L32PS OR MT58L256L36PS
3.3V
3.3V
3.3V C124
C125
C115
C97
C67
C68
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
C69 .1uF
A
A
SPECTRUM DIGITAL GND
Title
GND
TMS320VC5502 EVALUATION MODULE Size B Date:
5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
5
of
21
Spectrum Digital, Inc
A-6
5
5
4
3
2
1
D
D
RN19 4 3 2 1
(3) LcdSI (3) LcdA0 (3) LcdSCK (3) DSP_KEYBD_RSn
5 6 7 8
R147
LcdSIKYBD LcdA0KYBD LcdSCKKYBD DSP_RSnKYBD
P5 VCC_KEYOARD
3.3V +
5.1
C126 1uF
C127 0.1uF
1 3 5 7 9 11 13 15
LcdSIKYBD DSP_RSnKYBD
33 RPACK4 C
2 4 6 8 10 12 14 16
LcdA0KYBD LcdSCKKYBD
C
HEADER 8X2
(2,4,21) DSP_SDA
(2,4,18) DSP_SCL
R148
33
R149
33
B
B
A
3.3V
SPECTRUM DIGITAL
GND
GND
Title TMS320VC5502 EVALUATION MODULE
A-7
Size B Date: 5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
6
of
21
Spectrum Digital, Inc
3.3V A
4
3
2
3.3V
R16 150
R17 150
RN11
D
(3) (3) (3) (3)
4 3 2 1
USER_SW0 USER_SW1 USER_SW2 USER_SW3
5 6 7 8
1
USER LEDS
3.3V
R14 150
R15 150
DS3 GREEN
DS4 GREEN
R13 150 D
DS1 DS2 GREEN
GREEN
DS5 YELLOW
PWB REVISION IS EMBEDDED IN CPLD REGISTER DIRECTLY
8 7 6 5
RPACK4-10K
S2
1 2 3 4
SW DIP-4
(3)
USER_LED1
(3)
USER_LED2
(3)
USER_LED3
(3)
USER_LED4
USER_LED1 USER_LED2 USER_LED3 USER_LED4 3.3V DSP_RST_LEDn
(3) DSP_RST_LEDn
R19 10K
HPI MODE ONLY SUPPORT MULTIPLEXED MODE
3.3V C
C
9 10 11 12 13 14 15 16
DSP_GPIO6
(2,14)
R22 NO POP RN12
8 7 6 5 4 3 2 1
RPACK8-10K
USER OPTIONS
5 6 7 8
1 3 5 7 9
2 4 6 8 10
BOOTMODE2 BOOTMODE1 BOOTMODE0
DSP_EMIFCLKS (2,3) DSP_GPIO7 (2,14) DSP_GPIO2 (2,3,14) DSP_GPIO1 (2,3,14) DSP_GPIO0 (2,3,14)
B
HEADER 5X2 RN13
RPACK4-2K
3.3V
3.3V
R114 10K
3.3V 3.3V
3.3V
DSP_GPIO4
PUSHBUTTON RESET
B BB
AA
U30
R82
A
2
4
PBSW_RSTn
PBSW_RSTn
(3)
SPECTRUM DIGITAL
PUSHBUTTON SW SN74AHC1G14
33 C102 1uF
Title TMS320VC5502 EVALUATION MODULE
LEDS/SWITCHES
Size B Date:
5
GND
R113 NO POP
C117 0.1uF
S1 A
GND
5
R24 10K
(2,3,14)
3
TMS320VC5502 EVM Module Technical Reference
JP4 4 3 2 1
B
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
7
of
21
Spectrum Digital, Inc
A-8
5
5
4
3
2
1
U12 3.3V
R152 10K
D
18 17 16 15 14 13 12 11
R153 10K
4.1V
(3) CPLD_EX_MCBSP2n
20 10
(3) CPLD_OB_MCBSP2n
B1 B2 B3 B4 B5 B6 B7 B8
A1 A2 A3 A4 A5 A6 A7 A8
2 3 4 5 6 7 8 9
VCC
OE NC
19 1
X_DR2 X_DX2 X_CLKX2 X_CLKR2 X_FSX2 X_FSR2
(14) (14) (14) (14) (14) (14) 4.1V 4.1V
GND
D
C130
SN74CBT3245
C131
.1uF
.1uF
C132
C134
.1uF
C133 .1uF
.1uF
R167 360 U13 18 17 16 15 14 13 12 11
(2) DSP_BDR2 (2) DSP_BDX2 (2) DSP_BCLKX2 (2) DSP_BCLKR2 (2) DSP_BFSX2 (2) DSP_BFSR2
4.1V
20
C
10
B1 B2 B3 B4 B5 B6 B7 B8
A1 A2 A3 A4 A5 A6 A7 A8
VCC
OE NC
2 3 4 5 6 7 8 9
UART_DTR UART_RTS UART_TXD UART_CTS UART_RXD
(16) (16) (16) (16) (16)
19 1
C
GND SN74CBT3245
R68 360
McBSP2 BUFFER U14
(2) DSP_BDR1 (2) DSP_BDX1 (2) DSP_BCLKX1 (2) DSP_BCLKR1 (2) DSP_BFSX1 (2) DSP_BFSR1
3.3V
R70 10K
R77 10K
4.1V
(3) CPLD_EXP_MCBSP1n B
(3) CPLD_OB_MCBSP1n
18 17 16 15 14 13 12 11
B1 B2 B3 B4 B5 B6 B7 B8
A1 A2 A3 A4 A5 A6 A7 A8
2 3 4 5 6 7 8 9
20
VCC
OE NC
19 1
10
GND
X_DR1 X_DX1 X_CLKX1 X_CLKR1 X_FSX1 X_FSR1
(13) (13) (13) (13) (13) (13)
B
4.1V
SN74CBT3245 4.1V 3.3V
U15 18 17 16 15 14 13 12 11
(2,4) DSP_BDR0 (2,4) DSP_BDX0 (2,4) DSP_BCLKX0 (2) DSP_BCLKR0 (2) DSP_BFSX0 (2) DSP_BFSR0
3.3V
4.1V
20 10
R269 10K
A
B1 B2 B3 B4 B5 B6 B7 B8
A1 A2 A3 A4 A5 A6 A7 A8
VCC
OE NC
2 3 4 5 6 7 8 9
X_DR0 X_DX0 X_CLKX0 X_CLKR0 X_FSX0 X_FSR0
3.3V
U19
(13) (13) (13) (13) (13) (13)
18 17 16 15 14 13 12 11
19 1
4.1V
GND
20 10
B1 B2 B3 B4 B5 B6 B7 B8
A1 A2 A3 A4 A5 A6 A7 A8
VCC
OE NC
2 3 4 5 6 7 8 9
AIC23SDATAOUT (21) AIC23SDATAIN (21) BCLK (21) LRCIN LRCOUT
3.3V
GND
GND
(21) (21)
19 1
GND
A
SN74CBT3245 SN74CBT3245
SPECTRUM DIGITAL (3) CPLD_EXP_MCBSP0n
Title R168 360
McBSP0 BUFFER
A-9
SERIAL PORT BUFFER
TMS320VC5502 EVALUATION MODULE
McBSP1 BUFFER
Size B Date:
5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
8
of
21
Spectrum Digital, Inc
R71 360
4
3
2
1
3.3V ONB_D[0..31]
C52
RAMD[0..31]
(4,5) RAMD[0..31] D
C53
.1uF
.1uF
C54 .1uF
C55 .1uF
C48 .1uF
ONB_D[0..31]
(3,11,15)
C49 D
.1uF
U8
RAMD8 RAMD9 RAMD10 RAMD11 RAMD12 RAMD13 RAMD14 RAMD15 RAMD24 RAMD25 RAMD26 RAMD27 RAMD28 RAMD29 RAMD30 RAMD31 RAMD0 RAMD1 RAMD2 RAMD3 RAMD4 RAMD5 RAMD6 RAMD7 RAMD16 RAMD17 RAMD18 RAMD19 RAMD20 RAMD21 RAMD22 RAMD23
C
TMS320VC5502 EVM Module Technical Reference
B
P4 P3 L4 L3 F4 F3 C4 C3
2Vcc 2Vcc 2Vcc 2Vcc 1Vcc 1Vcc 1Vcc 1Vcc
A2 A1 B2 B1 C2 C1 D2 D1 E2 E1 F2 F1 G2 G1 H1 H2 J2 J1 K2 K1 L2 L1 M2 M1 N2 N1 P2 P1 R2 R1 T1 T2
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8 4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8
B3 B4 D3 D4 E3 E4 G3 G4 K3 K4 M3 M4 N3 N4 R3 R4
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8
OE1 OE2 OE3 OE4 1DIR 2DIR 3DIR 4DIR
A5 A6 B5 B6 C5 C6 D5 D6 E5 E6 F5 F6 G5 G6 H6 H5 J5 J6 K5 K6 L5 L6 M5 M6 N5 N6 P5 P6 R5 R6 T6 T5
ONB_D8 ONB_D9 ONB_D10 ONB_D11 ONB_D12 ONB_D13 ONB_D14 ONB_D15 ONB_D24 ONB_D25 ONB_D26 ONB_D27 ONB_D28 ONB_D29 ONB_D30 ONB_D31 ONB_D0 ONB_D1 ONB_D2 ONB_D3 ONB_D4 ONB_D5 ONB_D6 ONB_D7 ONB_D16 ONB_D17 ONB_D18 ONB_D19 ONB_D20 ONB_D21 ONB_D22 ONB_D23
C
#OE L L H
DIR L H X
OPERATION A <-- B A --> B ISOLATION
B
A4 H4 J4 T4 A3 H3 J3 T3
3.3V 3.3V 3.3V 3.3V GND
SN74LVCH32245AGKE
A
3.3V
GND
GND
GND
A
(3) ONB_XDATA_T/Rn (3) ONB_XDATA_OEn
SPECTRUM DIGITAL Title
EXPANSION DATA BUFFERS
TMS320VC5502 EVALUATION MODULE Size B Date:
5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
9
of
21
Spectrum Digital, Inc
A-10
5
5
4
3
2
1
3.3V
(2,4,5)
A[2..21]
A[2..21]
C56
C57
.1uF
.1uF
C58 .1uF
C59
C60
.1uF
.1uF
C61 .1uF
D
D
3.3V
ONB_A[2..21]
ONB_A[2..21]
(3,12,15)
U10
(2) (2,5)
CE2n CE3n
A21 A8 A9 A5 A10 A6 A7 A11 A20 A2 A3 A16 A12 A13 A14 A4 A17 A15
C
(2,4,5) (2,4,5) (2,4,5) (2,4,5) (2,4,5) (2,4,5) (2,4,5)
BE2n BE0n BE1n BE3n AREn A W En AOEn A18 A19
B
A5 A6 B5 B6 C5 C6 D5 D6 E5 E6 F5 F6 G5 G6 H6 H5 J5 J6 K5 K6 L5 L6 M5 M6 N5 N6 P5 P6 R5 R6 T6 T5
R118 360 3.3V
OE1 OE2 OE3 OE4 1DIR 2DIR 3DIR 4DIR
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8 4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8
A2 A1 B2 B1 C2 C1 D2 D1 E2 E1 F2 F1 G2 G1 H1 H2 J2 J1 K2 K1 L2 L1 M2 M1 N2 N1 P2 P1 R2 R1 T1 T2
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
B3 B4 D3 D4 E3 E4 G3 G4 K3 K4 M3 M4 N3 N4 R3 R4
ONB_A21 ONB_A8 ONB_A9 ONB_A5 ONB_A10 ONB_A6 ONB_A7 ONB_A11 ONB_A20 ONB_A2 ONB_A3 ONB_A16 ONB_A12 ONB_A13 ONB_A14 ONB_A4 ONB_A17 ONB_A15
ONB_CE2n ONB_CE3n
(3,11) (3,11)
C
ONB_BE2n ONB_BE0n ONB_BE1n ONB_BE3n ONB_AREn ONB_AWEn ONB_AOEn
(12) (12) (12) (12) (3,11) (3,11,15) (3,11,15)
ONB_A18 ONB_A19
B
#OE L L H
DIR L H X
OPERATION A <-- B A --> B ISOLATION
3.3V 3.3V 3.3V
3.3V 3.3V
SN74LVCH32245AGKE
GND
GND
GND
GND
A
A
SPECTRUM DIGITAL
EXPANSION ADDR, CONTROL BUFFERS
Title TMS320VC5502 EVALUATION MODULE
A-11
Size B Date: 5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
10
of
21
Spectrum Digital, Inc
A4 H4 J4 T4 A3 H3 J3 T3
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8
2Vcc 2Vcc 2Vcc 2Vcc 1Vcc 1Vcc 1Vcc 1Vcc
P4 P3 L4 L3 F4 F3 C4 C3
4
3
2
1
U23
56 ONB_D11 ONB_D10 ONB_D9 ONB_D8 ONB_D7 ONB_D6 ONB_D5 ONB_D4 ONB_D3 ONB_D2 ONB_D1 ONB_D0
D
2 3 4 5 6 7 9 10 11 12 13 14 55
(13)
X_ARDY
X_ARDY
1OE
NC 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 1B11 1B12
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 1A11 1A12
X_D[0..31]
X_D[0..31]
(13)
1 X_D11 X_D10 X_D9 X_D8 X_D7 X_D6 X_D5 X_D4 X_D3 X_D2 X_D1 X_D0
54 53 52 51 50 48 47 46 45 44 43 42
D
2OE 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12
2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 2A12
41 40 39 37 36 35 34 33 32 31 30 29
X_REn X_W En X_OEn X_CE3n X_CE2n
3.3V
(13) (13) (13) (13) (13)
R79 4.7K
C
DSP_ARDY
DSP_ARDY
(2)
GND GND GND GND
15 16 18 20 21 22 23 24 25 26 27 28
(3,10) ONB_AREn (3,10,15) ONB_AWEn (3,10,15) ONB_AOEn (3,10) ONB_CE3n (3,10) ONB_CE2n
C
C137 .1uF
VCC
ONB_D[0..31]
(3,9,15) ONB_D[0..31]
17
5V
8 19 38 49
R115 360
CBTD16211DGGR
5V 17
C121
56
XDATA_OEn ONB_D31 ONB_D30 ONB_D29 ONB_D28 ONB_D27 ONB_D26 ONB_D25 ONB_D24
B
2 3 4 5 6 7 9 10 11 12 13 14 55
(3,12) XCTL_OEn ONB_D23 ONB_D22 ONB_D21 ONB_D20 ONB_D19 ONB_D18 ONB_D17 ONB_D16 ONB_D15 ONB_D14 ONB_D13 ONB_D12
A
R116 360
15 16 18 20 21 22 23 24 25 26 27 28
NC
1OE 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 1A11 1A12
1
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 1B11 1B12
54 53 52 51 50 48 47 46 45 44 43 42
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12
41 40 39 37 36 35 34 33 32 31 30 29
X_D31 X_D30 X_D29 X_D28 X_D27 X_D26 X_D25 X_D24
B
2OE 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 2A12
X_D23 X_D22 X_D21 X_D20 X_D19 X_D18 X_D17 X_D16 X_D15 X_D14 X_D13 X_D12
5V
3.3V
5V GND
3.3V
GND
A
GND GND GND GND
(3)
SPECTRUM DIGITAL Title
8 19 38 49
TMS320VC5502 EVM Module Technical Reference
.1uF
VCC
U5
TMS320VC5502 EVALUATION MODULE CBTD16211DGGR Size B Date:
5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
11
of
21
Spectrum Digital, Inc
A-12
5
5
4
3
2
1
X_A[2..21]
X_A[2..21]
(13)
5V
C122 .1uF D
ONB_A[2..21]
U26
VCC
(3,10,15) ONB_A[2..21]
17
D
56 ONB_A21 ONB_A20 ONB_A19 ONB_A18 ONB_A17 ONB_A16 ONB_A15 ONB_A14 ONB_A13 ONB_A12 ONB_A11 ONB_A10
2 3 4 5 6 7 9 10 11 12 13 14 55
ONB_A9 ONB_A8 ONB_A7 ONB_A6 ONB_A5 ONB_A4 ONB_A3 ONB_A2
C
ONB_BE3n ONB_BE2n ONB_BE1n ONB_BE0n
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 1A11 1A12
1
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 1B11 1B12
54 53 52 51 50 48 47 46 45 44 43 42
X_A21 X_A20 X_A19 X_A18 X_A17 X_A16 X_A15 X_A14 X_A13 X_A12 X_A11 X_A10
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12
41 40 39 37 36 35 34 33 32 31 30 29
X_A9 X_A8 X_A7 X_A6 X_A5 X_A4 X_A3 X_A2
(2) DSP_CLKOUT (2) DSP_IACKn (2) INT0n (2) INT1n (2) INT2n (2) INT3n
4.1V
18 17 16 15 14 13 12 11
B1 B2 B3 B4 B5 B6 B7 B8
A1 A2 A3 A4 A5 A6 A7 A8
2 3 4 5 6 7 8 9
20
VCC
OE NC
19 1
10 C144 .1uF
X_CLKOUT X_IACKn X_IN T0n X_IN T1n X_IN T2n X_IN T3n
(13) (13) (13) (13) (13) (13)
GND SN74CBT3245
2OE 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 2A12
C
X_BE3n X_BE2n X_BE1n X_BE0n
(13) (13) (13) (13)
8 19 38 49
GND GND GND GND
(10) (10) (10) (10)
15 16 18 20 21 22 23 24 25 26 27 28
U33 NC
1OE
CBTD16211DGGR
B
B
(3,11) XCTL_OEn
5V
3.3V
GND
GND
5V
4.1V
4.1V A
A
SPECTRUM DIGITAL Title TMS320VC5502 EVALUATION MODULE
A-13
EXPANSION ADDR, CONTROL BUFFERS
Size B Date:
5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
12
of
21
Spectrum Digital, Inc
3.3V
4
3
2
MEMORY INTERFACE (12)
1
PERIPHERAL INTERFACE
X_A[2..21] POS_12V 5V 5V
D
P1A
P1B
5V
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
C
5V 3.3V_DB
X_A13 X_A11 X_A9 X_A7 5V X_A5 X_A3 X_BE3n X_BE1n
(12) (12)
X_D31 X_D29 X_D27 X_D25 X_D23 X_D21 X_D19 X_D17 X_D15 X_D13 X_D11 X_D9 X_D7 X_D5 X_D3 X_D1 X_REn X_OEn X_CE3n
(11) (11) (11)
MIN_12V 5V 3.3V_DB
P2B
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
5V X_A20 X_A18 X_A16 X_A14 X_A12 X_A10 X_A8 X_A6 5V X_A4 X_A2 X_BE2n X_BE0n
(12) (12)
X_D30 X_D28 X_D26 X_D24 X_D22 X_D20 X_D18 X_D16 X_D14 X_D12 X_D10 X_D8 X_D6 X_D4 X_D2 X_D0 X_W En X_ARDY X_CE2n
(11) (11) (11)
5V 5V X_SCL
(2)
X_CLKX0 X_FSX0
(8) (8)
X_CLKR0 X_FSR0
(8) (8)
X_CLKX1 X_FSX1
(8) (8)
X_CLKR1 X_FSR1
(8) (8)
X_TOUT0 X_INT0n X_TOUT1
(3) (12) (3)
X_INT1n
(12)
X_RESETn
(3)
DC_CNTL1 DC_STAT1 X_INT3n
(3) (3) (12)
DC_DETECTn (3)
SFM-140 SFM-140
SFM-140
D
5V 5V X_SDA
(2)
X_DX0
(8)
X_DR0
(8)
X_DX1
(8)
X_DR1
(8)
X_TIN0 X_IN T2n X_TIN1
(3) (12) (3)
X_IACKn
(12)
DC_CNTL0 DC_STAT0
(3) (3)
X_CLKOUT
(12)
C
SFM-140
3.3V
B
(11)
3.3V_DB
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
B
R67 10K
X_D[0..31]
3.3V RN17 DC_PORSTn
TPS76733QPWP U16
X_INT0n X_INT1n X_INT2n X_INT3n
(3)
3.3V_DB
3.3V 5V
5V
(3) DC_DETECTn C66 RPACK4-10K 5 6 7 8
.1uF
A
DC_DETECTn
R49 R50
IN1 IN2
5 3
ENn GND
4 8
NC1 NC2
OUT1 OUT2
14 13
RESET/PG FB
16 15
NC3 NC4
10K
1 2 3 4
8 7 6 5 RPACK4-10K
3.3V 3.3V_DB
17 18
5V
3.3V HS/GND1 HS/GND2 HS/GND3 HS/GND4 HS/GND5 HS/GND6 HS/GND7 HS/GND8 PWRPAD
RN18 4 3 2 1
DC_CNTL0 DC_CNTL1 DC_STAT0 DC_STAT1
6 7
+
3.3V_DB
C107 10uF
5V A
1 2 9 10 11 12 19 20 21
TMS320VC5502 EVM Module Technical Reference
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
X_A21 X_A19 X_A17 X_A15
P2A 3.3V_DB
SPECTRUM DIGITAL
4.7K Title
X_ARDY GND
TMS320VC5502 EVALUATION MODULE
GND Size B
DB MEMORY/PERIPERAL INTERFACES
Date: 5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
13
of
21
Spectrum Digital, Inc
A-14
5
5
4
3
5V
2
1
5V 3.3V_DB
3.3V_DB
P3A
P3B 3.3V 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
D
C
X_CLKX2 X_FSX2 X_DX2 DSP_GPIO4
(8) (8) (8) (2,3,7)
HR/W HPIENA DSP_GPIO6 HDS2
(2) (2) (2,7) (2)
HRDY DSP_GPIO0
(2) (2,3,7)
HC1
(2)
HCNTL1
(2)
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
HD7 HD5 HD3 HD1 DSP_HOLDAn (2) NMIn (2) DSP_XF (2)
X_CLKR2 X_FSR2 X_DR2
(8) (8) (8)
HCNTL0 HCS DSP_GPIO7 HDS1
(2) (2) (2,7) (2)
HINT DSP_GPIO1
(2) (2,3,7)
HC0
(2)
R75 NO POP
(2)
D
HPIENA R76 2K
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7
HD6 HD4 HD2 HD0 DSP_HOLDn DSP_GPIO2 HPI_RESETn
C
HD[0..7]
(2) (2,3,7) (3)
HD[0..7]
(2)
SFM-140
SFM-140
JP5 (2)
DSP_XF
1 2 HEADER 2x1
B
B
5V
5V 3.3V_DB
4.1V 3.3V GND 3.3V
GND
3.3V
A
A
SPECTRUM DIGITAL
DC HOST PORT CONNECTOR
Title TMS320VC5502 EVALUATION MODULE
A-15
Size B Date: 5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
14
of
21
Spectrum Digital, Inc
3.3V_DB 4.1V
4
3
ONB_D[0..31]
(3,9,11) ONB_D[0..31]
2
1
ONB_D[0..31]
ONB_A[2..21]
(3,10,12) ONB_A[2..21]
3.3V
3.3V C14
D
C142
.1uF ONB_A21 ONB_A20 ONB_A19 ONB_A18 ONB_A17 ONB_A16 ONB_A15 ONB_A14 ONB_A13 ONB_A12 ONB_A11 ONB_A10 ONB_A9 ONB_A8 ONB_A7 ONB_A6 ONB_A5 ONB_A4 ONB_A3 ONB_A2 3.3V
C
3.3V
R10
U6
9 16 17 48 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
47 26 28 11 12
BYTE CE OE WE RESET
27 46
VSS VSS
VCC DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 RY/BY
R11
10K
D
.1uF
U4 ONB_A21 ONB_A20 ONB_A19 ONB_A18 ONB_A17 ONB_A16 ONB_A15 ONB_A14 ONB_A13 ONB_A12 ONB_A11 ONB_A10 ONB_A9 ONB_A8 ONB_A7 ONB_A6 ONB_A5 ONB_A4 ONB_A3 ONB_A2
37 45 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29
ONB_D15 ONB_D14 ONB_D13 ONB_D12 ONB_D11 ONB_D10 ONB_D9 ONB_D8 ONB_D7 ONB_D6 ONB_D5 ONB_D4 ONB_D3 ONB_D2 ONB_D1 ONB_D0 3.3V
15
R155 NC1 NC2 NC3
10 13 14
10K
9 16 17 48 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
47 26 28 11 12
BYTE CE OE WE RESET
27 46
VSS VSS
VCC DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
37 ONB_D31 ONB_D30 ONB_D29 ONB_D28 ONB_D27 ONB_D26 ONB_D25 ONB_D24 ONB_D23 ONB_D22 ONB_D21 ONB_D20 ONB_D19 ONB_D18 ONB_D17 ONB_D16
45 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29
RY/BY
15
NC1 NC2 NC3
10 13 14
C
10K AM29LV400B FLASH
TMS320VC5502 EVM Module Technical Reference
(3)
AM29LV400B FLASH
FLASH_CEn
(3,10,11) ONB_AOEn (3,10,11) ONB_AWEn B
(2,3)
DSP_RSTn
B
3.3V
3.3V GND
3.3V GND
A
A
SPECTRUM DIGITAL Title TMS320VC5502 EVALUATION MODULE Size B Date: 5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
15
of
21
Spectrum Digital, Inc
A-16
5
5
4
D
3
3.3V
2
1
D
3.3V
C150 .1uF
(8) (8) (8)
UART_RTS UART_TXD UART_DTR
(8) (8)
UART_CTS UART_RXD
7 8 9
UART_CTS UART_RXD
R84 NO POP
10 11 12 13 14
R85 NO POP
C
C149 .1uF
DIN1 DIN2 DIN3 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5
5 23
EN STBY
6 24
C1+ C1-
2 4
C2+ C2-
28 26
C148
VCC
U32
UART_RTS UART_TXD R86 NO POP
3
R83 10K
DOUT1 DOUT2 DOUT3 RIN1 RIN2 RIN3 RIN4 RIN5
C3+ C3-
SN75LV4737A
.1uF
3.3V
C
CONNECTOR DB9
C151
VSS
1
25 C147
GND
C146
19 18 17 16 15
1 6 2 7 3 8 4 9 5
RXD RTS TXD CTS
.1uF VDD
.1uF
P4
22 21 20
.1uF
27
R78 10K
B
PC
NAME
TARGET IN/OUT
NAME
1
CARRIER DETECT
IN
OUT
NOT USED
1
2
RX DATA
IN
OUT
TX DATA
2
3
TX DATA
OUT
IN
RX DATA
3
4
DTR
OUT
IN
NOT USED
4
5
GND
GND
GND
GND
5
6
DSR
IN
OUT
NOT USED
6
7
RTS
OUT
IN
CTS
7
8
CTS
IN
OUT
RTS
8
9
RING INDICATOR
IN
OUT
NOT USED
9
PC IN/OUT
TARGET
B
A
3.3V GND
A
3.3V
SPECTRUM DIGITAL
GND Title
TMS320VC5502 EVALUATION MODULE
A-17
Size B Date: 5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
16
of
21
Spectrum Digital, Inc
3.3V
4
3
2
1
DSP JTAG HEADER
3.3V
J7 XDS_TMS XDS_TDI XDS_TVD XDS_TDO XDS_TCK_RTN XDS_TCK XDS_EMU0
D
1 3 5 7 9 11 13
2 4 8 10 12 14
XDS_TRST#
XDS_TRST#
DSP_TRST#
(2)
D
XDS_EMU1
XDS_EMU1
DSP_EMU1
(2)
TSW-107 R99
XDS_EMU0
DSP_EMU0
3.3V
(2)
NO POP
C113 NO POP
33
XDS_TDO XDS_TDI
DSP_TDO
(2)
DSP_TDI
(2)
DSP_TMS
(2)
C75 0.1uF 5
R64
XDS_TCK
U28
1
R65
4 XDS_TMS
33
DSP_TCK
2
(2)
3
SN74LVC1G32 C
C
3.3V
5
C114 0.1uF
U27
1 33
SN74LVC1G32 3
TMS320VC5502 EVM Module Technical Reference
R66
4 2
B
B
XDS_TCK_RTN
3.3V GND
GND 3.3V
JTAG INTERFACE
A
A
SPECTRUM DIGITAL Title TMS320VC5502 EVALUATION MODULE Size B Date: 5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
17
of
21
Spectrum Digital, Inc
A-18
5
5
4
3.3V
3
2
1
L12 BEAD
U20 C143 .1uF
OFFn VCC
C64 .001uF
8
Analog R128
4
GND
CLK
5
CODEC_SYSCLK
100 C154
D
(8,21) BCLK (8,21) LRCIN (8,21) AIC23SDATAIN (8,21) AIC23SDATAOUT (8,21) LRCOUT
12MHZ NO POP
3.3V
DATA_BCLK DATA_SYNCIN DATA_DIN DATA_DOUT DATA_SYNCOUT
(2,4,6,21) DSP_SDA R129
CTL_DATA CTL_CLK CTL_CS CTL_MODE
NO POP
D
AIC3.3V
GND
3.3V Analog R119 0
C123
R120 0
5
.1uF
(2,4,6)
U21 R139
1
DSP_SCL
33
4 2
C
C
3
SN74LVC1G32
3.3V
L13 BEAD U29 C116
C65
.1uF
.001uF
OFFn VCC
8
GND
5
R100 4
CLK
DSP_CLKIN
DSP_CLKIN
100
(2,3)
C153 20MHZ NO POP
R101
0 5V
B
3.3V
B
5V
Y2 3.3V
S1
S0 0
0
OPEN
0 OPEN
NO POP
4X
100 MHz
5.33X
133.25 MHz
1
5X
125 MHz
0
2.5X
62.5 MHz
2X
50 MHz
OPEN OPEN OPEN
1
3.33X
83.25 MHz
1
0
6X
150 MHz
1
OPEN
3X
75 MHz
1
1
8X
200 MHz
A
C155 NO POP
R109 10K
3.3V
C156 NO POP
GND
GND
U31
R106 NO POP
1
X1/ICLK
7 6
S1 S0
X2
8
CLK REF
5 4
R102
3 R108 NO POP
GND
VDD
DSP_ECLKIN
(2)
33
3.3V
R103
2
1k
R107 1K
ICS512
A
C145
SPECTRUM DIGITAL
.1uF Title
TMS320VC5502 EVALUATION MODULE
A-19
Size B
Hierarcharical Blocks 5
4
3
Date: 2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
18
of
21
Spectrum Digital, Inc
0
MULT
4
3
2
1
D
D
CVCC
C77 .1uF
C
C79
C81
.1uF
C83
.1uF
C85
.1uF
C87
.01uF
C89
.01uF
+ C95
C91
.01uF
.01uF
22uF
C
3.3V
+ C109
C78 .1uF
C80 .1uF
C82 .1uF
C84 .1uF
C86
C88
.01uF
.01uF
C90 .01uF
C92 .01uF
C94 .01uF
+ C96
C93 .01uF
10uF
+ C110
10uF
+ C50
+ C51
10uF
+ C62
10uF
+ C63
10uF
10uF
10uF
TMS320VC5502 EVM Module Technical Reference
B
B
3.3V
3.3V CVCC
CVCC
GND
GND
A
A
DSP DECOUPLING CAPS
SPECTRUM DIGITAL Title TMS320VC5502 EVALUATION MODULE Size B Date:
5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
19
of
21
Spectrum Digital, Inc
A-20
5
5
4
3
2
1
3.3V
EXTERNAL POWER PLU G
+3.3V & +1.2V DIGITAL VOLTAGE REGULA
TOR R61
5V
5V
10K
(11,12,13,14)
5V_IN D
J5
PON3.3VRSn
U25 R52
3 2 1
0
5V
5V
3 4
C105 +
JP2 RASM712
2
10uF
1 2
SWITCHCRAFT RAPC712 PLUG
C70
+
HEADER 2x1
C104 47uF
0.1uF
C71
1
Vin Vin
+
EN GND
C74 10uF
C103 NO POP
8
RESET
3.3V
(3)
D
5 6 7
Vout Vout SENSE
TPS76733QD
0.1uF R58 150
MIN_12V
POS_12V
3.3V
J6
+5 GND -12 +12
DS7 Green Power-On
4 3 2 1
R81 10K R97 PONCOREn
4-pin Molex C
ALTERNATE EXTERNAL POWE R
1K
(3) C
C108 NO POP
(DO NOT POPULATE)
L11
BEAD
JP3 HEADER 2x1
1 2
CVCC U34 1 +C98
INPUT POWER
6
10uF 6.3V
8 PWM/MIX
7 2 4
C101 0.1uF
3
IN
L10 L
9
LX2
5
FBVCC2
10uH
R51 R54 100K, 1%
C99
ILIM
Rs
47pF
EN FB
NO POP
R55
R57 53.2K, 1%
Q1 BSS138
Rref
+
+C100
NO POP
SYNC FC PowerG
+
C118 0.1uF
111K 1%
C119 22uF 3.3V
47uF 6.3V
TPS62000 B
C106 22uF
R56 100K
10
GND PGND
0
R60
10K
B
CBT VOLTAGE DIVIDE R 5V
4.1V
C111 0.1uF
R69 1
(3) CORE_V_CTL D7 LM4040DCIM3-4.1 5V
3.3V
2
4.1V
4.1V
5V
3.3V
CVCC GND
DAUGHTERCARD STANDOFF GROUNDING
GROUND TEST POINTS
M1 125_PH
A
TP1
TP2
TP4
TP3
TP5
M2 125_PH
M3 125_PH
M4 125_PH
A
KEEP TRACES A MINIMUM OF 0.070 INCHES FROM THESE HOLES.
A-21
3.3V
5V
(11,12,13,14)
SPECTRUM DIGITAL Title TMS320VC5502 EVALUATION MODULE Size B
CVCC
Date: 5
4
3
GND
CVCC
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
20
of
21
Spectrum Digital, Inc
1.5K
Selectable core voltage option enable
4
3
L1 HZ0805E601R J1
2
1
(18) CODEC_SYSCLK R25 2.0K
3
3.3VA
4 2 1
C15 +
R26
4.7K
Stereo In 1uF R28 NO POP
10uF
+
C16 NO POP
L2 HZ0805E601R
C19
C21
C20 NO POP
C17 NO POP
C23 220uF +
C18 NO POP
R27 0
C22 0.1uF
47pF +
10uF
4 2 1
C25
PHONES
C24 220uF C26 0.1uF
J2
L4 HZ0805E601R
C30 NO POP R34
10uF 4.7K
R35
4 2 1
C31
U7
4.7K C34 470nF
Stereo In L5 HZ0805E601R
R38 0
R36 4.7K
R37 4.7K
C35 C36 NO POP NO POP
C
SPIMODE AIC23LRCIN
AIC3.3V AIC23CS
8 7 6 5
PW Package
14 8 16
AVdd HPVdd VMID
17 18 20 19
MIC_BIAS MIC_IN LLINE_IN RLINE_IN
23 24 22
SDIN SCLK MODE
4 5 7 3
RN14 1 2 3 4
L3 HZ0805E601R C28 NO POP
C27 NO POP
C32 0.1uF
C33 470nF
3
+
C29 NO POP
21
AGND HPGND
15 11
XTI/MCLK XTO CLKOUT
25 26 2
RHPOUT LHPOUT
10 9
RLINE_OUT LLINE_OUT
13 12
DIN LRCIN LRCOUT BCLK CS
6
BVdd DVdd DGND
1 27 28
TLV320AIC23
R32 47K
R31 0
R33 47K
C37 470nF C38 470nF
RLINE_OUT LLINE_OUT
DOUT
C
C39 NO POP
AIC3.3V R39
L6 HZ0805E601R
C42
+
R40
100
10uF
PHONES L7 HZ0805E601R
CTL_MODE
R41 47K
(2,4,6) CTL_DATA
TMS320VC5502 EVM Module Technical Reference
(18)
CTL_CLK
(18)
CTL_CS
J3
4 2 1
C43 0.1uF
RPACK4-10K (18)
C40 NO POP
100 3
C41 0.1uF
D
J4
3
+
D
R42 47K
C44 NO POP
C45 NO POP
R43 0
Control Port
B
B
AIC3.3V RN15 1 2 3 4
8 7 6 5
AIC3.3V L8
R44
RPACK4-10K (8) DATA_DIN (8) DATA_SYNCIN (8) DATA_BCLK (8) DATA_DOUT
3.3VA HZ0805E601R
RN16 1 2 3 4
2
+
8 7 6 5
+
C46
C47
10uF
10uF
AIC3.3V RPACK4-33 R45
R12
0
33
(8) DATA_SYNCOUT
AIC3.3V TP11
A
A
SPECTRUM DIGITAL
GND L9
HZ0805E601R
Title TMS320VC5502 EVALUATION MODULE Size B Date:
5
4
3
2
Document Number 506662 Monday, May 19, 2003
Rev A Sheet 1
21
of
21
Spectrum Digital, Inc
A-22
5
8
7
6
5
4
3
2
1
REVI SI ONS REV
DESCRI PTI ON
DATE
APPROVED
NOTES. UNLESS OTHERWI SE SPECI FI ED
1.
D
D
I 2C ADDRESSES ADS7823
10010- A1- A0- RW
C
C
SPARES
B
B
DATE 07/ 01/ 2001 DATE
ENGR R. R. P. APVD ENGR
DATE 07/ 01/ 2001 DATE
QA
DATE
APVD MFG
DATE
S P E C T R U M D I GI T A L I N C OR P OR A T E D LOGI C DI AGRAM UNI VERSAL KEYPAD DI SPLAY FOR TMS320VC55XX
REVI SI ON STATUS OF SHEETS
A-23
REV SHT REV SHT REV SHT REV SHT 8
7
XXXXXX NEXT ASSEMBLY A 1
A 2 6
A 3
A 4
A 5
A 6 4
CopyRi ght 2001
XXXXX RLSE
DATE
APVD CUST
DATE
USED ON
APPLI CATI ON 5
A
3
SI ZE B SCALE NONE 2
DRAWI NG NUMBER 505747- 0001
REV A
SHEET
1 1
OF
6
Spectrum Digital, Inc
A
DWN R. R. P. CHK
7
6
3 .3 V
5
4
3
2
1
3 .3 V
R2 1 0K PO T
POT1
1
2
2
POT2
1
R1 1 0K PO T
3
D
3
D
R8
5 .1 R14
5.1
C
C
U2 POT1 C6 1 0 0 nF
1 2 3 4
V RE F A IN A0 V SS
V CC S CL S DA A1
8 7 6 5
A D S7 82 3
U5
3.3 V (3 ,4)
+
C5 1 uF
A 0 IN
JOG W HE E L 3. 3 V
C4 1 00 n F
1 2 3 4
V RE F A IN A0 V SS
C25 10 0n F
(3 ,4,5 ,6 )
S DA SCL
(3) (3)
TMS320VC5502 EVM Module Technical Reference
R13
POT2 3 .3 V
C 22 1 0 0 nF
1 2 3 4
V RE F A IN A0 V SS
C 23 1 0 0n F
3 .3 V
R3
5 .1
U1 V CC S CL S DA A1
A D S7 82 3
( 3) ( 3)
3. 3 V +
C24 1u F
S DA S CL
5 .1
U4 B
8 7 6 5
A D S 7 82 3
3 .3 V ( 3) ( 3)
VC C SC L SD A A1
8 7 6 5
1 2 3 4
3.3 V ( 3 ,5 )
A 1IN
+
C20 10 0n F
C 21 1 uF
C3 1 00 nF
S DA SCL
(3 ) (3 )
V R EF A IN A0 VSS
V CC S CL S DA A1
8 7 6 5
B
3 .3 V +
C2 1u F
A D S 7 8 23
C1 1 00 nF
SDA SC L
A
A
3.3 V
3 . 3V
S P E C TR U M D IG I T A L IN C O R P O R A T E D
3 .3 V
C o pyR igh t 20 0 1 G ND
8
7
6
5
4
T itle
GND
U N I V E R S A L K E Y P A D /D I S P L A Y
3
S ize B
D oc um e nt N u m b er 5 0 5 7 4 7 -00 01
D ate :
W ed n esda y, A p ril 16 , 2 0 0 3 2
R ev A S he e t
of
2 1
6
Spectrum Digital, Inc
A-24
8
8
7
6
5
4
3
2
1
NOT POPULATED 3 .3 V P2
D
( 5) ( 5) ( 5) ( 5)
C O LU M N 0 C O LU M N 1 C O LU M N 2 C O LU M N 3
1 3 5 7 9 11 13
C OLUM N0 C OLUM N1 C OLUM N2 C OLUM N3
2 4 6 8 10 12 14
ROW 2 ROW 1 ROW 0
RO W2 RO W1 RO W0
(5) (5) (5)
D
3 .3 V
3.3V
H EA DE R 7 X2
U 6A
14 1 8 7 6 5
3 2
3 . 3V
R N1 10 K O H M
7
T C 7 4 LV X 0 8 /S O _1
1 2 3 4
U 6B 4 6
RN2
C
5
4 3 2 1
L c dS I L cdA 0 LcdS CK DS P_ RS n
5 6 7 8
T C 7 4 LV X 0 8 /S O _1
33 O HM
R N5 1 2 3 4
U6C 9
8 7 6 5
L cd S IK Y B D (6 ) L cd A 0 K Y B D (6 ) L cd S C K K Y B D (6 ) D S P _ R S n K Y B D (6 )
C
33 O H M
8 10 T C 7 4L V X0 8/S O _ 1
3.3V
U 6D P1 R6 10 K
B
(2 )
S DA
(2 )
SCL
R5 1 0K
(2 ,4 )
R7
33
R4
33
3 .3 V A 0 IN L cd S I D S P_RS n
1 3 5 7 9 11 13 15
12 3. 3 V A 1 IN L cdA 0 Lc dS C K
2 4 6 8 10 12 14 16
11
(2,4 ,5,6 ) (2,5 )
13 T C 7 4 LV X 0 8 /S O _1
B
H E AD ER 8X 2
GN D A
S P E C TR U M D IG I T A L IN C O R P O R A T E D C o pyR igh t 20 0 1 T itle U N I V E R S A L K E Y P A D /D I S P L A Y 3 .3 V
A-25
8
7
6
5
4
3 .3 V
3.3 V
3
S ize B
D oc um e nt N u m b er 5 0 5 7 4 7 -00 03
D ate :
W ed n esda y, A p ril 16 , 2 0 0 3 2
R ev A S he e t
of
3 1
6
Spectrum Digital, Inc
G ND
A
7
6
5
4
3
2
1
D
D
3 .3 V
C 32 1 00 nF
3 .3 V +
C 31 1 uF
C30 1 0 0n F 2
R 18 8 0 .6 K 4
-
3
+
R 19 C
R 20
U7 1
A 0 IN
T L V 27 2 1
(2 ,3 )
33
C
5
33
S1
. .
TMS320VC5502 EVM Module Technical Reference
B SW 1 SW 2 SW 1 Com A
.
R 16 8 0 . 6K
C27 NO PO P
R15 3 9 . 2K
C 26 NO PO P
R17 1 1. 3 K
. .
E V Q W K A 00 1 Jog D ia l
C 29 NO PO P
. . .
C28 NO PO P
B
B
GND
GN D
A
A
S P E C TR U M D IG I T A L IN C O R P O R A T E D C o pyR igh t 20 0 1 T itle U N I V E R S A L K E Y P A D /D I S P L A Y 3 .3 V
8
7
6
5
4
3 .3 V
3 .3 V
3
S ize B
D oc um e nt N u m b er 5 0 5 7 4 7 -00 03
D ate :
W ed n esda y, A p ril 16 , 2 0 0 3 2
R ev A S he e t
4
of 1
6
Spectrum Digital, Inc
A-26
8
5
4
3
2
1
R N3 1 2 3 4
C OLUM N0
8 7 6 5
C O L U M N 0 (3) C OLUM N1 C OLUM N2
R11 33 O H M
3 .3 V
D
C OLUM N3
3 .3 V
C O L U M N 1 (3)
C8
C O L U M N 2 (3)
1 0 0n F
C O L U M N 3 (3)
D
+
C 17 1 0 0n F
8 0 . 6K 2
C 18 1 uF
C19
R12
A 1 IN K Y B D A 1 IN K Y B D
N O PO P
4
-
3
+
R10
U3 1
A 1IN
T L V 27 21 33
(3 )
R 29
3 9 . 2K
R 28
2 6 . 1K
R 27
4 7 . 5K
R 26
1 8 . 2K
SW 1
5
33
ROW 0
RO W0
P U S H B U TT O N
(3 )
SW 2
ROW 1
RO W1
P U S H B U TT O N C
(3 )
C
SW 3
ROW 2
RO W2
P US HB UTT O N SW 4
P US HB UTT O N R25
60 .4 K
SW 5 P U S H B U TT O N
R23
11 .3 K
SW 6
P U S H B U TT O N B
RN4 4 3 2 1
R24
80 .6 K
R22
4. 9 9 K
5 6 7 8
B
SW 7
P U S H B U TT O N SW 8
P U S H B U TT O N
R 21
10 0K
SW 9
P US HB UTT O N
A
A
S P E C TR U M D IG I T A L IN C O R P O R A T E D 3.3 V
3 .3 V
3 .3 V G ND
A-27
5
4
3
GND
2
C o pyR igh t 20 0 1 T itle U N I V E R S A L K E Y P A D /D I S P L A Y S ize B
D oc um e nt N u m b er 5 0 5 7 4 7 -00 03
D ate :
W ed n esda y, A p ril 16 , 2 0 0 3
R ev A S he e t 1
5
of
6
Spectrum Digital, Inc
33 OHM
7
6
5
4
3
2
1
D
D
Ser i al LCD 3 .3 V +C 9
1uF 1 6V
+C 1 6
+C 15
+C 1 4
+C 1 3
1uF 1 6V
1 uF 1 6V
1 uF 16 V
1uF 16V
J1 LC D_ V5 LC D_ V4 LC D_ V3 LC D_ V2 LC D_ V1
C
L C D _C A P 2+ L C D _C A P 2L C D _C A P 1L C D _C A P 1+ L C D _V O U T
+C 1 0
1uF 1 6V 3.3V C11
L C D _S I L C D _S C K C7 1 00 nF
1 uF 16 V
L C D _A 0
+
zLC D_ CS
C
LC D1
C12 +
TMS320VC5502 EVM Module Technical Reference
B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 uF 16 V
R9 33
B
(3 ) L c d S IK Y B D (3 ) L cd S C K K Y B D (3 ) Lc dA 0 K Y B D ( 3) D S P _R S n K Y B D
A
A
S P E C TR U M D IG I T A L IN C O R P O R A T E D 3 . 3V
3 . 3V
3. 3 V GN D
8
7
6
5
4
G ND
3
C o pyR igh t 20 0 1 T itle U N I V E R S A L K E Y P A D /D I S P L A Y S ize B
D oc um e nt N u m b er 5 0 5 7 4 7 -00 03
D ate :
W ed n esda y, A p ril 16 , 2 0 0 3 2
R ev A S he e t
of
6 1
6
Spectrum Digital, Inc
A-28
8
Appendix B Mechanical Information
This appendix contains the mechanical information about the TMS320VC5502 EVM and Keypad/display Module produced by Spectrum Digital.
Topic B.1 B.2
Page TMS320VC5502 EVM Mechanical Information Keypad/display Module Mechanical Information
B-2 B-3
B-1
THIS DRAWING IS NOT TO SCALE
Spectrum Digital, Inc
B-2
TMS320VC5502 EVM Module Technical Reference
THIS DRAWING IS NOT TO SCALE
Spectrum Digital, Inc
B-3
Spectrum Digital, Inc
B-4
TMS320VC5502 EVM Module Technical Reference
Printed in U.S.A., May 2003 506665-0001 Rev. A
