Transcript
PD-91896F
IRF1404 l l l l l l l
Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175°C Operating Temperature Fast Switching Fully Avalanche Rated Automotive Qualified (Q101)
HEXFET® Power MOSFET D
VDSS = 40V RDS(on) = 0.004Ω
G
ID = 202A
S
Description Seventh Generation HEXFET® Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications including automotive. The TO-220 package is universally preferred for all automotive-commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry.
TO-220AB
Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @T C = 25°C VGS EAS IAR EAR dv/dt TJ TSTG
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting Torque, 6-32 or M3 screw
Max.
Units
202 143 808 333 2.2 ± 20 620 See Fig.12a, 12b, 15, 16 1.5 -55 to + 175 -55 to + 175 300 (1.6mm from case ) 10 lbf•in (1.1N•m)
A W W/°C V mJ A mJ V/ns °C
Thermal Resistance Parameter RθJC RθCS RθJA
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Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
Typ.
Max.
Units
––– 0.50 –––
0.45 ––– 62
°C/W
1 10/10/03
IRF1404 Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on) VGS(th) gfs
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance
Qg Qgs Qgd td(on) tr td(off) tf
Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time
Min. 40 ––– ––– 2.0 76 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– –––
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss Coss Crss Coss Coss Coss eff.
Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance
––– ––– ––– ––– ––– –––
V(BR)DSS ∆V(BR)DSS/∆TJ
IGSS
Typ. Max. Units Conditions ––– ––– V VGS = 0V, ID = 250µA 0.039 ––– V/°C Reference to 25°C, ID = 1mA 0.0035 0.004 Ω VGS = 10V, ID = 121A ––– 4.0 V VDS = 10V, ID = 250µA ––– ––– S VDS = 25V, ID = 121A ––– 20 VDS = 40V, VGS = 0V µA ––– 250 VDS = 32V, VGS = 0V, TJ = 150°C ––– 200 VGS = 20V nA ––– -200 VGS = -20V 131 196 ID = 121A 36 ––– nC VDS = 32V 37 56 VGS = 10V 17 ––– VDD = 20V 190 ––– ID = 121A ns 46 ––– RG = 2.5Ω 33 ––– RD = 0.2Ω D Between lead, 4.5 ––– 6mm (0.25in.) nH G from package 7.5 ––– and center of die contact S 5669 ––– VGS = 0V 1659 ––– pF VDS = 25V 223 ––– ƒ = 1.0MHz, See Fig. 5 6205 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz 1467 ––– VGS = 0V, VDS = 32V, ƒ = 1.0MHz 2249 ––– VGS = 0V, VDS = 0V to 32V
Source-Drain Ratings and Characteristics IS ISM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol ––– ––– 202 showing the A G integral reverse ––– ––– 808 S p-n junction diode. ––– ––– 1.5 V TJ = 25°C, IS = 121A, VGS = 0V ––– 78 117 ns TJ = 25°C, IF = 121A ––– 163 245 nC di/dt = 100A/µs Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
Starting TJ = 25°C, L = 85µH RG = 25Ω, IAS = 121A. (See Figure 12)
ISD ≤ 121A, di/dt ≤ 130A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C
2
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS
Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A.
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IRF1404 1000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V TOP
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
1000
100
100
10
4.5V
20µs PULSE WIDTH TJ = 25 °C
1 0.1
1
10
4.5V
10
20µs PULSE WIDTH TJ = 175 °C
1 0.1
100
1
10
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance (Normalized)
I D , Drain-to-Source Current (A)
1000
TJ = 25 ° C TJ = 175 ° C
100
10
V DS= 25V 20µs PULSE WIDTH 4
5
6
7
8
9
10
11
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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12
2.5
ID = 202A
2.0
1.5
1.0
0.5
0.0 -60 -40 -20 0
VGS = 10V 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( ° C)
Fig 4. Normalized On-Resistance Vs. Temperature
3
IRF1404 10000
VGS , Gate-to-Source Voltage (V)
Crss = Cgd Coss = Cds + Cgd
8000
C, Capacitance(pF)
20
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED
Ciss
6000
4000
Coss
2000
Crss
ID = 121A
V DS= 32V V DS= 20V
16
12
8
4
0 1
10
FOR TEST CIRCUIT SEE FIGURE 13
100
0
0
VDS, Drain-to-Source Voltage (V)
1000
ISD , Reverse Drain Current (A)
100
150
200
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
10000
OPERATION IN THIS AREA LIMITED BY RDS(on)
TJ = 175 ° C
100
ID , Drain Current (A)
1000
10
10us
100us
100
TJ = 25 ° C 1
1ms 10ms
10
0.1 0.0
V GS = 0 V 0.5
1.0
1.5
2.0
2.5
3.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
4
50
QG , Total Gate Charge (nC)
3.5
1
TC = 25 °C TJ = 175 °C Single Pulse 1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF1404 220
VDS
LIMITED BY PACKAGE
200
VGS
ID , Drain Current (A)
180
RD
D.U.T.
RG
160
+
-V DD
140
10V
120
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
100 80
Fig 10a. Switching Time Test Circuit
60
VDS
40
90%
20 0
25
50
75
100
125
150
175
TC , Case Temperature ( °C) 10% VGS
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50 0.20
0.1
0.10 0.05 0.02 0.01
SINGLE PULSE (THERMAL RESPONSE)
PDM
0.01
t1 t2
0.001 0.00001
Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRF1404
DRIVER
L
VDS
D.U.T
RG
+ V - DD
IAS 20V
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp
EAS , Single Pulse Avalanche Energy (mJ)
1500
15V
ID 49A 101A BOTTOM 121A TOP
1200
A
900
600
300
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( ° C) I AS
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms QG
10 V QGD
4.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform Current Regulator Same Type as D.U.T.
50KΩ 12V
.2µF .3µF
D.U.T.
+ V - DS
-VGS(th) Gate threshold Voltage (V)
QGS
3.0
ID = -250µA
2.0
1.0 -75
VGS
-50
-25
0
25
50
75
100
125
150
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 14. Threshold Voltage Vs. Temperature
Fig 13b. Gate Charge Test Circuit
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IRF1404 1000
Avalanche Current (A)
Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav assuming ∆ Tj = 25°C due to avalanche losses
0.01 100
0.05 0.10 10
1 1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
400
TOP Single Pulse BOTTOM 10% Duty Cycle ID = 121A
EAR , Avalanche Energy (mJ)
350 300 250 200 150 100 50 0 25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 15, 16). tav = Average time in avalanche. 175 D = Duty cycle in avalanche = t av ·f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav
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IRF1404 Peak Diode Recovery dv/dt Test Circuit +
D.U.T
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
+
-
-
+
• • • •
RG
Driver Gate Drive P.W.
+
dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
D=
Period
-
VDD
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current
Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
Re-Applied Voltage
Body Diode
VDD
Forward Drop
Inductor Curent Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices Fig 17. For N-channel HEXFET® Power MOSFETs
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IRF1404 TO-220AB Package Outline Dimensions are shown in millimeters 10.54 (.415) 10.29 (.405)
2.87 (.113) 2.62 (.103)
-B-
3.78 (.149) 3.54 (.139)
4.69 (.185) 4.20 (.165)
-A-
1.32 (.052) 1.22 (.048)
6.47 (.255) 6.10 (.240)
4 15.24 (.600) 14.84 (.584)
1.15 (.045) MIN 1
2
14.09 (.555) 13.47 (.530)
4.06 (.160) 3.55 (.140)
3X 3X
LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
3
1.40 (.055) 1.15 (.045)
0.93 (.037) 0.69 (.027)
0.36 (.014)
3X M
B A M
0.55 (.022) 0.46 (.018)
2.92 (.115) 2.64 (.104)
2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF1010 LOT CODE 1789 ASS EMB LED ON WW 19, 1997 IN THE ASS EMB LY LINE "C"
Note: "P" in assembly line position indicates "Lead-Free"
INTERNAT IONAL RECTIFIER LOGO
ASS EMBLY LOT CODE
PART NUMB ER
DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C
For GB Production EXAMPLE: THIS IS AN IRF1010 LOT CODE 1789 AS SEMBLED ON WW 19, 1997 IN T HE AS SEMBLY LINE "C"
INTERNATIONAL RECTIFIER LOGO
PART NUMBER
DATE CODE LOT CODE
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice. This product has been designed and qualified for the automotive [Q101] market. Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.01/01
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Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/
