Transcript
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES MSM832 - 70/85/10 PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE ISSUE 4.4 : November 1998
32K x 8 SRAM MSM832 - 70/85/10 Issue 4.4 : Nov 1998
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191 2590997
Description
32,768 x 8 CMOS Static RAM
The MSM832 is a Static RAM organised as 32K x 8 available with access times of 70,85 or 100 ns. The device is available in three ceramic package options including the high denisty VIL™ package. It features completely static operation with a low power standby mode and is 3.0V battery back-up compatible. It is directly TTL compatible and has common data inputs and outputs. The device may be screened in accordance with MIL-STD-883.
Features • Fast Access Times of 70/85/100 ns. • JEDEC Standard footprint. • Low Power Operation : 605 mW (max) • Low Power Standby : 2.53mW (max) -L version. • Low Voltage Data Retention. • Directly TTL compatible. • Completely Static Operation.
Block Diagram
A3 A4 A5 A6 A7 A8 A12 A13 A14
X Address
Pin Definitions
Row
512 X 512
I/O Buffer
Column I/O
1 2 3 4 5 6 TOP VIEW 7 PACKAGE 8 V,T,S 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE A13 A8 A9 A11 OE A10 CS D7 D6 D5 D4 D3
Column Decoder
4 3 2 1 32 31 30
A7 A12 A14 NC Vcc WE A13
D7
Memory Array
Decoder
Buffer
D0
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND
Y Address Buffer
WE
A6 A5 A4 A3 A2 A1 A0 NC D0
OE A0 A1 A2 A9 A10 A11
CS
5 6 7 8 9 10 11 12 13
J,W PACKAGE TOP VIEW
29 28 27 26 25 24 23 22 21
20 19 18 17 16 15 14 D5 D4 D3 NC GND D2 D1
Package Details Pin Count 28 32 32
Description
Package Type
0.1" Vertical-in-Line (VILTM) J-Leaded Chip Carrier (JLCC) Leadless Chip Carrier (LCC)
V J W
1
Pin Functions A0-A14 Address inputs D0-7 Data Input/Output CS Chip Select OE Output Enable WE Write Enable V CC Power(+5V) GND Ground
A8 A9 A11 NC OE A10 CS D7 D6
ISSUE 4.4 : November 1998
MSM832 - 70/85/10
DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Voltage on any pin relative to VSS (2)
VT
Power Dissipation
PT
Storage Temperature
TSTG
-0.5V to +7
V
1
W
-65 to +150
o
C
Notes : (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
min
typ
max
Unit
Supply Voltage
V CC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.2
-
VCC+0.5
V
Input Low Voltage
VIL
-0.3
-
0.8
V
Operating Temperature
TA
0
-
70
o
TAL
-40
-
85
o
TAM
-55
-
125
o
C C ( Suffix I ) C ( Suffix M, MB )
DC Electrical Characteristics (VCC = 5.0V±10%, TA=-55°C to +125°C)
Parameter
Symbol Test Condition
min
typ
max
Unit
Input Leakage Current
ILI
VIN=0V to VCC
-4
-
4
µA
Output Leakage Current
ILO
CS=VIH or OE=VIH ,VI/O= VSS to VCC ,WE=VIL
-4
-
4
µA
Average Supply Current
ICC
CS=VIL,II/O=0mA, Min. Cycle, Duty=100%
-
-
110
mA
Standby Supply Current
ISB1
CS=VIH ,Min Cycle.
-
-
3.5
mA
ISB2
CS≥VCC-0.2V, 0.2V≥VIN≥VCC-0.2V
-
-
460
uA
VOL
IOL= 2.1 mA
-
-
0.4
V
VOH
IOH= -1.0 mA
2.4
-
-
V
min
typ
max
Unit
-L Version Output Voltage
Typical values at VCC=5.0V,TA=25OC and specified loading
Capacitance (VCC=5V±10%,TA=25°C)
Parameter
Symbol Test Condition
Input Capacitance
CIN
VIN = 0V
-
-
8
pF
I/O Capacitance
CI/O
VI/O= 0V
-
-
10
pF
Note:
This parameter is not 100% tested.
2
MSM832 - 70/85/10
ISSUE 4.4 : November 1998
Operating Modes The table below shows the logic inputs required to control the MSM832 SRAM.
Mode
CS
OE
WE
VCC Current
Not Selected
1
X
X
ISB1,ISB2
High Z
OutputDisable
0
1
1
ICC
High Z
Read
0
0
1
ICC
DOUT
Read Cycle
Write
0
X
0
ICC
DIN
Write Cycle
1 = VIH,
I/O Pin Reference Cycle
0 = VIL,
Power Down
X = Don't Care
Low Vcc Data Retention Characteristics - L Version Only ( TA=-55°C to +125°C)
Parameter
Symbol
Test Condition
min
typ
max
2.0
-
-
V
-
700
µA
-
-
ns
-
-
ns
VCC for Data Retention
VDR
CS≥VCC-0.2V, VIN≥0V
Data Retention Current -L Version
ICCDR2
VCC=3.0V, CS≥VCC-0.2V, VIN≥0V -
Chip Deselect to Data Retention Time
t CDR
See Retention Waveform
Operation Recovery Time
tR
0 t RC
See Retention Waveform
(1)
Notes (1) tRC = Read Cycle Time
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
I/O Pin
166 Ω
* Input rise and fall times: 3ns
1.76V
* Input and Output timing reference levels: 1.5V
30pF
* Output load: see diagram * Vcc=5V±10%
3
Unit
ISSUE 4.4 : November 1998
MSM832 - 70/85/10
AC OPERATING CONDITIONS Read Cycle
70 Parameter
Symbol min
85
10
max
min
max
min
max
Unit
Read Cycle Time
t RC
70
-
85
-
100
-
ns
Address Access Time
tAA
-
70
-
85
-
100
ns
Chip Select Access Time
tACS
-
70
-
85
-
100
ns
Output Enable to Output Valid
tOE
-
40
-
45
-
50
ns
Output Hold from Address Change
tOH
5
-
5
-
10
-
ns
Chip Selection to Output in Low Z
tCLZ
5
-
10
-
10
-
ns
tOLZ
0
-
5
-
5
-
ns
t CHZ
0
25
0
30
0
35
ns
tOHZ
0
25
0
30
0
35
ns
70 Symbol min. max
min.
85 max
min
max
Unit
Output Enable to Output in Low Z (3)
Chip Deselection to Output in High Z Output Disable to Output in High Z
(3)
Write Cycle
Parameter
10
Write Cycle Time
t WC
70
-
85
-
100
-
ns
Chip Selection to End of Write
t CW
65
-
75
-
80
-
ns
Address Valid to End of Write
tAW
65
-
75
-
80
-
ns
Address Setup Time
tAS
0
-
0
-
0
-
ns
Write Pulse Width
tWP
60
-
60
-
60
-
ns
Write Recovery Time
t WR
0
-
0
-
0
-
ns
Write to Output in High Z
t WHZ
0
30
0
30
0
35
ns
Data to Write Time Overlap
t DW
40
-
40
-
40
-
ns
t DH
0
-
0
-
0
-
ns
tOHZ
0
25
0
30
0
35
ns
t OW
5
-
5
-
5
-
ns
Data Hold from Write Time Output Disable to Output in High Z Output Active from End of Write
(3)
4
MSM832 - 70/85/10
ISSUE 4.4 : November 1998
Read Cycle Timing Waveform
(1)
t
RC
Address t AA
OE t OE
t OH
t OLZ t CLZ
CS
t ACS
t CHZ(3) t OHZ(3)
Dout
High-Z
Data Valid
Write Cycle No.1 Timing Waveform
t WC
Address
OE
t AS(3) t AW tWR
t CW(4)
(2)
(6)
CS t WP(1)
WE
t OHZ(3,9)
Dout
Din
t OW
High-Z t DW High-Z
t DH
Data Valid
5
ISSUE 4.4 : November 1998
MSM832 - 70/85/10
Write Cycle No.2 Timing Waveform
(5)
t WC Address tCW CS
(4)
(6)
t AW
t WR(2)
t WP(1) WE
t AS(3)
t OH t WHZ(3,9)
t OW
(8)
(7)
High-Z
Dout
t DW High-Z
Din
tDH
Data Valid
Data Retention Waveform
Vcc
DATA RETENTION MODE 4.5V
4.5V
tR
t CDR
2.2V
VDR CS 0V
CS>Vcc-0.2V
AC Write Characteristics Notes (1) (2) (3) (4) (5) (6) (7) (8) (9)
A write occurs during the overlap (tWP) of a low CS and a low WE. tWR is measured from the earlier of CS or WE going high to the end of write cycle. During this period, I/O pins are in the output state. Input signals out of phase must not be applied. If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain in a high impedance state. OE is continuously low. (OE=VIL) Dout is in the same phase as written data of this write cycle. Dout is the read data of next address. If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied to I/O pins. tWHZ and tOHZ is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage levels. This parameter is sampled and not 100% tested.
6
MSM832 - 70/85/10
ISSUE 4.4 : November 1998
PACKAGE DETAILS dimensions in mm (inches) 28 pin 0.1" Vertical-In-Line (VIL) - 'V' Package
35.94 (1.415)
3.18 (0.125)
35.18 (1.385) 10.41 (0.410)
11.43 (0.450)
2.67 (0.105)
4.00 (0.157) 3.00 (0.117) 1.54 (0.060)
2.54 (0.100)
0.51 (0.020)
1.02 (0.040)
2.54 (0.100)
0.41 (0.016)
28 pin 0.3" Dual-in-Line (SKINNY) - 'T' Package
35.94 (1.415) 35.18 (1.385)
1.54 (0.060) 1.02 (0.040)
Standard Product
4.00 (0.157) 3.00 (0.117) 2.67 (0.105) 2.41 (0.095)
0.51 (0.020) 0.41 (0.016)
7
7.87 (0.310) 7.37 (0.290)
4.30 (0.170) 3.30 (0.130)
ISSUE 4.4 : November 1998
MSM832 - 70/85/10
28 pin 0.6" Dual-In-Line (DIL) - 'S' Package
35.94 (1.415)
1.54 (0.060) 1.02 (0.040)
15.05 (0.590)
Standard Product
15.56 (0.610)
35.18 (1.385)
4.45 (0.175) 3.43 (0.135)
4.00 (0.157) 3.00 (0.117) 2.67 (0.105)
0.51 (0.020)
2.41 (0.095)
0.41 (0.016)
32 pin J-Leaded Chip Carrier - 'J' Package
9.91 (0.390)
10.41 (0.410)
13.45 (0.530)
13.95 (0.510)
14.22 (0.560)
11.30 (0.445)
0.71 (0.028) typ
1.27 (0.050) typ
1.90 (0.075) 1.65 (0.065)
13.84 (0.545)
11.70 (0.460)
No. 1 Index
0.43 (0.017) typ
4.32 (0.170)
7.87 (0.310)
3.80 (0.150)
7.37 (0.290)
8
MSM832 - 70/85/10
ISSUE 4.4 : November 1998
32 pad Leadless Chip Carrier (LCC) - 'W' Package
11.70 (0.460)
1.27 (0.050) typ
2.03 (0.080)
11.30 (0.445)
0.64 (0.025) typ
max
9.92 (0.390)
10.42 (0.410)
14.22 (0.560)
13.84 (0.545)
No. 1 Index
7.87 (0.310)
1.27 (0.050) typ
7.37 (0.290)
Minimum Order Product - Consult Factory for details SCREENING Military Screening Procedure The Component Screening Flow for high reliability parts in accordance with Mil-883 method 5004 is shown below:
MB COMPONENT SCREENING FLOW SCREEN
TEST METHOD
LEVEL
Visual and Mechanical Internal visual Temperature cycle Constant acceleration Pre-Burn-in electrical Burn-in
2010 Condition B or manufacturers equivalent 1010 Condition C (10 Cycles,-65°C to +150°C) 2001 Condition E (Y, only) (30,000g) Per applicable device specifications at TA=+25°C Method 1015,Condition D,TA=+125°C,160hrs min
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25°C and power supply extremes b) @ temperature and power supply extremes
100% 100%
Functional
a) @ TA=+25°C and power supply extremes b) @ temperature and power supply extremes
100% 100%
Switching (ac)
a) @ TA=+25°C and power supply extremes b) @ temperature and power supply extremes
100% 100%
Percent Defective allowable (PDA)
Calculated at post-burn-in at TA=+25°C
Hermeticity
1014
Fine Gross
Condition A Condition C
100% 100%
External Visual
2009 Per vendor or customer specification
100%
9
100% 100% 100% 100% 100%
5%
ISSUE 4.4 : November 1998
MSM832 - 70/85/10
ORDERING INFORMATION
MSM832SLMB - 85 Speed
70 85 10
= 70 ns = 85 ns = 100 ns
Temp. range/screening
Blank I M MB
= Commercial = Industrial = Military = Screened in accordance with MIL-STD-883
Power Option
Blank = Standard Power L = Low Power
Package
V J W
= 28 pin 0.1" VIL = 32 pad JLCC = 32 pad LCC
Memory Organisation
832
= 32K x 8 SRAM
THE MSM832W/J/V ARE NOT RECOMMENDED FOR NEW DESIGNS AND MAY BE MADE OBSOLETE WITHOUT NOTICE....
Although this data is believed to be accurate, the information contained herein is not intended to, and does not create any warranty of merchantability or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed at any time without notice. Our products are not authorised for use as critical components in life support devices, or systems without the express written approval of a company director.
10
