Transcript
Part num ber schem e
TO-240AA compatible package
PS KT 91 N 16 STD 1
80 6.2 6 7
21
2
3
20
M5
20
2
3
4
5
6
1) Power Semiconductors initials 2) Circuit designation 3) Series number 4) Designates standard recovery time 5) Voltage Multiplier (example: 16 x 100 = 1600 Volts) 6) Proprietary suffix
20
4 5
13 1
Pa r t # PSKT9 1 N . . se r ie s I T( AVE) 9 0 A V D RM V RRM 1 2 0 0 V ~ 1 8 0 0 V
Ph a se Con t r ol Th yr ist or s
P WER Semiconductors Inc.
2.8 x 0.8 TERMINAL
Features:
29
Weight 115g
X X X X X X X
3 92
KT circuit 1
2
4
5
7 6
3
Gate Terminal Table 4 = K2 5 = G2 6 = G1 7 = K1
All diffused silicone junctions. Standard recovery time for phase control applications. Module package compatible with JEDEC T0-240AA. Thick copper base plate. Isolated cooling, rated up to 3500 VRMS Easy mounting to heat sink Heat sink grounded.
V olt a ge Pa ra m e t e r
Sym bol
Ra t ing
U nit s
Maximum Repetitive Off-State Voltage Notes: 1, 3, 4, 5, 6, 7 Maximum Repetitive Reverse Voltage Notes: 1, 3, 4, 5, 6 Maximum non repetitive Surge of Reverse Voltage Notes: 2, 3, 4, 5, 6 Critical rate of rising off-state Voltage, Linear to 80% of VDRM Note: 2
VDRM VRRM VRSM dv/dt
1200 ~ 1800 1200 ~ 1800 VRRM + 100 500
Volts Volts Volts V/ s
Note 1: TJ 25oC. Note 2: TJ 125oC. Note 5: VDRM and VRRM have IDRM, IRRM of up to 20mA. Specifying voltage: 1400V, PSKT91N14 1200V, PSKT91N12 1600V, PSKT91N16
Note 3: Measured at the peak of the sine wave, Note 6: VDR and VRR have typical IDR, IRR of 2~3mA. 1800V, PSKT91N18 Above 1800V inquire about availability.
Note 4: Below 0oC derate VDRM and VRRM 10%. Note 7: For DC applications derate VDRM 45%.
Ga t e Pa ra m e t e r
Sym bol
Gate Trigger Voltage Note 3
VGT
Maximum Gate Trigger Current Notes 1,3 Minimum Forward Current to Latch on-state Notes 1, 5 Maximum permissible Gate Voltage not to Trigger Notes 1,3 Maximum permissible Gate Current not to Trigger Notes 1, 3 Maximum peak non repetitive Gate Voltage Notes 2, 3 Maximum Negative Gate Voltage Notes 2, 4 Maximum non repetitive Gate Current Notes 2, 3 Maximum Repetitive Gate Current Notes 2, 3 Average Gate Power (recommended) Note 2, 3 Note 1: TJ 25OC.
Note 2: TJ 125OC.
Note 3: Rectangular pulse, tp [ 8.3 ms.
IGT IL VGDM IGDM VGM -VGM IGM IGRM PG(AVE)
Ra t ing Temp. -20O C 25O C 125O C
Typ. 2.7 ~ 3.5 2.6 ~ 3.3 2.5 ~ 3.1
U nit s Max. 3.5
150 400 250 5 8 5 3 1 0.9 ~ 3.0
Note 4: Rectangular -V DC pulse, tp [ 8.3 ms.
Volts mA mA mV mA Volts Volts Amperes Amperes Watts
Note 5: Test conditions: I DC RL = 12 .
Cu r r e n t Pa ra m e t e r
Sym bol
Ra t ing
U nit s
Maximum, Average, On state, Current, Notes: 1, 2 Maximum, RMS, On state, Current Notes: 1, 3 Maximum non repetitive, Surge. On state, Current ,with no reverse voltage reapplied. Maximum non repetitive, Surge, On state, Current, with maximum reverse voltage reapplied. Notes: 2, 4 Critical rate of rising On-state Current, non repetitive Note: 6, 7 Holding Current Notes: 1, 5 Maximum On State Voltage drop at Maximum On State Current IDRM = Maximum (threshold), Repetitive, Off-State, Current. Note: 1 IRRM = Maximum (threshold), Repetitive, Reverse, Current. Note: 1 Fuse’s absolute maximum I2 t with no reverse voltage Fuse’s absolute maximum I2 t with up to 80% of VRRM
IT(AVE) IT(RMS)
90 145
Amperes Amperes
ITSM 0%VRRM
1.7
kA
ITSM 100%VRRM
1.4
kA
di/dt IH
150 250
A/ s mA
VTM @ ITM
1.4 @ 200
V@ A
IDRM & IRRM
20
mA
13.08 9.25
kA kA
Note 1: TJ 55OC, Air Cooled Note 4: Test conditions I DC RL = 12
2
I t, 0% VRR I2 t, [ 80% VRRM
Note 2: 120 o Conduction, 60 Hz, Sinewave Note 3: 180 o Conduction, 60 Hz, Sinewave Note 5: Switching from VDRM ] 1000V Note 6: In addition to 0.2 F and 20 snubber circuit
www.PowerSemiconductors.com
e-mail:
[email protected]
Tel. 760-931-9177
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