Transcript
Product Specifications PART NO:
VL383L5621E-B3S-I
REV: 1.0
General Information 2GB 256MX72 DDR SDRAM REGISTERED ECC 184 PIN DIMM Description
The VL383L5621E is a 256Mx72 Double Data Rate SDRAM high density registered DIMM. This memory module consists of thirty-six CMOS 128Mx4 bit with 4 banks DDR Synchronous DRAMs in BGA packages, two 13-26 bit Registered buffers in TSSOP package, a zero delay PLL clock in TSSOP package, and a 2K EEPROM in an 8-pin TSSOP package. This module is a 184-pin dual in-line memory module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR SDRAM.
Features . . . . . . . . . . . . . . . . .
VDD: 2.5V +/- 0.2V , VDDQ: 2.5V +/- 0.2V VDDSPD = 2.3V to 3.6V 2.5V I/O (STTL_2 compatible) Supports ECC error detection and correction Two data transfers per clock cycle Birdirectional data strobe (DQS) Differential clock inputs (CK and CK#) DLL aligns DQ and DQS transition with CK transition Programmable Read latency: DDR333(3 clock) Programmable burst; length (2, 4, 8) Programmable burst (sequential & interleave) Auto & self refresh, 7.8us refresh interval (8K/64ms refresh) Serial presence detect (SPD) with EEPROM PCB: Height 1.200”, double sided components Gold edge contacts Leaded & lead-free/RoHS compliant Operating temperature (T A): -400C to +85 0C
Order Information VL383L5621E-B3 S - I I: Screening temperature DRAM MANUFACTURER S - SAMSUNG
Pin Name
Function
A0~A12
Address Inputs
B A 0, B A 1
Bank Select Address
DQ0~DQ63
Data Input/Output
CB0~CB7
Check Bit (Data-in/Data-out)
DQS0~DQS17
Data Strobe Input/Output
C K 0, C K 0#
Clock Input
C K E 0, C K E 1
Clock Enable Input
C S 0#, C S 1#
Chip Select Input
RAS#
Row Address Strobe
C AS#
Column Addres Input
WE#
Write Enable
VD D
Power Supply
VD D Q
Power Supply for DQS
VSS
Ground
VREF
Power Supply for Reference
VD D SPD
SPD Power Supply (2.3V-3.6V)
SD A
Serial Data Input/Output
SC L
SPD Clock Input
SA0~SA2
SPD Address
RESET#
Reset Enable
NC
No Connection
MODULE SPEED B3: PC2700 @ CL2.5 VL : Lead-free/RoHS
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688 Tel: 949-888-2444 Fax: 949-888-2445 PAGE 1 OF 9
Product Specifications PART NO:
VL383L5621E-B3S-I
REV: 1.0
Pin Configuration 184-PIN DDR DIMM FRONT
184-PIN DDR DIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
24
DQ17
47
DQS8
70
VDD
93
VSS
116
VSS
13 9
VSS
162
DQ47
2
DQ0
25
DQS2
48
A0
71
NC
94
DQ4
117
DQ21
140
DQS17
163
NC
3
VSS
26
VSS
49
C B2
72
DQ48
95
DQ5
118
A11
141
A 10
164
VD DQ
4
DQ1
27
A9
50
VSS
73
DQ49
96
VD D Q
119
DQS11
142
C B6
165
DQ52
5
DQS0
28
DQ18
51
C B3
74
VSS
97
DQS9
120
VD D
143
VD D Q
166
DQ53
6
DQ2
29
A7
52
BA1
75
C K 2#*
98
DQ6
121
DQ22
144
CB7
167
A 13*
7
VD D
30
VD D Q
53
DQ32
76
C K 2*
99
DQ7
122
A8
145
VSS
168
VDD
8
DQ3
31
DQ19
54
VD D Q
77
VD D Q
100
VSS
123
DQ23
146
DQ36
169
DQS15
9
NC
32
A5
55
DQ33
78
DQS6
101
NC
124
VSS
147
DQ37
170
DQ54
10
RESET#
33
DQ24
56
DQS4
79
DQ50
102
NC
125
A6
148
VD D
171
DQ55
11
VSS
34
vss
57
DQ34
80
DQ51
103
NC
126
DQ28
149
DQS13
172
VD D Q
12
DQ8
35
DQ25
58
VSS
81
VSS
104
VD D Q
127
DQ29
150
DQ38
173
NC
13
DQ9
36
DQS3
59
BA0
82
NC
105
DQ12
128
VD D Q
151
DQ39
174
DQ60
14
DQS1
37
A4
60
DQ35
83
DQ56
106
DQ13
129
DQS12
152
VSS
175
DQ61
15
VD D Q
38
VDD
61
DQ40
84
DQ57
107
DQS10
130
A3
153
DQ44
176
VSS
16
C K 1*
39
DQ26
62
VD D Q
85
VDD
108
VD D
131
DQ30
154
RAS#
177
DQS16
17
C K 1#*
40
DQ27
63
WE#
86
DQS7
109
DQ14
132
VSS
155
DQ45
178
DQ62
18
VSS
41
A2
64
DQ41
87
DQ58
110
DQ15
133
DQ31
156
VD D Q
179
DQ63
19
DQ10
42
VSS
65
C AS#
88
DQ59
111
C KE1
134
CB4
157
C S 0#
180
VD D Q
20
DQ11
43
A1
66
VSS
89
VSS
112
VD D Q
135
CB5
158
C S 1#
181
SA0
21
C KE0
44
CB0
67
DQS5
90
NC
113
NC
136
VD D Q
159
DQS14
182
SA1
22
VD D Q
45
C B1
68
DQ42
91
SD A
114
DQ20
137
CK0
160
VSS
183
SA2
23
DQ16
46
VDD
69
DQ43
92
SC L
115
A 12
138
C K 0#
161
DQ46
184
VD D SPD
Note: *: These pins are not used on this module.
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688 Tel: 949-888-2444 Fax: 949-888-2445 PAGE 2 OF 9
Product Specifications PART NO:
VL383L5621E-B3S-I
REV: 1.0
Functional Block Diagram VSS RCS1# RCS0# DQS0
DQS9 DQS I/O 3 I/O 2 I/O 1 I/O 0
S0#
DQ0 DQ1 DQ2 DQ3
S0#
DQ8 DQ9 DQ10 DQ11
DQS I/O 3 I/O 2 I/O 1 I/O 0
S0#
DQ16 DQ17 DQ18 DQ19
DQS I/O 3 I/O 2 I/O 1 I/O 0
S0#
DQ24 DQ25 DQ26 DQ27
DQS I/O 3 I/O 2 I/O 1 I/O 0
S0#
DQ32 DQ33 DQ34 DQ35
DQS I/O 3 I/O 2 I/O 1 I/O 0
S0#
DQ40 DQ41 DQ42 DQ43
DQS I/O 3 I/O 2 I/O 1 I/O 0
S0#
DQ48 DQ49 DQ50 DQ51
DQS I/O 3 I/O 2 I/O 1 I/O 0
S0#
DQ56 DQ57 DQ58 DQ59
DQS I/O 3 I/O 2 I/O 1 I/O 0
DQS I/O 3 I/O 2 I/O 1 I/O 0
S0#
CB0 CB1 CB2 CB3
DM
D0
DQS I/O 3 I/O 2 I/O 1 I/O 0
S1#
DQS I/O 3 I/O 2 I/O 1 I/O 0
S1#
DQS I/O 3 I/O 2 I/O 1 I/O 0
S1#
DQS I/O 3 I/O 2 I/O 1 I/O 0
S1#
DQS I/O 3 I/O 2 I/O 1 I/O 0
S1#
DQS I/O 3 I/O 2 I/O 1 I/O 0
S1#
DQS I/O 3 I/O 2 I/O 1 I/O 0
S1#
DQS I/O 3 I/O 2 I/O 1 I/O 0
S1#
DQS I/O 3 I/O 2 I/O 1 I/O 0
S1#
DM DQ4 DQ5 DQ6 DQ7
D18
DQS1
D1
DM DQ12 DQ13 DQ14 DQ15
D19
D2
DM DQ20 DQ21 DQ22 DQ23
D20
S0#
DQS I/O 0 I/O 1 I/O 2 I/O 3
S0#
DQS I/O 0 I/O 1 I/O 2 I/O 3
S0#
DQS I/O 0 I/O 1 I/O 2 I/O 3
S0#
DQS I/O 0 I/O 1 I/O 2 I/O 3
S0#
DQS I/O 0 I/O 1 I/O 2 I/O 3
S0#
DQS I/O 0 I/O 1 I/O 2 I/O 3
S0#
DQS I/O 0 I/O 1 I/O 2 I/O 3
S1#
DM
D27
DM
D10
DQS I/O 0 I/O 1 I/O 2 I/O 3
D28
DQS I/O 0 I/O 1 I/O 2 I/O 3
D29
DQS I/O 0 I/O 1 I/O 2 I/O 3
D30
DQS I/O 0 I/O 1 I/O 2 I/O 3
D31
DQS I/O 0 I/O 1 I/O 2 I/O 3
D32
S1#
DM
DM
D11
S1#
DM
DQS12 DM
D3
DM DQ28 DQ29 DQ30 DQ31
D21
DM
D12
S1#
DM
DQS13
DQS4 DM
D4
DM DQ36 DQ37 DQ38 DQ39
D22
DM
D13
S1#
DM
DQS14
DQS5 DM
D5
DM DQ44 DQ45 DQ46 DQ47
D23
DQS6
DM
D14
S1#
DM
DQS15 DM
D6
DM DQ52 DQ53 DQ54 DQ55
D24
DQS7
DM
D15
DQS I/O 0 I/O 1 I/O 2 I/O 3
D33
DQS I/O 0 I/O 1 I/O 2 I/O 3
D34
DQS I/O 3 I/O 2 I/O 1 I/O 0
D35
S1#
DM
DQS16 DM
D7
DM DQ60 DQ61 DQ62 DQ63
D25
DQS8
DM
D16
S1#
DM
DQS17 DM
D8
DM CB4 CB5 CB6 CB7
D26
RCS0# : RCS1# :
S0#
DM
D17
A0
A1
A2
SA0
SA1
SA2
S1#
DM
SPD
V D D /V DDQ
D0 - D35
VREF
D0 - D35
V SS
D0 - D35
SDA
WP
1:2 R E G I S T E R
DQS I/O 3 I/O 2 I/O 1 I/O 0
V DDSPD
Serial PD SCL
PCK
DQS I/O 0 I/O 1 I/O 2 I/O 3
DM
D9
DQS11 DM
DQS3
WE#
S0#
DQS10 DM
DQS2
CS0# CS1# BA0-BA1 A0-A12 RAS# CAS# CKE0 CKE1
DQS I/O 0 I/O 1 I/O 2 I/O 3
SDRAMs D0 - D17 SDRAMs D18 - D35
RBA0 - RBA1 RA0 - RA12 RRAS# RCAS#
BA0-BA1: SDRAMs D0 - D35 A0-A12: SDRAMs D0 - D35 R A S #: SDRAMs D0 - D35 C A S #: SDRAMs D0 - D35
RCKE0
CKE : SDRAMs D0 - D17
RCKE1
CKE : SDRAMs D18 - D35
RWE#
WE # : SDRAMs D0 - D35
CK0 CK0#
PLL
RESET#
DDR SDRAM X 4 DDR SDRAM X 4 DDR SDRAM X 4 DDR SDRAM X 4 DDR SDRAM X 4 DDR SDRAM X 4 DDR SDRAM X 4 DDR SDRAM X 4 DDR SDRAM X 4 REGISTER X2
Notes: DQ, DQS, DM/DQS resistors: 22 Ohms.
PCK#
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688 Tel: 949-888-2444 Fax: 949-888-2445 PAGE 3 OF 9
Product Specifications PART NO:
VL383L5621E-B3S-I
REV: 1.0
Absolute Maximum Ratings Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
VDD, VDDQ
-0.1 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
0
C
Operating temperature
TA
-40 ~ +85
0
C
Power Dissipation
PD
36
W
Short circuit output current
IOS
50
mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposing to higher than recommended voltage for extended periods of time could affect device reliability.
D C Operating C onditions TA = -400C to +850C
Parameter
Symbol
Mi n
Max
Uni t
VDD
2.3
2.7
V
I/O Supply voltage D D R333 ( nomi nal VD D 2.5V)
VDDQ
2.3
2.7
V
I/O Reference voltage
Supply voltage D D R333 ( nomi nal VD D 2.5V)
Note
VREF
0.49 * VD D Q
0.51 * VD D Q
V
1
I/O Termi nati on voltage
VTT
VREF-0.04
VREF+0.04
V
2
Input logi c hi gh voltage
VIH(D C )
VREF+0.15
VDDQ+0.30
V
Input logi c low voltage
VIL(D C )
-0.3
VREF-0.15
V
Input voltage level, C K and C K#
VIN(D C )
-0.3
VDDQ+0.30
V
Input di fferenti al voltage, C K and C K#
VID(D C )
0.36
VDDQ+0.60
V
Input crossi ng poi nt voltage, C K and C K#
VIX(D C )
0.3
VDDQ+0.60
V
-5
5
uA
Addr, C AS#,RAS#,WE# Input leakage current
C S #, C K E
-5
5
uA
C K, C K#
-10
10
uA
DM
-4
4
uA
II
Output leakage current
IOZ
-10
10
uA
Output hi gh current(normal strength) VOUT = v + 0.84V
IOH
-16.8
-
mA
Output hi gh current(normal strength) VOUT = VTT - 0.84V
IOL
16.8
-
mA
Output hi gh current(half strength) VOUT = VTT + 0.45V
IOH
-9
-
mA
Output hi gh current(half strength) VOUT = VTT - 0.45V
IOL
9
-
mA
Notes:
3
1. VREF i s expected to be equal to 0.5*VD D Q of the transmi tti ng devi ce, and to track vari ati ons i n the D C level of the same. Peak to peak noi se on VREF may not exceed +/- 2% of the D C value. 2. VTT i s not appli ed di rectly to the devi ce. VTT i s a system supply for si gnal termi nati on resi stors, i s expected to be set equal to VREF, and must track vari ati ons i n the D C level of VREF. 3. VID i s the magni tude of the di fference between the i nput level on C K and the i nput level of C K#.
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688 Tel: 949-888-2444 Fax: 949-888-2445 PAGE 4 OF 9
Product Specifications PART NO:
VL383L5621E-B3S-I
REV: 1.0
AC Operating Conditions (TA = -400C to +850C)
Parameter
Symbol
Min
Input High (Logic1) Voltage
VIH(AC)
VREF+0.31
Input Low (Logic0) Voltage
VIL(AC)
Input Differential Voltage, CK and CK# Inputs
VID(AC)
Input Crossing Point Voltage, CK and CK# Inputs
VIX(AC)
Max
Unit V
VREF-0.31
V
0.7
VDDQ+0.6
V
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
Input/Output Capacitance TA=250C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A12, BA0~BA1, RAS#, CAS#, WE#)
CIN1
9
11
pF
Input capacitance (CKE0, CKE1)
CIN2
9
11
pF
Input capacitance (CS0#, CS1#)
CIN3
9
11
pF
Input capacitance (CK0, CK0#)
CIN4
11
12
pF
Input/Output capacitance (DQ, DQS, DM, CB)
CIO
11
13
pF
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688 Tel: 949-888-2444 Fax: 949-888-2445 PAGE 5 OF 9
Product Specifications PART NO:
VL383L5621E-B3S-I
REV: 1.0
IDD Specification (TA = -400C to +850C)
Condition
Symbol
-B3
Unit
IDD0*
2460
mA
IDD1*
3000
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks are idle; Power-down mode; tCK=tCK(MIN); CKE=LOW
IDD2P**
660
mA
IDLE STANDBY CURRENT: CS#=HIGH; All device banks are idle; tCK=tCK(MIN); CKE=HIGH; Address and other control inputs changing once per clock cycle. VIN=VREF for DQ,DQS and DM
IDD2F**
1560
mA
ACITVE POWER-DOWN STANDBY CURRENT: One device bank active; Powerdown mode; tCK=tCK(MIN) ; CKE=LOW
IDD3P**
1560
mA
ACTIVE STANDBY CURRENT: CS#=HIGH; CKE=HIGH; One device bank active; tRC=tRAS(MAX); tCK=tCK(MIN); DQ,DM and DQS inputs change twice per clock cycle; Address and other control inputs changing once per clock cycle
IDD3N**
2100
mA
OPERATING CURRENT: Burst = 2; Reads; Continnuous burst; One device bank active; Address and other control inputs changing once per clock cycle; tCK=tCK(MIN); IOUT=0mA
IDD4R*
3090
mA
OPERATING CURRENT: Burst = 2; Writes; Continnuous burst; One device bank active; Address and other control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs change twice per clock cycle
IDD4W*
3270
mA
AUTO REFRESH CURRENT: TRC=TRFC(MIN)
IDD5**
7860
mA
SELF-REFRESH CURRENT: CKE< 0.2V
IDD6**
180
mA
OPERATING CURRENT: Four device bank interleaving Reads Burst=4 with auto precharge; tRC=tRC(MIN) ; tCK=tCK(MIN); Address and control inputs change only during Active READ, or WRITE commands
IDD7*
7050
mA
OPERATING CURRENT: One device bank active; Active-Precharge; tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS inputs change once per clock cycle; Address and control inputs change once every two clock cycles OPERATING CURRENT: One device bank; Active-Read-Precharge; BL=4; tRC=tRC(MIN); tCK=tCK(MIN); IOUT=0mA; Address and control inputs change once per clock cycle
Note: IDD specification is based on Samsung D-die components. *: Value calculated as one module rank in this operation condition, and other module rank in IDD2P (CKE LOW) mode. **: Value calculated as all module ranks in this operation condition.
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Product Specifications PART NO:
VL383L5621E-B3S-I
REV: 1.0
AC Timing Parameters & Specifications -B 3 Parameter
Symbol MIN
Row C ycle Ti me
MAX
U nit
tRC
60
ns
tRFC
72
ns
Row acti ve
tRAS
42
RAS# to C AS# delay
tRC D
18
ns
Refresh row cycle ti me
Row precharge ti me Row acti ve to row acti ve delay Wri te recovery ti me Last data i n to READ command
C L=2.5
tRP
18
ns
12
ns
tWR
15
ns
tWTR
1
tC K
-
-
ns
tC K
6
12
ns
-
-
ns
tC H
0.45
0.55
tC K
C L=3 C lock hi gh level wi dth C lock low level wi dth D QS-out access ti me from C K/C K#
ns
tRRD
C L=2 C lock cycle ti me
70K
tC L
0.45
0.55
tC K
tD QSC K
-0.6
+0.6
ns ns
Output data access ti me from C K/C K#
tAC
-0.7
+0.7
D ata strobe edge to output data edge
tD QSQ
-
0.4
ns
Read preamble
tRPRE
0.9
1.1
tC K
Read postamble
tRPST
0.4
0.6
tC K
C K to vali d D QS-i n
tD QSS
0.75
1.25
tC K
D QS-i n setup ti me
tWPRES
0
ns
tWPRE
0.25
tC K
tD SS
0.2
tC K tC K
D QS-i n hold ti me D QS falli ng edge to C K ri si ng-setup ti me D QS falli ng edge to C K ri si ng-hold ti me
tD SH
0.2
D QS-i n hi gh level wi dth
tD QSH
0.35
tC K
D QS-i n low level wi dth
TD QSL
0.35
tC K
Address and control i nput setup ti me (fast)
tISF
0.75
ns
Address and control i nput hold ti me (fast)
tIHF
0.75
ns
Address and control i nput setup ti me (slow)
tISs
0.8
ns
Address and control i nput hold ti me (slow)
tIHs
0.8
D ata-out hi gh i mpedance ti me from C K/C K#
tHZ
-0.7
+0.7
ns
D ata-out low i mpedance ti me from C K/C K#
tLZ
-0.7
+0.7
ns
Mode regi gster set cycle
ns
tMRD
12
ns
tD S
0.45
ns
D Q & D M hold ti me to D QS
tD H
0.45
ns
C ontrol & address i nput pulse wi dth
tIPW
2.2
ns
D Q & D M i nput pulse wi dth
tD IPW
1.75
ns
Exi t self refresh to non-Read command
tXSNR
75
ns
Exi t self refresh to Read command
tXSRD
200
tC K
D Q & D M setup ti me to D QS
Refresh i nterval ti me Output D QS vali d wi ndow C lock half peri od
tREFI tQH
tHP -tQHS
tHP
tC Lmi n or tC Hmi n
D ata hold skew factor
tQHS
D QS wri te postamble
tWPST
0.4
Acti ve Read wi th auto precharge command
tRAP
18
Auto precharge Wri te recovery + Precharge ti me
tD AL
tWR/tC K + tRP/tC K
7.8
us
-
ns
-
ns
0.5
ns
0.6
tC K
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688 Tel: 949-888-2444 Fax: 949-888-2445 PAGE 7 OF 9
tC K
Product Specifications PART NO:
VL383L5621E-B3S-I
REV: 1.0
Package Dimensions
0.150 (3.80) M AX
5.256 (133.50) 5.244 (133.20) 5.077 (128.95) TYP
U1
U3
U2
U4
U19
0 .161(4.10) (4X) 0.154(3.90)
U5
U6
U7
U8
U9
U10
1.206 (30.63) 1.194 (30.33) U11
U12
U14
U13
U15
U16
U17
U20
U18
0.700 (17.78) TYP.
0.098 (2.50) D (2X) 0.091 (2.30) TYP. 0.035 (0.90) R
PIN 1 0.050 (1.27) 0.039 (1.00) TYP. TYP. 2.55 (64.77)
0.091 (2.30) TYP.
0.394 (10.00) TYP.
0.250 (6.35) TYP. 1.95 (49.53)
PIN 92
4.750 (120.65)
U21
U32
U23
U22
U33
U24
U34
U25
U35
U26
U36
U27
U28
U37
U30
U29
U38
U39
U31
U40
PIN 93
PIN 184
0.150 (3.80) TYP.
NOTE:
All dimensions in inches (millimet ers)
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688 Tel: 949-888-2444 Fax: 949-888-2445 PAGE 8 OF 9
0.054 (1.37) 0.046 (1.17)
Product Specifications PART NO:
VL383L5621E-B3S-I
Revision History: Date
Rev.
P ag e
07/30/09
1.0
All
C h an g es Spec release
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688 Tel: 949-888-2444 Fax: 949-888-2445 PAGE 9 OF 9
REV: 1.0