Transcript
ICS9LPRS480
Integrated Circuit Systems, Inc.
Programmable System Clock Chip for ATI RS780 - K8TM based Systems Key Specifications: • CPU outputs cycle-to-cycle jitter < 150ps • SRC outputs cycle-to-cycle jitter < 125ps • SB_SRC outputs cycle-to-cycle jitter < 125ps • +/- 100ppm frequency accuracy on CPU, SRC, ATIG • 0ppm frequency accuracy on 48MHz
Recommended Application: ATI RS780 systems using AMD K8 processors Output Features: • Integrated series resistors on all differential outputs. • 1 - Greyhound compatible K8 CPU pairs • 5 - low-power differential SRC pairs • 2 - low-power differential chipset SouthBridge SRC pairs • 1 - Selectable low-power differential 100MHz non-spread SATA/ SRC output • 1 - Selectable low-power differential SRC / 27MHz Single Ended outputs • 1 - Selectable HT3 100MHz low-power differential hypertransport clock / HT66MHz Single Ended outputs • 1 - 48MHz USB clock • 3 - 14.318MHz Reference clock • 2 - low-power differential ATIG pairs • 5- Dedicated CLKREQ# pins
Features/Benefits: • Power Saving Features: Optional Separate supply rail for SRC low Voltage I/O - ~33% power saving when 1.5V is used for this rail • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • External crystal load capacitors for maximum frequency accuracy
CPUKG0C_LPRS
CPUKG0T_LPRS
PD#
GNDHTT
HTT0C_LPRS/66M
HTT0T_LPRS/66M
VDDHTT
VDDREF
REF2/SEL_27
REF1/SEL_SATA
REF0/SEL_HTT66
GNDREF
X1
X2
VDD48
48MHz_0
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND48 1
48 VDDCPU
SMBCLK 2
47 VDDCPU_IO
SMBDAT 3
46 GNDCPU
VDD 4
45 CLKREQ1#*
SRC7C_LPRS/27MHz_NS 5
44 CLKREQ2#*
SRC7T_LPRS/27MHz_SS 6
43 GNDSATA
GND 7
42 SRC6T/SATAT_LPRS
SRC4C_LPRS 8
41 SRC6C/SATAC_LPRS
ICS9LPRS480
SRC4T_LPRS 9
40 VDDSATA
GNDSRC 10
39 CLKREQ3#*
VDDSRC_IO 11
38 CLKREQ4#*
SRC3C_LPRS 12
37 SB_SRC0T_LPRS
SRC3T_LPRS 13
36 SB_SRC0C_LPRS
SRC2C_LPRS 14
35 VDDSB_SRC
SRC2T_LPRS 15
34 VDDSB_SRC_IO
VDDSRC 16
33 GNDSB_SRC
1391D—02/02/09
SB_SRC1T_LPRS
ATIG0T_LPRS
SB_SRC1C_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
VDDATIG
VDDATIG_IO
GNDATIG
*CLKREQ0#
SRC0T_LPRS
SRC0C_LPRS
SRC1T_LPRS
SRC1C_LPRS
GNDSRC
VDDSRC_IO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
*Other names and brands may be claimed as the property of others.
ICS9LPRS480
Integrated Circuit Systems, Inc.
MLF Pin Description PIN # 1 2 3 4
PIN NAME GND48 SMBCLK SMBDAT VDD27
PIN TYPE GND IN I/O PWR
5
SRC7C_LPRS/27MHz_NS
OUT
6
SRC7T_LPRS/27MHz_SS
OUT
7
GND27
GND
8
SRC4C_LPRS
OUT
9
SRC4T_LPRS
OUT
10 11
GNDSRC VDDSRC_IO
GND PWR
12
SRC3C_LPRS
OUT
13
SRC3T_LPRS
OUT
14
SRC2C_LPRS
OUT
15
SRC2T_LPRS
OUT
16 17 18
VDDSRC VDDSRC_IO GNDSRC
PWR PWR GND
19
SRC1C_LPRS
OUT
20
SRC1T_LPRS
OUT
21
SRC0C_LPRS
OUT
22
SRC0T_LPRS
OUT
23
*CLKREQ0#
IN
24 25 26
GNDATIG VDDATIG_IO VDDATIG
GND PWR PWR
27
ATIG1C_LPRS
OUT
28
ATIG1T_LPRS
OUT
29
ATIG0C_LPRS
OUT
30
ATIG0T_LPRS
OUT
31
SB_SRC1C_LPRS
OUT
32
SB_SRC1T_LPRS
OUT
DESCRIPTION Ground pin for the 48MHz outputs Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. 3.3V Power supply for SRC/27MHz output and 27MHz SS PLL True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)/27MHz 3.3V Single-ended non-spread output for discrete graphics Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)/27MHz 3.3V Single-ended spreading output for discrete graphics Ground for the SRC/27MHz outputs Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Ground pin for the SRC outputs Power supply for differential SRC outputs, nominal 1.05V to 3.3V Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Supply for SRC core, 3.3V nominal Power supply for differential SRC outputs, nominal 1.05V to 3.3V Ground pin for the SRC outputs Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Clock Request pin for SRC0 outputs. If output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = Low-Low Ground pin for the ATIG outputs Power supply for differential ATIG outputs, nominal 1.05V to 3.3V Power supply for ATIG core, nominal 3.3V Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed
1391D—02/02/09
2
ICS9LPRS480
Integrated Circuit Systems, Inc.
MLF Pin Description (Continued) PIN # PIN NAME 33 GNDSB_SRC 34 VDDSB_SRC_IO 35 VDDSB_SRC
PIN TYPE DESCRIPTION GND Ground pin for the SB_SRC outputs PWR Power supply for differential SB_SRC outputs, nominal 1.05V to 3.3V PWR Supply for SB SRC PLL core, 3.3V nominal Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt OUT resistor to GND and no 33 ohm series resistor needed True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor OUT to GND and no 33 ohm series resistor needed Clock Request pin for SRC4 outputs. If output is selected for control, then that output is controlled IN as follows: 0 = enabled, 1 = Low-Low Clock Request pin for SRC3 outputs. If output is selected for control, then that output is controlled IN as follows: 0 = enabled, 1 = Low-Low PWR Power supply for SATA core logic, nominal 3.3V Complement clock of low power differential SRC/SATA clock pair. (no 50ohm shunt resistor to OUT GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 OUT ohm series resistor needed) GND Ground pin for the SRC outputs Clock Request pin for SRC2 outputs. If output is selected for control, then that output is controlled IN as follows: 0 = enabled, 1 = Low-Low Clock Request pin for SRC1 outputs. If output is selected for control, then that output is controlled IN as follows: 0 = enabled, 1 = Low-Low GND Ground pin for the CPU outputs PWR Power supply for differential CPU outputs, nominal 1.05V to 3.3V PWR Supply for CPU core, 3.3V nominal Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with OUT integrated series resistor. (no 33 ohm series resistor needed) True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series OUT resistor.(no 33 ohm series resistor needed) Enter /Exit Power Down. IN 0 = Power Down, 1 = normal operation. PWR Ground pin for the HTT outputs Complementary signal of low-power differential push-pull hypertransport clock with integrated OUT series resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) / 1.8V single ended 66MHz hyper transport clock True signal of low-power differential push-pull hypertransport clock with integrated series OUT resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) /1.8V single ended 66MHz hyper transport clock PWR Supply for HTT clocks, nominal 3.3V. PWR Ref, XTAL power supply, nominal 3.3V
36
SB_SRC0C_LPRS
37
SB_SRC0T_LPRS
38
CLKREQ4#*
39
CLKREQ3#*
40
VDDSATA
41
SRC6C/SATAC_LPRS
42
SRC6T/SATAT_LPRS
43
GNDSATA
44
CLKREQ2#*
45
CLKREQ1#*
46 47 48
GNDCPU VDDCPU_IO VDDCPU
49
CPUKG0C_LPRS
50
CPUKG0T_LPRS
51
PD#
52
GNDHTT
53
HTT0C_LPRS/66M
54
HTT0T_LPRS/66M
55 56
VDDHTT VDDREF
57
REF2/SEL_27
I/O
14.318 MHz reference clock, 3.3V/3.3V Latched input to select 27MHz SS and non SS on SRC7 0 = 100MHz differential spreading SRC clock, 1 = 27MHz non-spreading singled clock on pin 5 and 27MHz spread clock on pin 6.
58
REF1/SEL_SATA
I/O
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select function of SRC6/SATA output 0 = 100MHz differential spreading SRC clock, 1 = 100MHz non-spreading differential SATA clock
59
REF0/SEL_HTT66
I/O
60 61 62 63 64
GNDREF X1 X2 VDD48 48MHz_0
GND IN OUT PWR OUT
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock Frequency. 0 = 100MHz differential HTT clock, 1 = 66MHz 3.3V single ended HTT clock Ground pin for the REF outputs. Crystal input, nominally 14.318MHz Crystal output, nominally 14.318MHz Power pin for the 48MHz outputs and core. 3.3V 48MHz clock output.
1391D—02/02/09
3
ICS9LPRS480
Integrated Circuit Systems, Inc.
REF1/SEL_SATA REF0/SEL_HTT66 GNDREF X1 X2 VDD48 48MHz_0 GND48 SMBCLK SMBDAT VDD27 SRC7C_LPRS/27MHz_NS SRC7T_LPRS/27MHz_SS GND27 SRC4C_LPRS SRC4T_LPRS GNDSRC VDDSRC_IO SRC3C_LPRS SRC3T_LPRS SRC2C_LPRS SRC2T_LPRS VDDSRC VDDSRC_IO GNDSRC SRC1C_LPRS SRC1T_LPRS SRC0C_LPRS SRC0T_LPRS *CLKREQ0# GNDATIG VDDATIG_IO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ICS9LPRS480
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
REF2/SEL_27 VDDREF VDDHTT HTT0T_LPRS/66M HTT0C_LPRS/66M GNDHTT PD# CPUKG0T_LPRS CPUKG0C_LPRS VDDCPU VDDCPU_IO GNDCPU CLKREQ1#* CLKREQ2#* GNDSATA SRC6T/SATAT_LPRS SRC6C/SATAC_LPRS VDDSATA CLKREQ3#* CLKREQ4#* SB_SRC0T_LPRS SB_SRC0C_LPRS VDDSB_SRC VDDSB_SRC_IO GNDSB_SRC SB_SRC1T_LPRS SB_SRC1C_LPRS ATIG0T_LPRS ATIG0C_LPRS ATIG1T_LPRS ATIG1C_LPRS VDDATIG
64-Pin TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor
1391D—02/02/09
4
ICS9LPRS480
Integrated Circuit Systems, Inc.
TSSOP Pin Description PIN #
PIN NAME
PIN TYPE
1
REF1/SEL_SATA
I/O
2
REF0/SEL_HTT66
I/O
3 4 5 6 7 8 9 10 11
GNDREF X1 X2 VDD48 48MHz_0 GND48 SMBCLK SMBDAT VDD27
GND IN OUT PWR OUT GND IN I/O PWR
12
SRC7C_LPRS/27MHz_NS
OUT
13
SRC7T_LPRS/27MHz_SS
OUT
14
GND27
GND
15
SRC4C_LPRS
OUT
16
SRC4T_LPRS
OUT
17 18
GNDSRC VDDSRC_IO
GND PWR
19
SRC3C_LPRS
OUT
20
SRC3T_LPRS
OUT
21
SRC2C_LPRS
OUT
22
SRC2T_LPRS
OUT
23 24 25
VDDSRC VDDSRC_IO GNDSRC
PWR PWR GND
26
SRC1C_LPRS
OUT
27
SRC1T_LPRS
OUT
28
SRC0C_LPRS
OUT
29
SRC0T_LPRS
OUT
30
*CLKREQ0#
IN
31 32
GNDATIG VDDATIG_IO
GND PWR
DESCRIPTION 14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select function of SRC6/SATA output 0 = 100MHz differential spreading SRC clock, 1 = 100MHz non-spreading differential SATA clock 14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock Frequency. 0 = 100MHz differential HTT clock, 1 = 66MHz 3.3V single ended HTT clock Ground pin for the REF outputs. Crystal input, nominally 14.318MHz Crystal output, nominally 14.318MHz Power pin for the 48MHz outputs and core. 3.3V 48MHz clock output. Ground pin for the 48MHz outputs Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. 3.3V Power supply for SRC/27MHz output and 27MHz SS PLL True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)/27MHz 3.3V Single-ended non-spread output for discrete graphics Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)/27MHz 3.3V Single-ended spreading output for discrete graphics Ground for the SRC/27MHz outputs Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Ground pin for the SRC outputs Power supply for differential SRC outputs, nominal 1.05V to 3.3V Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Supply for SRC core, 3.3V nominal Power supply for differential SRC outputs, nominal 1.05V to 3.3V Ground pin for the SRC outputs Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Clock Request pin for SRC0 outputs. If output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = Low-Low Ground pin for the ATIG outputs Power supply for differential ATIG outputs, nominal 1.05V to 3.3V
1391D—02/02/09
5
ICS9LPRS480
Integrated Circuit Systems, Inc.
TSSOP Pin Description (Continued) PIN # PIN NAME 33 VDDATIG 34 35 36 37 38 39 40 41 42 43 44
ATIG1C_LPRS ATIG1T_LPRS ATIG0C_LPRS ATIG0T_LPRS SB_SRC1C_LPRS SB_SRC1T_LPRS GNDSB_SRC VDDSB_SRC_IO VDDSB_SRC SB_SRC0C_LPRS SB_SRC0T_LPRS
45 CLKREQ4#* 46 47 48 49 50
CLKREQ3#* VDDSATA SRC6C/SATAC_LPRS SRC6T/SATAT_LPRS GNDSATA
51 CLKREQ2#* 52 53 54 55 56 57 58 59
CLKREQ1#* GNDCPU VDDCPU_IO VDDCPU CPUKG0C_LPRS CPUKG0T_LPRS PD# GNDHTT
60 HTT0C_LPRS/66M 61 62 63
HTT0T_LPRS/66M VDDHTT VDDREF
64 REF2/SEL_27
PIN TYPE DESCRIPTION PWR Power supply for ATIG core, nominal 3.3V Complementary clock of low-power differential push-pull PCI-Express pair with integrated series OUT resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no OUT 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Complementary clock of low-power differential push-pull PCI-Express pair with integrated series OUT resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no OUT 50ohm shunt resistor to GND and no 33 ohm series resistor needed) Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor OUT to GND and no 33 ohm series resistor needed True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor to GND OUT and no 33 ohm series resistor needed GND Ground pin for the SB_SRC outputs PWR Power supply for differential SB_SRC outputs, nominal 1.05V to 3.3V PWR Supply for SB SRC PLL core, 3.3V nominal Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor OUT to GND and no 33 ohm series resistor needed True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor to GND OUT and no 33 ohm series resistor needed Clock Request pin for SRC4 outputs. If output is selected for control, then that output is controlled as IN follows: 0 = enabled, 1 = Low-Low Clock Request pin for SRC3 outputs. If output is selected for control, then that output is controlled as IN follows: 0 = enabled, 1 = Low-Low PWR Power supply for SATA core logic, nominal 3.3V Complement clock of low power differential SRC/SATA clock pair. (no 50ohm shunt resistor to GND and OUT no 33 ohm series resistor needed) True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm OUT series resistor needed) GND Ground pin for the SRC outputs Clock Request pin for SRC2 outputs. If output is selected for control, then that output is controlled as IN follows: 0 = enabled, 1 = Low-Low Clock Request pin for SRC1 outputs. If output is selected for control, then that output is controlled as IN follows: 0 = enabled, 1 = Low-Low GND Ground pin for the CPU outputs PWR Power supply for differential CPU outputs, nominal 1.05V to 3.3V PWR Supply for CPU core, 3.3V nominal Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated OUT series resistor. (no 33 ohm series resistor needed) True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series OUT resistor.(no 33 ohm series resistor needed) Enter /Exit Power Down. IN 0 = Power Down, 1 = normal operation. PWR Ground pin for the HTT outputs Complementary signal of low-power differential push-pull hypertransport clock with integrated series OUT resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) / 1.8V single ended 66MHz hyper transport clock True signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no OUT 50ohm shunt resistor to GND and no 33 ohm series resistor needed) /1.8V single ended 66MHz hyper transport clock PWR Supply for HTT clocks, nominal 3.3V. PWR Ref, XTAL power supply, nominal 3.3V 14.318 MHz reference clock, 3.3V/3.3V Latched input to select 27MHz SS and non SS on SRC7 I/O 0 = 100MHz differential spreading SRC clock, 1 = 27MHz non-spreading singled clock on pin 12 and 27MHz spread clock on pin 13.
1391D—02/02/09
6
ICS9LPRS480
Integrated Circuit Systems, Inc.
General Description The ICS9LPRS480 is a main clock synthesizer chip that provides all clocks required for ATI RS7xx-based systems.using AMD processors. An SMBus interface allows full control of the device. Block Diagram
X1 X2
REF(2:0)
14.318MHz
OSC
48MHz_(1:0) Fixed PLL 100MHz
SRC6/SATA
100MHz
SS PLL CPU/HTT, SRC, ATIG
SRC(5:0)
100MHz ATIG(2:0) 100MHz DIF/66MHz
HTT0/66MHz
200MHz
CPUKG
SRC7T/27MHz_SS
27MHz SS PLL
27MHz SS PLL
SRC7C/27MHz_NS
SB_SRC(1:0) SS SB_SRC
PD# SEL_27 SEL_SATA SEL_HTT66 SMBCLK
Control Logic
SMBDAT CLKREQ(5:0)#
Power Groups Pin Number VDD 63
VDDIO
Description
GND 1
USB_48 outputs
4
7
SRC/27MHz Outputs
16
10,18 11,17
35
33 34
SB_SRC Core Logic SB_SRC differential outputs (IO's)
40
43
26
24 25
48
SRC Logic Core SRC differential outputs (IO's)
SRC/SATA differential output ATIG Core Logic ATIG differential outputs (IO's)
43 47
CPUKG Core Logic CPUKG differential outputs (IO's)
55
52
HTTCLK output
56
60
REF outputs
1391D—02/02/09
7
ICS9LPRS480
Integrated Circuit Systems, Inc.
Table1: CPU/HTT, SRC and ATIG Frequency Selection Table Byte 0 Byte 3 HTT Differential HTT CPU Single-ended Bit0 Bit3 Bit2 Bit1 Bit0 (MHz) CPU CPU CPU CPU SEL_HTT66 = 1 SEL_HTT66 = 0 SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 173.63 57.88 86.81 0 0 0 0 1 177.17 59.06 88.58 0 0 0 1 0 180.78 60.26 90.39 0 0 0 1 1 184.47 61.49 92.24 0 0 1 0 0 188.24 62.75 94.12 0 0 1 0 1 192.08 64.03 96.04 0 0 1 1 0 196.00 65.33 98.00 0 0 1 1 1 200.00 66.67 100.00 0 1 0 0 0 204.00 68.00 102.00 0 1 0 0 1 208.08 69.36 104.04 0 1 0 1 0 212.24 70.75 106.12 0 1 0 1 1 216.49 72.16 108.24 0 1 1 0 0 220.82 73.61 110.41 0 1 1 0 1 225.23 75.08 112.62 0 1 1 1 0 229.74 76.58 114.87 0 1 1 1 1 234.33 78.11 117.17 1 0 0 0 0 173.63 57.88 86.81 1 0 0 0 1 177.17 59.06 88.58 1 0 0 1 0 180.78 60.26 90.39 1 0 0 1 1 184.47 61.49 92.24 1 0 1 0 0 188.24 62.75 94.12 1 0 1 0 1 192.08 64.03 96.04 1 0 1 1 0 196.00 65.33 98.00 1 0 1 1 1 200.00 66.67 100.00 1 1 0 0 0 204.00 68.00 102.00 1 1 0 0 1 208.08 69.36 104.04 1 1 0 1 0 212.24 70.75 106.12 1 1 0 1 1 216.49 72.16 108.24 1 1 1 0 0 220.82 73.61 110.41 1 1 1 0 1 225.23 75.08 112.62 1 1 1 1 0 229.74 76.58 114.87 1 1 1 1 1 234.33 78.11 117.17
1391D—02/02/09
8
SRC/ATIG
86.81 88.58 90.39 92.24 94.12 96.04 98.00 100.00 102.00 104.04 106.12 108.24 110.41 112.62 114.87 117.17 86.81 88.58 90.39 92.24 94.12 96.04 98.00 100.00 102.00 104.04 106.12 108.24 110.41 112.62 114.87 117.17
Spread %
Off
-0.5%
CPU OverClock % -13% -11% -10% -8% -6% -4% -2% 0% 2% 4% 6% 8% 10% 13% 15% 17% -13% -11% -10% -8% -6% -4% -2% 0% 2% 4% 6% 8% 10% 13% 15% 17%
ICS9LPRS480
Integrated Circuit Systems, Inc.
Table 2: SB_SRC Frequency Selection Table Byte 4 Byte 0 SRC Spread Bit0 Bit3 Bit2 Bit1 Bit0 (MHz) % SB SB SB SB SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 80.00 0 0 0 0 1 81.25 0 0 0 1 0 82.63 0 0 0 1 1 84.00 0 0 1 0 0 85.25 0 0 1 0 1 86.63 0 0 1 1 0 88.00 0 0 1 1 1 89.25 Off 0 1 0 0 0 90.63 0 1 0 0 1 92.00 0 1 0 1 0 93.25 0 1 0 1 1 94.63 0 1 1 0 0 96.00 0 1 1 0 1 97.25 0 1 1 1 0 98.63 0 1 1 1 1 100.00 1 0 0 0 0 80.00 1 0 0 0 1 81.25 1 0 0 1 0 82.63 1 0 0 1 1 84.00 1 0 1 0 0 85.25 1 0 1 0 1 86.63 1 0 1 1 0 88.00 1 0 1 1 1 89.25 -0.50% 1 1 0 0 0 90.63 1 1 0 0 1 92.00 1 1 0 1 0 93.25 1 1 0 1 1 94.63 1 1 1 0 0 96.00 1 1 1 0 1 97.25 1 1 1 1 0 98.63 1 1 1 1 1 100.00
SB_SRC OverClock % -20% -19% -17% -16% -15% -13% -12% -11% -9% -8% -7% -5% -4% -3% -1% 0% 20% -19% -17% -16% -15% -13% -12% -11% -9% -8% -7% -5% -4% -3% -1% 0%
1391D—02/02/09
9
ICS9LPRS480
Integrated Circuit Systems, Inc.
Table3: 27Mhz_Spread and Frequency Selection Table SS Enable B2b1
SS3 Byte 4 bit 7
SS2 Byte 4 bit 6
SS1 Byte 4 bit 5
SS0 Byte 4 bit 4
27MHz_Spread (MHz)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00
1391D—02/02/09
10
Spread % (when enabled)
No Spread
-0.50 -1.00 -1.50 -2.00 -0.75 -1.25 -1.75 -2.25 +/-0.25 +/-0.5 +/-0.75 +/-1.0 +/-0.25 +/-0.5 +/-0.75 +/-1.0
Down Down Down Down Down Down Down Down Center Center Center Center Center Center Center Center
ICS9LPRS480
Integrated Circuit Systems, Inc.
Differential Output Power Management Table PD#
CLKREQ#
1 0 1 X
SMBus Register OE
True output
Complement Output
Free-Run
0 X
Enable
Running
X
Low/20K
1 X
Enable
Running
Disable
Low/20K
True output
Complement Output
CLKREQ# Selected
Running
Running
Running
Low
Low/20K
Low
Running
Low/20K
Low
Low
Low/20K
Low
Note: 20K means 20Kohm Pull Down Singled-ended Power Management Table PD#
SMBus Register OE
48MHz
27MHz
HTT66MHz
REF(2:0)
1
Enable
Running
Running
Running
Running
0
Enable
Low
Low
Low
Hi-Z
1391D—02/02/09
11
ICS9LPRS480
Integrated Circuit Systems, Inc.
Absolute Maximum Rating PARAMETER SYMBOL CONDITIONS 3.3V Supply Voltage VDDxxx Storage Temperature Ts Ambient Operating Temp Tambient Case Temperature Tcase Input ESD protection HBM ESD prot 1 Guaranteed by design and characterization, not 100% tested in production.
MIN
TYP 3.3
MAX GND + 3.9V 150 70 115
UNITS V ° C °C °C V
NOTES 1 1 1 1 1
TYP 3.3
MAX 3.465 VDD + 0.3 0.8 VDD + 0.3 0.4 VDD + 0.3 0.4 VDD + 0.3 0.4 5
UNITS V V V V V V V V V uA
NOTES 1 1 1 1 1 1 1 1 1 1
-5
uA
1
-200
uA
1
-65 0 2000
Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER 3.3V Core Supply Voltage Input High Voltage Input Low Voltage Input High Voltage - SEL_27 Input Low Voltage - SEL_27 Input High Voltage - SEL_SATA Input Low Voltage - SEL_SATA Input High Voltage - SEL_HTT66 Input Low Voltage - SEL_HTT66 Input High Current
SYMBOL VDDxxx VIH VIL VIH VIL VIH VIL VIH VIL I IH
CONDITIONS* VDD = 3.3 V +/-5% VDD = 3.3 V +/-5% VDD = 3.3 V +/-5% VDD = 3.3 V +/-5% VDD = 3.3 V +/-5% VDD = 3.3 V +/-5% VDD = 3.3 V +/-5% VDD = 3.3 V +/-5% VIN = V DD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors
MIN 3.135 2 VSS - 0.3 2 VSS - 0.3 2 VSS - 0.3 2 VSS - 0.3 -5
VIH_FS
VDD = 3.3 V +/-5%
0.7
VDD + 0.3
V
1
VIL_FS
VDD = 3.3 V +/-5%
VSS - 0.3
0.35
V
1
225
mA
1
2 7 5 6 5
mA MHz nH pF pF pF
1 2 1 1 1 1
1.8
ms
1
33
kHz
1
300
us
1
I IL1 Input Low Current I IL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Current
IDD3.3OP
Powerdown Current Input Frequency Pin Inductance
IDD3.3PD Fi Lpin CIN COUT CINX
Input Capacitance
Clk Stabilization Modulation Frequency Tdrive_PD
TSTAB
3.3V VDD current, all outputs driven all diff pairs low/low VDD = 3.3 V +/-5% Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of PD rise time of
14.31818
30
Tfall_PD 5 ns 1 Trise_PD 5 ns 1 SMBus Voltage VDDSMB 2.7 5.5 V 1 Low-level Output Voltage VOLSMB @ IPULLUP 0.4 V 1 Current sinking at 4 6 mA 1 IPULLUPSMB VOL = 0.4 V SMBCLK/SMBDAT (Max VIL - 0.15) to TRSMB 1000 ns 1 Clock/Data Rise Time (Min VIH + 0.15) SMBCLK/SMBDAT (Min VIH + 0.15) to TFSMB 300 ns 1 Clock/Data Fall Time (Max VIL - 0.15) *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 1 Guaranteed by design and characterization, not 100% tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 1391D—02/02/09
12
ICS9LPRS480
Integrated Circuit Systems, Inc.
AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT PARAMETER Crossing Point Variation Frequency - CPU Frequency - HTT Long Term Accuracy Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation CPU, DIF HTT Jitter - Cycle to Cycle Accumulated Jitter Peak to Peak Differential Voltage Differential Voltage Duty Cycle
SYMBOL ∆VCROSS fCPU fHTT ppm SRISE SFALL tSLVAR CPUJC2C tJACC VD(PK-PK) VD DCYC
CONDITIONS Single-ended Measurement Spread Specturm On Spread Specturm On Spread Specturm Off Differential Measurement Differential Measurement Single-ended Measurement Differential Measurement See Notes Differential Measurement Differential Measurement Differential Measurement
Amplitude Variation
∆VD
Change in VD DC cycle to cycle
MIN
TYP
400 200 45
MAX 140 200 100 +300 10 10 20 150 1 2400 1200 55
UNITS mV MHz MHz ppm V/ns V/ns % ps ns mV mV %
NOTES 1,2,5 1,3 1,3 1,11 1,4 1,4 1 1,6 1,7 1,8 1,9 1
-75
75
mV
1,10
198.8 99.4 -300 0.5 0.5
CPUSKEW10 CPU[1:0] Skew Differential Measurement 100 ps Notes on Electrical Characteristics: 1 Guaranteed by design and characterization, not 100% tested in production. 2 Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is not important 3 Minimum Frequency is a result of 0.5% down spread spectrum 4 Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate spec when crossing through this region. 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 6 Max difference of tCYCLE between any two adjacent cycles. 7
1
Accumulated tjc.over a 10 µs time period, measured with JIT2 TIE at 50ps interval.
8
VD(PK-PK) is the overall magnitude of the differential signal. VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V VD. VD(max) is the largest amplitude allowed. 10 The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of the 9
11
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
AC Electrical Characteristics - Low-Power DIF Outputs: SRC, SB_SRC and ATIG PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
NOTES
Rising Edge Slew Rate
tSLR
Differential Measurement
2.5
TYP
8
V/ns
1,2
Falling Edge Slew Rate
tFLR
Differential Measurement
2.5
8
V/ns
1,2
% mV mV mV mV mV % ps ps ps ps
1 1 1 1 1,3,4 1,3,5 1 1 1 1 1
Single-ended Measurement 20 Slew Rate Variation t SLVAR Includes overshoot 1150 Maximum Output Voltage VHIGH Minimum Output Voltage VLOW Includes undershoot -300 Differential Voltage Swing VSWING Differential Measurement 300 Single-ended Measurement 300 550 Crossing Point Voltage VXABS Crossing Point Variation VXABSVAR Single-ended Measurement 140 Duty Cycle DCYC Differential Measurement 45 55 SRC, ATIG, Jitter - Cycle to Cycle SRCJ C2C Differential Measurement 125 SRC[5:0] Skew SRCSKEW Differential Measurement 250 Differential Measurement 100 SB_SRC[1:0] Skew SRCSKEW ATIG[2:0] Skew SRCSKEW Differential Measurement 100 Notes on Electrical Characteristics: 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 1391D—02/02/09
13
CLK
ICS9LPRS480
Integrated Circuit Systems, Inc.
Electrical Characteristics - Single-ended HTT 66MHz Clock PARAMETER Long Accuracy
SYMBOL ppm
CONDITIONS MIN TYP MAX UNITS see Tperiod min-max values -300 300 ppm 66.67MHz output nominal 14.9955 15.0045 ns HTT66 Clock period Tperiod 66.67MHz output spread 14.9955 15.0799 ns Output High Voltage VOH IOH = -1 mA 1.6 1.8 V I OL = 1 mA 0 0.2 V Output Low Voltage VOL Rise Time t r1 VOL = 0.36 V, VOH = 1.44 V 1.5 ns VOH = 1.44 V, VOL = 0.36 V 1.5 ns Fall Time t f1 Duty Cycle dt1 VT = 0.9 V 45 55 % VT = 0.9 V 300 ps Jitter, Cycle to cycle tjcyc-cyc Jitter, Long Term t LTJ VT = 0.9 V 1 ns *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33Ω (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz
NOTES 1,2 2 2 1 1 1 1 1 1 1
Electrical Characteristics - USB - 48MHz PARAMETER Long Accuracy Clock period Clock Low Time Clock High Time Output High Voltage Output Low Voltage
SYMBOL ppm Tperiod Tlow Thigh VOH VOL
CONDITIONS* MIN TYP see Tperiod min-max values -100 48.00MHz output nominal 20.8229 Measure from < 0.6V 9.3750 Measure from > 2.0V 9.3750 IOH = -1 mA 2.4 I OL = 1 mA -33 V OH @MIN = 1.0 V Output High Current I OH V OH@MAX = 3.135 V 30 VOL @ MIN = 1.95 V Output Low Current I OL VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 0.5 Rise Time tr_USB VOH = 2.4 V, VOL = 0.4 V 0.5 Fall Time tf_USB VT = 1.5 V 45 Duty Cycle dt1 VT = 1.5 V Group Skew tskew VT = 1.5 V tjcyc-cyc Jitter, Cycle to cycle *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33Ω (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 2 ICS recommended and/or chipset vendor layout guidelines must be followed to meet this specification
1391D—02/02/09
14
MAX 100 20.8344 11.4580 11.4580 0.55 -33 38 1.5 1.5 55 250 130
UNITS ppm ns ns ns V V mA mA mA mA ns ns % ps ps
NOTES 1,2 2 2 2 1 1 1 1 1 1 1 1 1 1 1,2
ICS9LPRS480
Integrated Circuit Systems, Inc.
Electrical Characteristics - 27MHz PARAMETER
SYMBOL
CONDITIONS
Long Accuracy
ppm
see Tperiod min-max values
Clock period Output High Voltage(27SS, 27NSS) Output Low Voltage
Tperiod VOH VOL
27.000MHz output nominal IOH = -1 mA I OL = 1 mA VOH = 1.0 V VOH = 3.135 V VOL = 1.95 V VOL = 0.4 V Rising/Falling edge rate VT @ 20%-80% VT = 1.5 V Long Term (10us) VT = 1.5 V
Output High Current
I OH
Output Low Current
I OL
Edge Rate
t slewr/f
Duty Cycle
dt1 tltj
Jitter
tjcyc-cyc
MIN -50 -15 37.0365 2.1
TYP
MAX 50 15 37.0376
27
ns V V mA mA mA mA
NOTES 1,2 1,2,3 2 1,10 1 1,10 1,10 1,10 1,10
4
V/ns
1
55 300 200
% ps ps
1 1 1
UNITS ppm ns ns ns V V
NOTES 1,2 2 2 2 1 1
mA
1
mA
1
ns ns ps % ps
1 1 1 1 1
0.55 -29 -23 29
1 45
2
UNITS ppm
1
Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 10 VDD = 3.3V 2
Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Clock Low Time Clock High Time Output High Voltage Output Low Voltage
SYMBOL ppm Tperiod Tlow Thigh VOH VOL
CONDITIONS MIN TYP MAX see Tperiod min-max values -300 300 14.318MHz output nominal 69.8270 69.8550 Measure from < 0.6V 30.9290 37.9130 Measure from > 2.0V 30.9290 37.9130 I OH = -1 mA 2.4 IOL = 1 mA 0.4 VOH @MIN = 1.0 V, -29 -23 Output High Current IOH VOH@MAX = 3.135 V VOL @MIN = 1.95 V, 29 27 Output Low Current IOL VOL @MAX = 0.4 V Rise Time t r1 VOL = 0.4 V, VOH = 2.4 V 1 1.5 Fall Time t f1 VOH = 2.4 V, VOL = 0.4 V 1 1.5 Skew tsk1 VT = 1.5 V 250 Duty Cycle dt1 VT = 1.5 V 45 55 Jitter tjcyc-cyc VT = 1.5 V 300 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33Ω (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
1391D—02/02/09
15
ICS9LPRS480
Integrated Circuit Systems, Inc.
General SMBus serial interface information for the ICS9LPRS480 How to Write:
How to Read:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit
• • • •
• • • • • • • •
• • • • • • • • • •
Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite
Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK RT Repeat starT Slave Address D3(H) RD ReaD
Data Byte Count = X ACK Beginning Byte N ACK X Byte
ACK Data Byte Count = X ACK Beginning Byte N
Byte N + X - 1
ACK X Byte
ACK P
stoP bit
Byte N + X - 1 N P
1391D—02/02/09
16
Not acknowledge stoP bit
ICS9LPRS480
Integrated Circuit Systems, Inc.
SMBus Table: Latched Input Readback Output Enable Control Register Byte
0
Name
Description
Type
0
1
Bit 7
SEL_HTT66 readback
Hypertransport Select
R
100MHz Differential HTT clock
Bit 6
SEL_SATA readback
SATA Select
R
SRC6/SATA pair is SRC SS capable output
Bit 5
REF0_OE
Output Enable
RW
Hi-Z
66 MHz 3.3V Singleended HTT clock SRC6/SATA pair is SATA non-spread output Enabled
Bit 4
REF1_OE
Output Enable
RW
Hi-Z
Enabled
Bit 3
REF2_OE
Output Enable
RW
Hi-Z
Enabled
Reserved
Bit 2
Byte
Bit 1
48MHz_0_OE
Bit 0
SS_Enable
Byte
SMBus Table:Output Enable Control Register Name Control Function
1 Bit Bit Bit Bit Bit Bit Bit Bit
Output Enable Spread Spectrum Enable (CPU, SRC, SB_SRC, ATIG)
7 6 5 4 3 2 1 0
SRC7/27MHz_OE SRC6/SATA_OE Enable SRC4_OE SRC3_OE SRC2_OE SRC1_OE SRC0_OE
Bit 7 Bit 6
SB_SRC1_OE SB_SRC0_OE
Byte
ATIG1_OE ATIG0_OE
RW
Spread Off
Spread On
0
Type
RW RW
Bit 1
27MHz_SS_Enable
Bit 0
Reserved
RW
0
1
Default
Low/Low Low/Low
Enabled Enabled
Low/Low Low/Low Low/Low Low/Low Low/Low
Enabled Enabled Enabled Enabled Enabled
1 1 0 1 1 1 1 1
1
Default
Enabled Enabled
1 1
7 6 5 4
CPU0_OE SEL_27 readback HTT/66MHz_OE
1
1
Enabled Enabled
1 1
RW
Spread Off
Spread On
0
RW
-
-
X
Bit 3
CPU_FS3
CPU Frequency Select
RW
Bit 2
CPU_FS2
CPU Frequency Select
RW
Bit 1
CPU_FS1
CPU Frequency Select
RW
Bit 0
CPU_FS0
CPU Frequency Select LSB
RW
17
These bits program the slew rate of the single ended outputs. The maximum slew rate is 1.9V/ns and the minimum slew rate is 1.1V/ns. The slew rate selection is as follows: 11 = 1.9V/ns 10 = 1.6V/ns 01 = 1.1V/ns 00 = tristated Low/Low Low/Low
Output enable RW SRC7/27MHz Select R Reserved Output Enable RW
1391D—02/02/09
Low/Low Low/Low
RW RW
SMBus Table: CPU/HTT Frequency Control Register Name Control Function Type
3 Bit Bit Bit Bit
Output Enable Output Enable Spread Spectrum Enable 27MHz_SS Reserved
1 1
Bit 4
Bit 3 Bit 2
1
Enabled
RW RW Reserved Output Enable RW Output Enable RW Output Enable RW Output Enable RW Output Enable RW
Slew Rate Control
1
Low
Bit 5 48MHz_0_Slew Rate
Latch
RW
Output Enable Output Enable
Output Enable Output Enable
Latch
0
SMBus Table: Output Enable and 48MHz Slew Rate Control Register Name Control Function Type 0
2
Default
0
1
Default
Low/Low SRC7 Output
Enable 27MHz Output
Low/Low
Enabled
1 Latch 1 1
See CPU/HTT/SRC/ATIG Frequency Select Table Default value corresponds to 200MHz. Note that the HTT frequency tracks the CPU frequency.
0 1 1 1
ICS9LPRS480
Integrated Circuit Systems, Inc.
Byte
Byte
SMBus Table: SB_SRC Frequency Control Register Name Control Function Type
4
RW RW RW
Default
Bit 4
S0
Bit 3
SB_SRC_FS3
SB_SRC Frequency Select
RW
Bit 2
SB_SRC_FS2
SB_SRC Frequency Select
RW
Bit 1
SB_SRC_FS1
SB_SRC Frequency Select
RW
1
Bit 0
SB_SRC_FS0
SB_SRC Freq. Select LSB
RW
1
27_SSC Spread Select
RW
SMBus Table: 27MHz Slew Rate Control Register Name Control Function Type
5
27M_SS_Slew Rate
Slew Rate Control
RW
Bit 6 Bit 5 27M_NS_Slew Rate
Slew Rate Control
RW
Bit 4 Bit Bit Bit Bit
3 2 1 0
7 6 5 4 3 2 1 0
SB_SRC Source Selection RW Reserved Reserved Reserved
SRC Diff AMP SRC Diff AMP CPU Diff AMP CPU Diff AMP SB_SRC Diff AMP SB_SRC Diff AMP
7 6 5 4 3 2 1 0
RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0
Type
REVISION ID
VENDOR ID
1391D—02/02/09
18
S[1:0]: 00 = -0.5% Default, 01 =1.0%, 10 = -1.5%, 11 = -2%. See Table 3: 27Mhz_Spread, LCDCLK Spread and Frequency Selection Table for additional selections.
0 0 0 0 1
See SB_SRC Frequency Select Table.
0
1
These bits program the slew rate of the single ended outputs. The maximum slew rate is 1.9V/ns and the minimum slew rate is 1.1V/ns. The slew rate selection is as follows: 11 = 1.9V/ns 10 = 1.6V/ns 01 = 1.1V/ns 00 = tristated SB_SRC PLL
1
Default 1 1 1 1
SRC PLL
1 0 0 0
0
1
Default
00 = 700mV 10 = 900mV 00 = 700mV 10 = 900mV 00 = 700mV 10 = 900mV
01 = 800mV 11 = 1000mV 01 = 800mV 11 = 1000mV 01 = 800mV 11 = 1000mV
0 1 0 1 0 1 X X
Type
0
1
Default
R R R R R R R R
-
-
0 0 0 1 0 0 0 1
SRC Differential output RW Amplitude Control RW CPU Differential output RW Amplitude Control RW SB_SRC Differential output RW Amplitude Control RW Reserved Reserved
SMBus Table: Vendor & Revision ID Register Name Control Function
7 Bit Bit Bit Bit Bit Bit Bit Bit
SB_SRC Source
SMBus Table: I/O Vout Control Register Name Control Function
6 Bit Bit Bit Bit Bit Bit Bit Bit
Byte
1
S3 S2 S1
Bit 7
Byte
0
Bit 7 Bit 6 Bit 5
ICS9LPRS480
Integrated Circuit Systems, Inc.
Byte
Bit Bit Bit Bit Bit Bit Bit Bit
Byte
SMBus Table: Byte Count Register Name Control Function
8 7 6 5 4 3 2 1 0
1
Determines the number of bytes that are read back from the device. Default is 0F hex.
Default 0 0 0 0 1 1 1 1
0
1
Default
HWD_EN
Watchdog Hard Alarm Enable
RW
Disable and Reload Hartd Alarm Timer, Clear WD Hard status bit.
Enable Timer
0
Bit 6
SWD_EN
Watchdog Soft Alarm Enable
RW
Disable
Enable
0
Bit 5 Bit 4
WD Hard Status WD Soft Status
R R
Normal Normal
Alarm Alarm
X X
Bit 3
WDTCtrl
290ms Base
1160ms Base
Bit 2 Bit 1 Bit 0
HWD2 HWD1 HWD0
WD Hard Alarm Status WD Soft Alarm Status Watch Dog Alarm Time base Control WD Hard Alarm Timer Bit 2 WD Hard Alarm Timer Bit 1 WD Hard Alarm Timer Bit 0
10
SWD2 SWD1 SWD0 WD SF4 WD SF3 WD SF2 WD SF1
Bit 0
WD SF0
11 Bit Bit Bit Bit Bit Bit Bit Bit
7 6 5 4 3 2 1 0
RW RW RW RW
These bits represent the number of Watch Dog Time Base Units that pass before the Watch Alarm expires. Default is 7 X 290ms = 2s.
SMBus Table: WD Timer Safe Frequency Control Register Name Control Function Type
7 6 5 4 3 2 1
Bit Bit Bit Bit Bit Bit Bit
Byte
0
SMBus Table: WatchDog Timer Control Register Name Control Function Type
9 Bit 7
Byte
BC5 BC4 BC3 BC2 BC1 BC0
Type
Reserved Reserved Byte Count bit 5 (MSB) RW Byte Count bit 4 RW Byte Count bit 3 RW Byte Count bit 2 RW Byte Count bit 1 RW Byte Count bit 0 (LSB) RW
WD Soft Alarm Timer Bit 2 WD Soft Alarm Timer Bit 1 WD Soft Alarm Timer Bit 0
Watch Dog Safe Freq Programming bits
RW RW RW RW RW RW RW RW
SMBus Table: CPU PLL Frequency Control Register Name Control Function Type N Div2 N Div1 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0
N Divider Prog bit 2 N Divider Prog bit 1
M Divider Programming bits
1391D—02/02/09
19
RW RW RW RW RW RW RW RW
0
1
These bits represent the number of Watch Dog Time Base Units that pass before the Watch Alarm expires. Default is 7 X 290ms = 2s. These bits configure the safe frequency that the device returns to if the Watchdog Timer expires. The value show here corresponds to the power up default of the device. See the various Frequency Select Tables for the exact frequencies.
0
1
The decimal representation of M and N Divider in Byte 11 and 12 will configure the VCO frequency. Default at power up = Byte 3 Rom table. VCO Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0) .
0 1 1 1
Default 1 1 1 0 0 1 1 1
Default X X X X X X X X
ICS9LPRS480
Integrated Circuit Systems, Inc.
Byte
12 7 6 5 4
N Div10 N Div9 N Div8 N Div7
Bit 3
N Div6
Bit 2 Bit 1 Bit 0
N Div5 N Div4 N Div3
Bit Bit Bit Bit
Byte
13 Bit Bit Bit Bit Bit Bit Bit Bit
Byte
7 6 5 4 3 2 1 0
14 Bit Bit Bit Bit Bit Bit Bit Bit
Byte
7 6 5 4 3 2 1 0
15 Bit 7
Byte
SMBus Table: CPU PLL Frequency Control Register Name Control Function Type
N Divider Programming b(10:3)
RW RW RW RW RW RW RW RW
0
The decimal representation of M and N Divider in Byte 11 and 12 will configure the VCO frequency. Default at power up = Byte 3 Rom table. VCO Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0) .
SMBus Table: CPU PLL Spread Spectrum Control Register Name Control Function Type SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Spread Spectrum Programming b(7:0)
RW RW RW RW RW RW RW RW
SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8
SMBUS Table: CPU Output Divider Register Name Control Function CPU NDiv0
LSB N Divider Programming
Type RW
0
1
Bytes 13 and 14 set the CPU/HTT/SRC/ATIG spread pecentage.Please contact ICS for the appropriate values.
SMBus Table: CPU PLL Spread Spectrum Control Register Name Control Function Type Reserved RW RW RW Spread Spectrum RW Programming b(14:8) RW RW RW
1
0
1
Bytes 13 and 14 set the CPU/HTT/SRC/ATIG spread pecentage.Please contact ICS for the appropriate values.
0
1
CPU M/N programming.
Default X X X X X X X X
Default X X X X X X X X
Default X X X X X X X X
Default X
Bit 6
Reserved
X
Bit 5
Reserved
X
Bit 4
Reserved
Bit 3
CPUDiv3
Bit 2
CPUDiv2
Bit 1
CPUDiv1
Bit 0
CPUDiv0
16 Bit Bit Bit Bit Bit Bit Bit Bit
7 6 5 4 3 2 1 0
CPU Divider Ratio Programming Bits
0000:/2 ; 0100:/4
1000:/8 ; 1100:/16
X
RW
0001:/3 ; 0101:/6
1001:/12 ; 1101:/24
X
RW
0010:/5 ; 0110:/10
1010:/20 ; 1110:/40
X
RW
0011:/15 ; 0111:/18
1011:/36 ; 1111:/72
X
0
1
Default
SMBUS Table: SB_SRC Frequency Control Register Name Control Function Type N Div2 N Div1 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0
N Divider Prog bit 2 N Divider Prog bit 1
M Divider Programming bit (5:0)
1391D—02/02/09
20
X
RW
RW RW RW RW RW RW RW RW
The decimal representation of M and N Divider in Byte 16 and 17 configure the SB_SRC VCO frequency. See M/N Caculation Tables for VCO frequency formulas.
X X X X X X X X
ICS9LPRS480
Integrated Circuit Systems, Inc.
Byte
17 Bit Bit Bit Bit Bit Bit Bit Bit
Byte
18 Bit Bit Bit Bit Bit Bit Bit Bit
Byte
7 6 5 4 3 2 1 0
20 Bit Bit Bit Bit Bit Bit Bit Bit
Byte
7 6 5 4 3 2 1 0
19 Bit Bit Bit Bit Bit Bit Bit Bit
Byte
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
21 Bit Bit Bit Bit Bit Bit Bit Bit
7 6 5 4 3 2 1 0
SMBUS Table: SB_SRC Frequency Control Register Name Control Function Type N Div10 N Div9 N Div8 N Div7 N Div6 N Div5 N Div4 N Div3
N Divider Programming Byte16 bit(7:0) and Byte15 bit(7:6)
RW RW RW RW RW RW RW RW
0
The decimal representation of M and N Divider in Byte 16 and 17 configure the SB_SRC VCO frequency. See M/N Caculation Tables for VCO frequency formulas.
SMBUS Table: SB_SRC Spread Spectrum Control Register Name Control Function Type SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Spread Spectrum Programming bit(7:0)
RW RW RW RW RW RW RW RW
Spread Spectrum Programming bit(14:8)
RW RW RW RW RW RW RW RW
SMBUS Table: SB_SRC Output Divider Control Register Name Control Function Type SB_SRC NDiv0
SB_SRCDiv3 SB_SRCDiv2 SB_SRCDiv1 SB_SRCDiv0
LSB N Divider Programming RW Reserved Reserved Reserved RW SRC Divider Ratio RW Programming Bits RW RW
SMBus Table: Device ID register Name Control Function Device ID7 Device ID6 Device ID5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID0
Type R R R R R R R R
Device ID
1391D—02/02/09
21
0
1
Bytes 18 and 19 set the the SB_SRC spread pecentages. Please contact ICS for the appropriate values.
SMBUS Table: SB_SRC Spread Spectrum Control Register Name Control Function Type SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8
1
0
1
Bytes 18 and 19 set the the SB_SRC spread pecentages. Please contact ICS for the appropriate values.
0
1
SB_SRC M/N programming.
Default X X X X X X X X
Default X X X X X X X X
Default X X X X X X X X
Default
0000:/2 ; 0100:/4 0001:/3 ; 0101:/6 0010:/5 ; 0110:/10 0011:/15 ; 0111:/18
1000:/8 ; 1100:/16 1001:/12 ; 1101:/24 1010:/20 ; 1110:/40 1011:/36 ; 1111:/72
X X X X X X X X
0
1
Default
76 hex
0 1 1 1 0 1 1 0
ICS9LPRS480
Integrated Circuit Systems, Inc.
Byte
22 Bit 7 Bit Bit Bit Bit Bit Bit Bit
Byte
23 Bit Bit Bit Bit Bit Bit Bit Bit
Byte
6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
24
CPU/HTT/SRC/ATIG M/N En SB_SRC M/N En Reserved Reserved Reserved Reserved Reserved Reserved
CPU/HTT/SRC/ATIG PLL M/N Prog. Enable SB_SRC M/N Prog. Enable Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved CLKREQ4# controls CLKREQ3# controls CLKREQ2# controls CLKREQ1# controls CLKREQ0# controls
SRC4 SRC3 SRC2 SRC1 SRC0
M/N Prog. Disabled
M/N Prog. Enabled
0
M/N Prog. Enabled -
0 0 0 0 X X X
0
1
Default
Not Controlled Not Controlled Not Controlled Not Controlled Not Controlled
Controlled Controlled Controlled Controlled Controlled
0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW
SMBus Table: Test Mode Configuration Register Name Control Function Type
0
1
Default
All ouputs are REF/N
0
DIAG mode Enabled
0
R R R R
Normal mode Reset forces B24[6:4,2,0] to 0 unlocked unlocked unlocked unlocked
Locked Locked Locked Locked
HW HW HW HW
R
Not Accurate
Accurate
HW
Selects Test Mode
RW
Bit 6
DIAG Enable#
DIAG enable CPU and LCD PLL
RW
CPU PLL_LOCK signal 27MHz PLL_LOCK signal Fixed PLL_LOCK signal SRC PLL_LOCK signal
CPU PLL Lock Detect 27MHz PLL Lock Detect Fixed PLL Lock Detect Fixed PLL Lock Detect
Frequency Check
Primary PLL or external crystal Frequency Accuracy
Bit 1
Bit 0
25 Bit 7 Bit 6 Bit 5
PWRGD Status
Power on Reset Status
SMBus Table:Slew Rate Select Register Name Control Function
R
HW
Type
0
1
Default
Reserved Reserved
RW RW
-
-
0 0
REF2_Slew Rate
Slew Rate Control
RW
REF1_Slew Rate
Slew Rate Control
RW
Bit 2 Bit 1
Invalid voltage levels on Valid voltage levels any of the VDDs. exist on all the VDD. CKPWRGD is not CKPWRGD is asserted asserted or external and external XTAL is XTAL not detected. detected.
Reserved Reserved
Bit 4 Bit 3
Default
M/N Prog. Disabled -
Test_Md_Sel
5 4 3 2
1
RW
SMBus Table: CLKREQ# Configuration Register Name Control Function Type Reserved Reserved Reserved CLKREQ4#_Enable CLKREQ3#_Enable CLKREQ2#_Enable CLKREQ1#_Enable CLKREQ0#_Enable
0
RW RW RW RW RW RW RW
Bit 7
Bit Bit Bit Bit
Byte
SMBus Table: CLKREQ# Configuration Register Name Control Function Type
REF0_Slew Rate
Slew Rate Control
Bit 0
1391D—02/02/09
22
RW
These bits program the slew rate of the single ended outputs. The maximum slew rate is 1.9V/ns and the minimum slew rate is 1.1V/ns. The slew rate selection is as follows: 11 = 1.9V/ns 10 = 1.6V/ns 01 = 1.1V/ns 00 = tristated
1 1 1 1 1 1
ICS9LPRS480
Integrated Circuit Systems, Inc.
(Ref. )
Seating Plane
(N D - 1)x e (Ref. )
A1
Index Area
A3
N
L
N
Anvil Singulation
1
Top View
(N E - 1)x e
E2
(Ref. )
2
Sawn Singulation
b (Ref.)
A
D
e (Typ.) 2 If N D & N E are Even 1 2
E2
OR
E
ND & NE Even
e D2 2
ND & NE Odd
Thermal Base
D2
Chamfer 4x 0.6 x 0.6 max OPTIONAL
C 0.08
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE
SYMBOL N ND NE
DIMENSIONS (mm) SYMBOL A A1 A3 b e D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX.
64L 64 16 16
Ordering Information 9LPRS480yKLFT
MIN. MAX. 0.8 1.0 0 0.05 0.25 Reference 0.18 0.3 0.50 BASIC 9.00 x 9.00 7.00 7.25 7.00 7.25 0.30 0.50
*Due to package size constraints actual top side marking may differ from the full orderable part number. Example:
XXXX y K LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type K = MLF Revision Designator Device Type
1391D—02/02/09
23
ICS9LPRS480
Integrated Circuit Systems, Inc.
c
N
SYMBOL L
E1
A A1 A2 b c D E E1 e L N α aaa
E
INDEX AREA
1 2
α D
6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° -0.10 -.004
VARIATIONS A
A2
N 64
A1
- Ce b
D mm. MIN 16.90
D (inch) MAX 17.10
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
SEATING PLANE
aaa C
Ordering Information 9LPRS480yGLFT Example:
XXXX y G LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type G = TSSOP Revision Designator Device Type
1391D—02/02/09
24
MIN .665
MAX .673
ICS9LPRS480
Integrated Circuit Systems, Inc.
Revision History Rev. A B C D
Issue Date 7/8/2008 7/29/2008 9/18/2008 2/2/2009
1391D—02/02/09
Description Going to Release. Removed Table 4 and updated 27MHz electrical characteristics. Updated Input/Supply/Common Output Parameters. Changed Rs Value from 22 Ohm to 33 Ohm.
Page # 10-11 12 14, 15
This product is protected by United States Patent NO. 7,342,420 and other patents.
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