사본 - Ddr2 U

Transcript

HYMP125U648-E3/C4 SERIAL PRESENCE DETECT E3 Function described 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58~61 62 63 Number of SPD Bytes Written during Module Production Total Number of Bytes in SPD Device Fundmetal Memory Type Number of Row Addresses on This Assembly Number of Column Addresses on This Assembly Module Height, Package, Number of DIMM Ranks Module Data Width Reserved Voltage Interface Level of This Assembly SDRAM Cycle Time at CAS Latency =4 (tCK) SDRAM Access Time from Clock at CL=4 (tAC) DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Reserved Burst Lengths Suppoted Number of Banks on Each SDRAM Device CAS Latency DIMM Mechanical characteristics; thickness DIMM Type SDRAM Device Attributes : General SDRAM Device Attributes : General SDRAM Cycle Time at CL=4 (tCk) SDRAM Access Time from Clock at CL=4 (tAC) SDRAM Cycle Time at CL=3 (tCk) SDRAM Access Time from Clock at CL=3 (tAC) Minimum Row Precharge Time (tRP) Minimun Row Active to Row Active Delay (tRRD) Minimum RAS to CAS Delay (tRCD) Minimum Active to Precharge Time (tRAS) Module Rank Density Command and Address Signal Input Setup Time (tIS) Command and Address Signal Input Hold Time (tIH) Data Signal Input Setup Time (tDS) Date Signal Input Hold Time (tDH) Write Recovery Time (tWR) Internal Write to Read Command Delay (tWTR) Internal Read to Precharge Command Delay (tRTP) Memory Analysis Probe Characteristics Extension of Byte 41 tRC and Byte 42 tRFC Minimum Active to Active / Auto - Refresh Time ( tRC) Min Auto-Refresh to Active / Auto- Refresh Command period (tRFC) Maximum Cycle Time ( tCK max) Maximum DQS-DQ skew time (tDQSQ) Maximum Read Data Hold Skew Factor (tQHS) PLL Relock Time DRAM Tcase max/DT4R4W mode bit Thermal resistance of DRAM Package from Top(Case) to Ambient. DRAM Tcase Rise in IDD0 condtion/Mode Bits(DT0/Mode Bits) DRAM Tcase Rise in IDD2N or IDD2Q condition(DT2N/DT2Q) DRAM Tcase Rise in IDD2P condition(DT2P) DRAM Tcase Rise in IDD3N condition(DT3N) DRAM Tcase Rise in IDD3P-fast condition(DT3Pfast) DRAM Tcase Rise in IDD3P-slow condition(DT3P slow) DRAM Tcase Rise in IDD4RW condition/Mode Bit(DT4R) DRAM Tcase Rise in IDD5B condtion(DT5B) DRAM Tcase Rise in IDD7 condtion(DT7) SPD Bytes for R-DIMM SPD Revision Code Check SUM for Bytes 0-62 C4 Function support HEX Function support HEX 128 Bytes 256 Bytes DDR2 SDRAM 14 10 30.0mm/ planar/ 2rank 64 SSTL 1.8V 5.0ns 80 08 08 0E 0A 61 40 00 05 50 128 Bytes 256 Bytes DDR2 SDRAM 14 10 30.0mm/ planar/ 2rank 64 SSTL 1.8V 3.75ns 80 08 08 0E 0A 61 40 00 05 3D 50 00 02 08 00 00 0C 08 38 01 02 00 01 3D 50 50 60 3C 1E 3C 2D 01 25 37 10 22 3C 1E 1E 00 06 3C 7F 80 1E 28 00 52 64 6B 34 26 2C 39 1E 50 33 39 00 12 8F +/-0.6ns 60 +/-0.5ns No Parity/ECC 7.8us 8 Undefined - 00 02 08 00 00 0C 08 38 01 02 00 01 50 60 50 60 3C 1E 3C 28 01 35 47 15 27 3C 28 1E 00 06 37 7F 80 23 2D 00 52 64 5B 2B 20 26 30 1B 3E 33 2E 00 12 BB No Parity/ECC 7.8us 8 Undefined - 4,8 8 3,4,5 ≤ 4.10mm Regular UDIMM Undefined Supports Weak Driver 5.0ns +/-0.6ns 5.0ns +/-0.6ns 15ns 7.5ns 15ns 40ns 1GB 0.35ns 0.475ns 0.15ns 0.275ns 15ns 10ns 7.5ns N/A Extension of Byte 42 55ns 127.5ns 8.0ns 0.35ns 0.45ns No PLL 95℃/ 10℃ 50℃/W 6.6℃/ High temp. support 4.3℃ 0.48℃ 5.7℃ 2.4℃ 0.675℃ 12.4℃/ DT4W greater 25.5℃ 23℃ N/A 1.2 - 4,8 8 3,4,5 ≤ 4.10mm Regular UDIMM Undefined Supports Weak Driver 3.75ns +/-0.5ns 5.0ns +/-0.6ns 15ns 7.5ns 15ns 45ns 1GB 0.25ns 0.375ns 0.1ns 0.225ns 15ns 7.5ns 7.5ns N/A Extension of Byte 42 60ns 127.5ns 8.0ns 0.3ns 0.4ns No PLL 95℃/ 10℃ 50℃/W 8℃/ High temp. none suppo 5.2℃ 0.57℃ 6.6℃ 2.85℃ 0.75℃ 16℃/ DT4W greater 25.5℃ 28.5℃ N/A 1.2 - HYMP125U648-E3/C4 SERIAL PRESENCE DETECT E3 Function described 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87~90 91 92 93 94 95-98 99~127 128~255 Manufacturer JEDEC ID Code ----------Manufacturer JEDEC ID Code Manufacturing location(See Sheet Name "Byte#72") Manufacture part number ( Hynix Memory Module ) ~~~~Manufacture part number ( Hynix Memory Module ) ~~~~Manufacture part number ( Hynix Memory Module ) Component group (DDR2 SDRAM) ~~~Component group(DDR2 SDRAM) Manufacture part number ( Module depth ) ~~~~Manufacture part number ( Module depth ) Manufacture part number ( Module type ) Manufacture part number ( Data width ) ~~~~Manufacture part number ( Data width ) Manufacture part number ( Component configuration) Manufacture part number ( Hyphen ) Manufacture part number ( Minimum cycle time ) ~~~Manufacture part number ( Minimum cycle time ) Manufacture part number ( T.B.D) Manufacture revision Code ( for Componuent ) Manufacture revision Code ( for PCB ) Manufacturing Data ( Year ) Manufacturing Data ( Week ) Module Serial Number(Main Lot N0)-Hexa Manufacturer specific data (may be used in future) Open for customer use C4 Function support HEX Function support HEX Hynix JEDEC ID Hynix(Ichon) H Y M P 1 2 5 U 6 4 8 E 3 Blank AD 00 01 48 59 4D 50 31 32 35 55 36 34 38 2D 45 33 20 Hynix JEDEC ID Hynix(Ichon) H Y M P 1 2 5 U 6 4 8 C 4 Blank AD 00 01 48 59 4D 50 31 32 35 55 36 34 38 2D 43 34 20 Undefined Undefined 00 00 Undefined Undefined 00 00