Transcript
Memory Datasheet
DDR3 SDRAM Controller IP
Overview
Application Processor CPU 1
LCD Ctrl
CPU 2
HW Sec
Config Regs
...
Physical Layer
SoC
DDR Controller IP with DFI Interface
Transaction Processing
HW Sec
DDR SDRAM Control
The memory subsystem is a core component to any SoC development. The SDRAM interface has a fundamental impact on performance, power and cost of the system, requiring large engineering resources to properly achieve timing closure, power and performance targets – which is no small feat.
DSP
Arbitration CMD Priority
Cadence IP Factory delivers custom, synthesizable IP to support specific design requirements.
.2 .to .32 Ports
MODEM
DDR3 LPDDR3 LPDDR2 ST-MRAM
8 to 288 Data Bits
The Cadence DDR3 SDRAM Controller IP is designed to support the high-speed DDR3 SDRAM Figure 1: Example System Level Block Diagram standard, and can also support any combination of DDR3 and legacy memory systems. It incorporates advanced error correction and data protection required by enterprise, networking and high performance applications. The Cadence DDR3 SDRAM Controller IP is architected to quickly and easily integrate into any SoC, and to connect seamlessly to a Cadence, or third-party, DFI 2.1-compliant PHY. Host applications access the controller through industry standard AXI3TM, AXI4TM, AHBTM or OCP 2.0 interfaces. The Cadence DDR3 SDRAM Controller IP is silicon proven, and has been extensively validated with multiple hardware platforms. Cadence IP Factory offers a comprehensive IP solution that is in volume production, and has been successfully implemented in more than 400 applications.
Key Features • Compliant to DDR3, LPDDR3, and LPDDR2 memory
• Industry-standard DFI 2.1 interface
• Single- and multi-port host interface options
• Supports Cadence or third-party PHYs
• Flexible paging policy including autoprecharge-percommand
• Multi-stage reordering queue to optimize bandwidth and latency
• Advanced low-power modes with power-down and self-refresh
• Full or half device datapath width programmable at boot time
• RDIMM including SSTE32882 and parity, and UDIMM including SoDIMM options
• Error correction coding (ECC) allows SEC/DED over 32 or 64 bits on bus widths of 16, 32, 64, or 128 bits
• Support for Everspin DDR3 ST-MRAM
• Silicon proven and shipping in volume
• Priority-per-command on AXI3TM and OCP interfaces
• QoS features allow command prioritization on AXI4TM
Product Details
DDR Controller IP with DFI
. . . AHB AXI3
Multiport and Command Arbiter
The Cadence DDR3 SDRAM Controller IP uses multi‑stage reordering algorithms that are capable of delivering 30% performance improvement over the competition (depending on traffic). Performance-tuning parameters, driven from memory model files, allow performance optimization according to individual system and memory requirements.
OCP
Host Interface 2 to 32 Ports
DDR3 SDRAM Controller
BIST
AXI4
Autoprecharge-per-command allows setting a closed-page policy for transactions with low locality of reference and an open-page policy for transactions with a high locality of reference, which optimizes power and latency for mixed transaction types within the SoC. All Cadence DDR3 SDRAM Controller IP configurations support power-down and self-refresh. The optional advanced low power module includes automatic power level stepping (based on traffic). This level of low-power support can reduce standby power by 10x without system intervention, and active power can be reduced by up to 50%. A security option for address range protection is also available.
Host Interface
Command Queue with Two-Stage Ordering
Transaction Processing
Write Queue
Look-Ahead Optimization
Read Queue Config Registers
Priority and quality-of-service (QoS) features reduce latency on critical commands by hundreds of clock cycles, and a flexible paging policy (including autoprecharge-per-command) reduces average latency by up to 11 clock cycles.
Low Power
ECC
DFI Interface
The Cadence DDR3 SDRAM Controller IP is a low-latency, 32-bit design that has been tuned to support the highest-speed SDRAMs as well as legacy devices.
DIMM
Local Management Bus
Figure 2: IP Level Block Diagram
Priority-per-command on AXI3TM and OCP interfaces, and QoS on AXI4TM interfaces improves latency and controller QoS, especially for transactions delivered through an interconnect fabric. Flexible synchronicity allows low-latency synchronous port connection, reduced-latency pseudo-synchronous ratio port connection, or highly flexible asynchronous port connection.
DFI Interface The DFI 2.1-compliant PHY interface connects to Cadence, or third‑party, Hard and Soft PHYs.
Cadence IP Factory
Natively supports any mix of AHBTM, AXI3TM, AXI4TM, and OCP 2.0 interfaces, up to 32 buses.
Cadence IP Factory can deliver various combination of DDR SDRAM protocols to meet your design requirements. For example, DDR3, LPDDR3 and LPDDR2, or any such combination. For more information, visit www.cadence.com/ip
Benefits
Deliverables
• Low Risk solutions – Silicon proven
• Clean, readable, synthesizable Verilog RTL
• Ease of Use – Customizable with easy integration
• Synthesis and STA scripts
• Low Power – Reduced standby by 10x and active by 50%
• Documentation – Integration and User Guide, Release Notes
• Small silicon area – Up to 33% smaller with controller in the I/O ring
• Sample Verification test-bench with integrated BFM and monitors
• Hardened Solution – Improved latency and all timing is closed for subsystem
Available Products
• High Performance – Up to 30% improvement over other designs
• DDR3 Controller IP • DDR3 Subsystem – Integrated Controller, PHY, and Software Solutions • DDR3 PHY IP
Cadence Design Systems enables global electronic design innovation and plays an essential role in the creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design and verify today’s mobile, cloud, and connectivity applications. www.cadence.com © 2013 Cadence Design Systems, Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. AHB, AMBA, ARM, and AXI are trademarks and registered trademarks of ARM Ltd. All others are the properties of their respective holders. V2.0 08/13
