Dec-09-i9ab-d_dm09a_apr72

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Oigi~al Equipment Corporation ~Vlaynard, Massachusetts PDP-9 Maintenance Manual OM09A Adapter/Multiplexer DEC-09-19 AB-D OM09A ADAPTER/MUL TIPLEXER MAINTENANCE MANUAL digital equipment corporation · maynard. massachusetts 1st Pri nti ng October 1968 2 nd Pri nti ng October 1969 3rd Pri nti ng Apri I 1972 Copyright © 1968, 1969, 1972 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC FLIP CHIP DIGITAL PDP FOCAL COMPUTER LAB CONTENTS Page 1• 1 Introducti on 1 .1 Related Documentation 1 1 .2 Engineering Drawing References 2 2. 2 Specifications 2.1 Environmental 2.2 Power Requirements 2 2 2.3 Physical 2 2.4 Controls and Indicators 2 2.5 Performance 2 3. Installation 3 4. 4.1 Principles of Operation 3 4.2 Basic 3 Detailed 4 4.2.1 Power Turn-On 4 4.2.2 Internal Control Pulse Train 4.2.3 4.2.4 Single-Fast-Input Cycle 4 5 Single-Slow-Output Cycle 6 4.2.5 Double (Back to Back) - Fast-Output Cycles 7 5. Acceptance Test Procedure 11 6. 6.1 Maintenance 11 General 11 6.2 Delay Adjustments 11 6.3 Module Complement 11 7. 12 Engineering Drawings ILLUSTRATIONS 1-1 Basic DM09A System Block Diagram 3-1 Insta Ilati on Diagra m 4-1 Control Pulse Train Circuitry 3 5 4-2 Control Pulse Train Time Relationship 5 iii CONTENTS (Cant) TABLES 1-1 Reference Documents 4-1 Single-Fast-Input Cycle Signal Flow 8 4-2 4-3 Single-Slow-Output Cycle Signal Flow 9 Double (Back to Back)-Fast-Output Cycles Signal Flow 10 6-1 Module Complement 12 7-1 Engineering Drawings 12 iv 1• INTRODUCTION The DM09A Adapter/Multiplexer an option to the PDP-9 manufactured by Digital Equipment Corporation (DEC), provides an interface through which three I/O devices may gain access to the PDP-9 memory via the DMA channel. A basic system block diagram is given in Figure 1-1. Figure 1-1 Basic DM09A System Block Diagram This document and the documents referenced herein provide the information necessary for installation, operation and maintenance of the option. The leve I of discussion assumes that the user is fami liar with the basic PDP-9. 1 .1 Related Documentation The DEC documents listed in Table 1-1 contain material which supplements information in this document. Table 1-1 Reference Documents Document Number Description PDP-9 User Handbook F-95 Operation and programming information for the PDP-9. PDP-9 Maintenance Manual Volumes I and II F-97 Operation and maintenance information for the PDP-9 including basic PDP-9 engineering drawings. Basic DM09A theory of operation. DIGITAL Logic Handbook C-105 Specifications and descriptions of most FLIP CHIP modules used in the DM09A. Title 1 .2 Engineering Drawing References Engineering drawings wi II be referenced using an abbreviated code. As an example, drawing D-BS-DM09-A-2, DMA Adapter Multiplexer Control, sheet 1 of 2, will be referenced as [DM-2(2)] • 2. SPECIFICATIONS 2. 1 Environmental The DM09A consists entirely of modules of the type used in the PDP-9 central processor. Therefore, PDP-9 environmenta I specifications apply to the DM09A. 2.2 Power Requirements The option obtains a II necessary operating power from the PDP-9 power supply system. No additional power supplies, power control or fan assemblies are necessary. 2.3 Physical The DM09A consists entirely of modules which are housed by two DEC standard 1943 mount- ing panels, thus requiring 10-1/2 in. of mounting space. Placement of these panels is given in Section 3, IN ST ALLATION • 2.4 Controls and Indicators No controls or indicators are associated with the DM09A. The option is entirely under the control of the PDP-9 and the I/O devices. 2.5 Performance The multiplexer operates at two speeds. I/O devices with 10 mHz ·Iogic may request the high speed and thus achieve a 1 .,.s/transfer rate; I/O devices with low speed logic should request the low speed of 3 ~/transfer to permit sufficient data-line settling time. It should be remembered that the speed range applies only to the DM09A. The PDP-9 DMA channel and the memory require only 1 .,.s/transfer. 2 3. INSTALLATION Implementation of the option involves insta II ing the option modules into their preassigned, prewired locations in the basic PDP-9 cabinet. The location in which the option mounts is shown in Figure 3-1 • RESERVED FOR DM09A RESERVED FOR ME09B PAPER TAPE READER AND PUNCH OPERATOR'S CONSOLE TABLE Figure 3-1 Insta Ilation Diagram The following engineering drawings provide all necessary interface information. Draw i ng Number Title D-CD-DM09-A-9 (Rev. A) Memory Interface Interface between the DM09A and the basic PDP-9 memory. CD-D-DM09-A-10 Interface Cabling DM09 Memory Interface between the DM09A, ME09A memory extension control and MM09A extended memory bank. CD-D-DM09-A-11 Cabling DMA Inter-Memory Interface between the MC70B basic PDP-9 memory and MM09A, Band C extended memory banks. 4. PRINCIPLES OF OPERATION 4.1 Basic Description A basic description of DM09A logic operation can be obtained from Section 3.8.3, DMA Channel Transfers, of the PDP-9 Maintenance Manual, Volume 1. A detailed DM09A block diagram is also contain in that section. This document describes in detai I the operation of the DM09A DMA Adapter/Multiplexer. 3 4.2 Detailed A variety of transfer type combinations are possible with the DM09A. To avoid excessive repetition, only three types will be described herein; Single-Fast-Input cycle, Single-Slow-Output cycle and Double (Back to Back)-Fast-Output cycles. Certain DM09A operations are executed regardless of transfer type; namely, control circuitry initialization via power turn-on and interna I DM09A control pulse train generation. Transfer type descriptions assume I/O device 0 is being acted upon. All reference will be made to I/O device O. Similar operations wi II result when any other device is acted upon. All transfer types can be thought of as consisting of a number of "time states" each commencing with a PDP-9 ClK pulse. Single transfers consist of time states in which either an I/O device is made ready, in which a device is synchronized to the PDP-9, or in which a data transfer takes place. With multiple transfers, synchronization is established during the previous data transfer. When reading the logic descriptions, the user should refer to the engineering drawings referenced on the signal flow tables. In addition, DM09A timing diagrams, drawings DM-8(1) and DM-8(2) should be referenced for specific timing information. 4.2. 1 Power Turn- On When the system is first turned on, PK ClR (power and key clear) pulses arrive at the DM09A control logic and produce PWR ClR POS (power clear positive) pulses to condition the control logic. The operations performed are as follows: Clear SYNC 0 Clear SET AO Clear SET DO C lear DEY 0 CONT Clear SLOW CYCLE A 4.2.2 Interna I Contro I Pu Ise Tra i n Following PK ClR, ClK (clock) pulses arrive at the DM09A control logic and are used to generate an interna I DM09A control pulse train via the circuitry of Figure 4-1. Time re lationships are illustrated in Figure 4-2. The pulse train is generated whenever the system is ope rat i ng • 4 D ClK D H -----+-----eI u t5en Figure 4-1 ClK A PHASE U I ~oon.jl I lOAD AMEMA ~ I I D PHASE 650n. r 7OOn. Control Pulse Train Circuitry U n n n n n Figure 4-2 Control Pulse Train Time Relationship 4.2.3 Single-Fast-Input Cycle The DM09A adapter/multiplexer is uti lized during the memory read/write cycle. During this time the I/O device break request flag is set providing the DM09A with a CH 0 SK RQ level. Referring to Table 4-1 and the referenced engineering drawings, internal control logic operations serve to generate an AM RQ level. This level is applied to the PDP-9 memory control circuitry shown on drawing D-SS-MC7Q-S-1 (sheet· 2). A ClK pulse marking the beginning of the SYNCING time state is then produced. During SYNCING, the central processor has access to core memory. ClK, delayed 100 ns, generates SYNC ClK to set the AM SYNC flip-flop in memory control via AM RQ(l). AM 5 SYNC(l) produces AM SYNC(1)B and AM SYNC BUS(l). AM SYNC(l)B is utilized by CM (control memory) timing to prevent SM(1) from restarting the CM on the next ClK pulse which marks the beginning of the DATA XFER time state. The DATAXFER time state is entered via another PDP-9 CLK pulse. ClK, delayed 50 ns, is POST ClK and resets the MODE flip-flop conditioned by AM SYNC(l). MODE(O) signifies AM access to memory while MODE(l) signifies CP access to memory. PRE-WRITE OFF of the previous core memory cycle (SYNCING) sets the MEM DONE flip-flop and produces AM GRANT. If on EAE or an lOT instruction immediately precedes the DM09A request, AM GRANT is not produced. In this case AM SYNC(l)B is delayed to generate AM GRANT SMlTD (simulated). During the current time state, I/O device 0 address bits are present at the input gating circuitry of the AM REGISTER (refer to drawing DM-3(2». Address bits utilized by a PDP-9 with basic memory are designated CH 0 ADDR BIT 05 through CH 0 ADDR BIT 17. The bits are applied to the inverter modules shown. ADDR 0, the result of DEV 0 CONT(O) and SET 00(1), allows the address bits access to the jam input gates of the AM REGISTER as LAM 05 through LAM 17. An AMI (adapter multiplexer input) pulse jam transfers the 13-bit address into the register. AMI is the result of AM GRANT* or AM GRAND SMlTD. The flip-flops designated AMEMA 03 and AMEMA 04 are used with PDP-9 systems containing extended memory banks. Inverter inputs are CH 0 ADDR BIT 03 and SET AO(l) for AMEMA 03 and CH 0 ADDR BIT 04 and SET AO(l) for AMEMA 04. lOAD AMEMA jam transfers the extended memory addressing bits into their respective flip-flops. This pulse is produced 650 ns after CLK by the control pulse train circuitry described in Section 4.2.2. Following memory addressing, an la-bit data word is jam transferred into the AM REGISTER. I/O device 0 data word consists of CH 0 DATA BIT 00 through CH 0 DATA BIT 17. The data word is also applied to a network of inverter modules. The enabling signal is DEV O. The data word is jam transferred into the AM REGISTER by a second AMI pulse which is produced by AM STROBE. 4.2.4 Single-Slow-Out·put Cycle Table 4-2 illustrates the signal flow associated with a Single-Slow-Output cycle. The I/O device is programmed to indicate that an output transfer is to take place, the number of words to be transferred and the address of the first word, DM09A control logic operations which result from this type of data transfer are basically simi lar to those of the Single-Fast-Input cycle. The I/O device requests multiplexer service via CH 0 BK RQ. The control logic proceeds to generate AM RQ and AM RQ NEG. SYNC 0(1) and CH 0 FAST RQ condition the set DCD gate of the SLOW CYCLE A *Both may be present but the circuit is a logical OR. 6 flip-flop which is set by the positive going transition of AM RQ NEG. Following logic operations in the multiplexer and in the PDP-9, an AM GRANT pulse is issued to produce AMI. With input transfers, this pulse jam transfers the device supplied address into the AM register. This is not necessary with the current type of transfer. Following further DM09A control logic operations, simi lar to those of Single-Fast-Input cycle, PDP-9 AM STROBE arrives at the DM09A. This pulse is gated with CH 0 RQ IN and SET 00(1) to produce SAl (sense amplifier input) thus allowing PDP-9 sense amplifier bits SA 00 through SA 17 access to the jam input gates of the AM register. A second AMI pulse is produced at this time to jam transfer these bits into the AM register. 4.2.5 Double (Back to Back)-Fast-Output Cycles Signa I flow for the current transfer type is given in Tab Ie 4-3. Initia I signa Is sent to the DM09A control logic are CH 0 BK RQ, CH 0 FAST RQ and CH 0 RQ IN. CH 0 BK RQ signals the DM09A that service is requested. This signal and internal SLOW CYCLE A(O) produce SYNC 0 EN to condition the set DCD gate of the SYNC 0 flip-flop. The 0 PHASE pulse preceding the SYNCING 1 time state sets SYNC 0 to establish device priority. This conditions the CH 0 FAST CLR and sets the DCD gate to produce AM RQ and AM RQ NEG. AM RQ signals the PDP-9 that a DMA cycle is desired; the computer responds with AM SYNC(l) B. The A PHASE pulse of SYNCING 1 sets SET AO and generates CLR SYNC. This clears SYNC O. SET AO(l) and AM SYNC(l)B generate SET DO EN which conditions the set DCD gate of the SET DO fl ip-flop. The following D PHASE pulse sets SET DO. SET AO(l) and SET DO(l) produce CLR SLW CYC EN which with A PHASE, maintains SLOW CYCLE A (0) , a characteristic of fast transfers. SYNC 0 is set again because SLOW CYCLE A(O) and CH 0 BK RQ are sti II present. Setting SYNC 0 generates another AM RQ signal. Because this signal is applied to the PDP-9 AM SYNC flip-flop prior to SYNC CLK, the flip-flop remains set. The PDP-9 produced AM GRANT arrives at the multiplexer control circuitry as the DATA XFER 1 and SYNCING 2 time states are entered. The pulse jam-transfers address information into the AM REGISTER. During these time states the data transfer associated with the preceding syncing operations, and syncing operations for the next data transfer take place. AM STROBE arrives from the PDP-9 and generates SAl and AMI, thus allowing the sense amplifier bits, SA 00 through SA 17, access through the AM register gating circuitry and into the AM reg ister • DATA XFER 2 is entered. SET AO is cleared and operations similar to DATA XFER 1 take place to jam transfer the data bits of the second word into the AM register. The 0 PHASE pulse at the end of the current time state clears SET DO. 7 Table 4-1 Single-Fast-Input Cycle Signal Flow Time State Control Pulse D PHASE SYNCING A PHASE D PHASE DATA XFER A PHASE D PHASe Signal SYNC 0 EN SYNC 0(1) AMRQ AM SYNC(l)B SET AO(l) CLR SYNC SET DO EN CH 0 FAST CLR SYNC 0(0) SET DO(l) CLR SLW CYC EN AM GRANT CH OADDRACC IN DEY 0 CONT(l) DEVICE 0 SET AO (0) CH o ADDRACC SLOW CYCLE A(O) AM STROBE CH 0 DATA RDY IN INH 0 DAP(O) CH 0 DATA RDY CH 0 DATAACC seT 00(0) Conditions Drawing Number CH 0 BK RQ * SLOW CYCLE A(O) D PHASE * SYNC 0 EN SYNC 0(1) From PDP-9 A PHASE * SYNC 0(1) A PHASE * AM SYNC(l)B(B) AM SYNC(l)B * SET AO (1) CLR SYNC * SYNC 0 (1) SYNC 0(1) * CLR SYNC D PHASE * SeT DO EN SET AO(O) * SET DO(l) From PDP-9 A PHASE * SET AO(l) * SeT DO(l) DM-2(2) DM-2(l) DM-2(2) MC-l(2) DM-2(1) DM-2(2) DM-2(2) DM-2(1) DM-2(1) DM-2(1) DM-2(1) MC-l(2) DM-2(1) CH 0 ADDR ACC IN * SET DO(l) DEV 0 CONT(l) * seT DO(l) * CH 0 RQ IN A PHASE * SYNC 0(0) * SET DO(l) CH 0 ADDR ACC IN A PHASE * CLR SLW CYC EN From PDP-9 D PHASE * SET DO(l) * SLOW CYCLE D(O) DM-2(1) DM-2(2) DM-2(1) DM-2(1) DM-2(1) MC-2 DM-2(2) CH 0 DATA RDY IN CH 0 DATA RDY IN D PHASE *CH ORQ IN * INH 0 DAP(O)~ S~T qO{l) D PHASE * SET AO(O) * SLOW CYCLE 0(0) DM-2(2) DM-2(2) DM-2(1) DM-2(l) Table 4-2 Single-Slow-Output Cycle Signal Flow Time State Control Pulse SYNC D PHASE SYNCING A PHASE D PHASE DATA XFER A PHASE Signal Conditions CH 0 BK RQ * SLOW CYCLE A(O) D PHASE * SYNC 0 EN SYNC 0(1) SYNC 0(1) * CH 0 FAST RQ * AM RQ NEG ... 0 From PDP-9 A PHASE * SYNC 0(1) A PHASE * AM SYNC(l)B(B) AM SYNC(l)B * SET AO(l) CLR SYNC * SYNC 0 (1) CLR SYNC * SYNC 0(1) D PHASE * SET DO EN From PDP-9 A PHASE * SET AO(1) * SET 00(1) SYNC 0 EN SYNC 0(1) AMRQ SLOW CYCLE A(l) AM SYNC(l)B SET AO(l) CLR SYNC SET DO EN CH 0 FAST CLR SYNC 0(0) SET DO (1) AM GRANT CH 0 ADDR ACC IN DEY 0 CONT(1) SET AO(O) CH 0 ADDR ACC CLR SLW CYC EN SLOW CYCLE A(O) AM STROBE AMI SAl CH 0 ADDR ACC IN * SET DO(1) A PHASE * SYNC 0(0) * SET DO(l) CH 0 ADDR ACC IN SET AO(O) * SET D(1) A PHASE * CLR SLW CYC EN From PDP-9 AM STROBE + AM GRANT AM STROBE * CH 0 RQ IN * SET DO(l) SET DO(O) D PHASE * SET AO(O) * SLOW CYCLE D(O) Drawing Number DM-2(2) DM-2(1) DM-2(2) DM-2(1) MC-l(2) DM-2(l) DM-2(2) DM-2(2) DM-2(1) DM-2(1) DM-2(l) MC-l(2) DM-2(1) DM-2(l) DM-2(1) DM-2(1) DM-2(1) ' DM-2(1) MC-2 DM-2(2) DM-2(2) D PHASE DM-2(1) Table 4-3 Double (Back to Back)-Fast-Output Cycles Signal Flow Time State Control Pulse o PHASE SYNCING 1 A PHASE o PHASE ..... o DATA XFER 1 SYNCING 2 A PHASE o PHASE DATA XFER 2 A PHASE o PHASE Signal Conditions Drawing Number SYNC 0 EN SYNC 0(1) AM RQ AM SYNC(l)B CLR SYNC CH 0 FAST CLR SET AO(1) SET DO EN SYNC 0(0) SET 00(1) SYNC 0(1) AMRQ AM GRANT CH 0 AODR ACC IN CH 0 ADDR ACC OEV 0 CaNT (1) AM STROBE SAl SYNC 0(0) CH 0 FAST CLR CH 0 DATA ROY IN CH 0 DATA ROY AM GRANT CLR SLW CYC EN SLOW CYC LE A (0) CH 0 AOOR ACC IN CH 0 AODR ACC AM STROBE SAl SET 00(0) CH 0 BK RQ * SLOW CYCLE A(O) o PHASE * SYNC 0 EN SYNC 0(1) From POP-9 A PHASE * AM SYNC(l)B(B) CLR SYNC * SYNC 0(1) A PHASE * SYNC 0(1) SET AO(l) * AM SYNC(l)B CLR SYNC * SYNC 0(1) o PHASE * SET DO EN o PHASE * SYNC 0 EN SYNC 0(1) From POP-9 A PHASE * SET AO(l) * SET 00(1) OM-2(2) OM-2(1) OM-2(2) MC-1(2) OM-2(2) OM-2(l) OM-2(1) OM-2(2) DM-2(l) OM-2(l) OM-2(1) OM-2(2) MC-2(1) . , CH 0 ADDR ACC IN SET 00(1) * CH 0 ADDR ACC IN From PDP-9 CH 0 RQ IN * SET 00(1) * AM STROBE CLR SYNC * SYNC 0(1) CLR SYNC * SYNC 0(1) o PHASE * SET 00(1) * SLOW CYCLE 0(0) CH 0 DATA ROY IN From PDP-9 SET AO(O) * SET OO( 1) A PHASE * CLR SLW CYC EN A PHASE * SET AO(l) * SET 00(1) CH 0 AOOR ACC IN From POP-9 CH 0 RQ IN * SET 00(1) * AM STROB'E o PHASE * SET AO(O) * SLOW CYCLE 0(0) DM-2(l) DM02(l) DM-2(l) MC-2 DM-2(2) DM-2(1) OM02(1) DM-2(2) DM-2(2) MC-2(1) DM-2(1) MC-2(1) OM-2(1) OM-2(1) MC-2 OM-2(2) .OM-2(1) 5. ACCEPTANCE TEST PROCEDURE Acceptance testing of the DM09A option consists of executing Test Procedure DM09A-O with the DM09A Tester at both normal operating conditions and the voltage margins specified below. Aggravation Condition Trial Test 1 DM09A-O None 2 DM09A-O Margin rack A 3 DM09A-O Margin rack B Minimum margin specifications for rack A and rack B are listed below. Margin -15V +10V +6V 6. MAINTE NANCE 6.1 General I +4V 1-4V -6V The general maintenance procedures described in the PDP-9 mainteoonce manual also apply to the DM09A option. 6.2 Delay Adjustments Adjust the R302 Delay at A27 according to the data given on engineering drawing DM-2(2). 603 Module Complement Table 6-1 lists the module complement of the DM09A option. 11 Table 6-1 Module Complement DEC Type Module Type Quantity Recommended Spare Quantity 8169 Inverter 17 2* 8213 Jam Flip-Flop 14 1* R002 Diode Cluster 2 1* R111 Diode Gate 12 1* S107 Inverter 2 1* S202 Dual Flip-Flop 7 1* S203 Triple Flip-Flop 1 1* 5603 Pulse Amplifier 5 Woo5 Clamped Loads 3 1* W300 Delay Line 1 1 W612 Pulse Amplifier 8 R302 One-Shot Delay 1 1* *Contained in the basic processor spare parts kit. 7. ENGINEERING DRAWINGS Table 7-1 lists the DEC engineering drawings associated with the DM09A option. Table 7-1 Engineering Drawings Drawing Number Title Revision DM-2(1) DMA Adapter Multiplexer Control BS-DM09-A-2 Sheet 1 of 2 J DM-2(2) DMA Adapter Multiplexer Control BS-DM09-A-2 Sheet 2 of 2 J DM-3(1) AM Register BS- DM09-A-3 Sheet 1 of 2 B DM-3(2) AM Register BS-DM09-A-3 Sheet 2 of 2 B DM-4(1) Cable Diagram BS-DM09-A-4 Sheet 1 of 2 0 DM-4(2) Cab Ie Diagram BS- DM09-A-4 Sheet 2 of 2 A DM-5 Module Uti lization MU-DM09-A-5 H DM-8(1) DM09A Timing Diagram TD-DM09-A-8 Sheet 1 of 2 a DM-8(2) DM09A Timing Diagram TD-DM09-A-8 Sheet 2 of 2 0 12 7 8 CH 0 6 ADDR Ace ~N .4 5 CH I AOOR ACC XN 2 3 CH 2 "'OOR Ac.e IN D CH ¢ AClOR ACC CH I ADOR ACC CH 2. AODR ACC SeT A2(1) SET D 10). L CH (/J O"TA ACC CH 0 RQIJN-~-=-t~ SET 02(1) N' 1\ I we(i1S CI9 A PH,AS£ K SLOW'· CYCLE 0(1) .AI ACC c CH 2. DATI>. ACe PWR' CLf{ C.H Z RQ IJi'---.-:v----'-"'I 011 Rq IN :It PIfASF --t>I5~-«52'1 Wal05 vrfJr,Js el9 CI9 c POS-~::r'""-...:..O.,..... 11 PHIISE flMRQ-'IEG. SLOW CYCLE 0(1) SLOW CYCLE 0(1) CLR A PHASE CH '2. F .....ST C.LR o;:;,ET 0 (6(1) B CH 2. PWR CLR B PO~ ~~UL~~-L----~~~~~~----~~fU~~~----~~~~~~-------~~~~~~~______~~~~~~ D PHASE CL R '5YN C .:::..{;tg;J----+----------....:.N~Zl---_+_---------'::O"018J ~------_+-------_+--OCLR :SET 0 Z.(I") SYNC 1])(1) :SYNC. 1(1) :SYNC eel) CH ¢ DATA ROY Ij,j CH If> CH I DATA RD,{ IN AOOR. ACe. IN CH 2 Oo'o.TA RDY IN CH I "OOR Ace. IN SL VI' eye EN SETIl~(I) SET D '1(1) CH Z ADDR ACC IN A A 8 7 6 5 3 2 BS-DM09-A-2 Sheet 1 of 2 DMA Adapter Multiplexer Control 13 6 7 8 5 SET D 2 E.N AM RQ. NEG. ~---'--':'-=-.IrN7\l--.AM SYNC(I)S(e.) D 2 3 P SYNC ¢ D K (I) SYNC. I (I) DEVICE ~ SYNC. e \;:N SYNC e(l) ¢ CH CH F D ~ RQIN U 6K RQ DEV 'Ii CONTROL(t) SE.T D¢(I) RDY CH ~ DATil RDY IN F AMI H c DEVI(.\;' CH I RQ IN • DEV c \ K 1 CONTROL(I) SET I (I) o .11M G.RIjNT SMLTD SAl. WI!J¢5 1'.2.3 A K I.. 011 D .IIMEMII D L CH a RQ IN U 1\ V p I'lM B DEV a CONTROL(I; SE.T D 2.(1) CHa1RQTI'l SYNC(I)B---£~~ v U I1DJUST AM GR/Jf(T SMLTO TO occuR AT AM GRIII"r TIME. H B PWR ("LA. p05 SYNC Z (¢) '" PHASE (6) A f>HjI,.SE snlC A 8 7 6 PK CLR ISqI./I.. 2. (91) A 5 3 2 BS-DM09-A-2 Sheet 2 of 2 DMA Adapter Multiplexer Control 15 8 7 6 2 3 5 o D' SAO" SAl 01 a DATA-BIT()0' DEY fI CH I ~TA-BIT0'0' DEVI c CH 2DATA-BlT~ c C M C =NOTE: loon, tw, C -= -=- -= -=- C C =- -=- -=- 10". TERM I NATORS TO GROUND MUST BE PUT ON SA!Il0 THRU SA 17. N P N loon 8 SA 12 SAl 01 0 DATA-BIT 12 DEv0 CH I {)I.TA-BIT 12 8 DEVI CH 2 DATA-BIT 12 C M -=- hi C -=- A. A. 8 7 6 5 3 2 BS-OM09-A-3 Sheet 1 of 2 AM Register 17 0 E E P 0 N .4 5 6 7 8 2 3 P fM D i-C~J D AYE",A LAM CH0ADDR BIT 05 CH (\ ADOF\ 81T03- SET A0111 CH I ADDR BIT 03 CHIADDR BIT 05 CH I AODR S BIT 04 SET AI II) CH 2 ADDP. 81T03 CH 2ADOR BIT IIj LAM (67 CH 0AODR BIT 06 S CH2AOOR V BIT 05 04 £15 CH '" ADDP BIHJ7 IIj LAM~9 LAM 08 CH0ADDR BIT 08 CHI2lADDR BIT 09 CHi2IADDP BIT II CH 0ADDR BIT IfIJ CHIADDR BIT 06 CHIADDR BIT 1217 CHIADDR BIT 08 CHIAOOR BIT 09 CH 2 ADDR BIT 06 CH 2 AODR BIT 07 81T 1iJ8 CH 2 ADDR V BIT 09 LAM 13 LAM 12 LAM II S BIT II C H 2 ADD ~ V BIT II CH 2ADDR BIT 10 CH I ADDR BI T 12 CH I ",uDR S 81 T 13 81 T 12 C H 2 A DOR V BIT 13 DDI\ SET A2 III M M C -=- ':' M -= M C M C C -= -= -=- C M -= c C W!1l05 'A23 LAM 14 ADDR iJ CH I J.OORBIT 14 C'" IAODR BIT 15 ADDR LAMI7 ADDR fJ ADDR I ADDR 2 S DEV I CH2 ADDR V BIT 15 CH2 ADDRBIT 14 B LAM 16 (H0 ADDR BI T ,5 :H0ADDR BI T ADDR LAM 1'5 H CH2ADDR V BI T 17 L 2 M C C M SET 0 0( I )-,--T.-."" - " SET 0 2 (I) ,H-,-~--,.,------,K B A A 8 7 6 5 3 2 BS-DM09-A-3 Sheet 2 of 2 19 AM Register 8 7 6 4 5 o * G795 W(/J33 AIS A(/JI 3 2 W(il33 A02 CLK SA 1/J0 BK RO AM SYNC(I)8 02 II RO IN AM RO 03 12 SA o 09 f/JI CH ¢ I j CH 0 ~~~: :~~ AM GRANT 04 13 PK CLR 1/J5 14 DATA ROY AMEMA 03(01--.1.,----1.. 06 15 FAST RO AM STROBE (/;7 16 08 SA 17 V AMEMA 04 (0} ........" __+-_t-e FAST CLR * W031 W¢31 D08 c 013 USED FOR TERMINATION ONLY NOT A CABLE.(OPTIONAL) CH CH I BK RO A03 AM f/J0 (I) AM (/J(/J (I) RO IN 01 01 FAST RO 1/J2 02 03 03 0 ¢ CH I BK RQ RO IN W¢31 DI/J2 rJj' W!2l31 *" CH rtJ 8K RQ CH SA CH I RO IN CH I FAST RO 06 07 AM 08 (IJ K K K M M --"T AM (jI8 (I) AM 09 T ~V V Iv '-" (CH I) (CH 2) (CH 2) W¢31 0~J7 W031 NOTE: PINS C,F, J,L,N,R,U ARE GNO FOR ALL w031's AND WI/J33'S II RO IN 12 12 ADOR ACC 13 13 DATA ACC 14 14 15 15 RO B 16 16 AM 17 IJ) AM 17 (Il CH 2 FAST CLR t DII I~ CH 2 BK RO FAST (CH r) AM ¢9 (Il (I) Ic;l P S T '-" B P S --.. t::Hc;J) Wf/J31 DI2 c M -P f/J6 CH 2 FAST RQ E H ~S 07 CH I FAST E !/J4 CH 2 BK RO (!5' 010 H 05 CH 2 FlO IN (0' H 04 DATA WI/l31 E 05 FAST RO W031 006 A A 8 7 6 5 4 3 2 BS-DM09-A-4 Sheet 1 of 2 21 Cable Diagram 6 7 8 4 5 2 3 D D iW~¢Io-·' I c'"' \" , C'f-Tf- a,T ¢¢ I ClIO W031 I I DI --:----~ ~ o I) CH ¢ ~ - - , - - -......, . q)'2. . lC{N CIjZI~ ~ cf> I rw~¢~-;tl W{!I31 : CQlI I r-.1)t:>R SI\" QJ9 cb~ ..........;---....:...;...~­ -;-----=~ • I-! 12- 1'2.. ¢~ I~ \~ RI M - - - . - - -.... 1 .. • ¢a,- T 0 1<0 --;--.,:.:-.1 • DA,"" S\, 11 ---'-I--~I"· V L _ _ _ .....l CI-I(/) "-OOR SrT 07 \<0 ¢s CH (/> M)DR. SIT \"7 I/J\ t (M. . 'P ,: ~ IJI \ --;--~I,. T CI4 <:bch PI \<, --;--~I~· I'::> I V ¢B -7--.........,,.... 1 51\ -'--+--''"""'1eI ~I ¢.-, ---:-I---~· Di'.T~ --:--+-'-.... 1 eI • P --;----I~· \/1 V -+---~. rw¢¢i5il : CI.DDR BIt FI ":: I--'A-?: ~! -:---~.' iwa'>c:t>:. W~31 D .... -'----....· .... --:----..... .... -'----. .........,...---. CI-l \ 01>.,,,", '0\\ ~'e, (It..: ':;."/;'<> I~/lr-pl CH 1 D"-,,,, an' t:p9 EI E -;---~I" • ¢'O 1wcbct>=- ~ L~~ __ J c CH I ,t..ODR EIT NI CH I I ell M ¢5 ~--"----;-<" ¢/& ~ CH (/J DI>.TA BIT E \I II K ¢a,- Ml : CHZ Dt>..\"A. BIT I I I rvj~¢5"""il W¢31 c.¢"?J DI o - ,,-I '6. -";'--~I'-44 • 1""1 1-1 --,---_1'-44 1-11 K -..;.----I~ • J, M \'(1 p CH2. D"""''''' BIT o;zl'?J ¢-e, -..;._ _..N...;.;I'-44 ~ L ___ J D Rl E E 1-1 1-\ ...........:.--~-41. \'2. -;.-- \'4 --,---+-'-"" • 0 --i----~. \3 <$'1 . 5: ....T:ul,.-K --;----1-41 · vI F' LI ~ I Iq, 12- ... - Iq. IS T --;----,....V I D . • EO -;----,.... \~ .........,...--_.- 1 <:"IZ- H • CH 2. t--DDR B\\" ¢~ I M! 1\ ·M -;---~I·101 P -;---"I~ 1-\1 '5 -;----~I I Ws ¢xe. I fW"0-~5~ I CI'::. W(ll31 W031 I CI~ II ¢4 - " ; ' - - FI:-4oI- Li '5 ...........:._--,.... I I CIS I c \(0 CH Z. I>..t>OR e l l \ I PI K R: M si p ---:---FI~· ~ __..T-,-,I,.; .........;.--..ul --.---,,.... T v-:,...~ L ___~ iWci>¢5 : LC~:""'_J B ·OPTIONAL CLAMPED LOADS. A A 8 7 6 5 4 3 2 BS-DM09-A-4 Sheet 2 of 2 23 Cable Diagram 8 11833 7 2 3 4 1833 U33 W~33 5 'lYJL33 7 6 ~213 6 8 Jl1ll Jl213 9 8213 10 8213 5 II 12 13 14 8213 B213 B213 &213 15 s~n" 16 17 18 19 20 1.12 HII: Kill _~'7 ~2~ ClM 2QL m A2111 All D All III 11. SA SA AM 8-2 9-17 (,21-8 .2 ,,. All CONT. All All " All All 18 ,1.8 AM 12 All AlII 16 MEM. AM All ,81 .3 AM AM '7 '5 All AM All AM A1811 AIIH ""' 18S _ r-- All SJI as 11 13 15 r-- 17 r-- 8169 ~169 --"-169 LAM LAM iAMEMA 118 112 (63 8189 ---'-'- RQ SYNC 8169 8189 9169 9169 9169 9169 9169 B189 9189 B 69 8119 9189 LAM LAII LAM LAM LAM LAII LAII LAII LAII LAII LAM LAM LAM ,84 liS 8S 18 18 II III 12 12 14 14 16 18 22 F- 24 !i12 ~ AZ8i I BZ8T B19J - iPHASi (B) l¥l8213 8213 8213 ADDR lDOR DEVICE 2 1 l18li2 B c LAII 111 J~4 J 13 2 W0.31 3 W031 W~31 85 B7JI't 913 B28v LAII LAM LAII LAII LAM LAII LAII LAII LAM LAM LAM LAM 85 17 .07 ,89 19 11 11 1.3 13 15 15 17 17 ADOR I-- ~i7ii_ 5 jWl2l3 7 6 'K0M U't£l~J 8 W~ 9 10 31 IW031 W031 II 12 W031 IW0.31 13 14 15 l1li5" l1li5 • 1 _ - 16 17 l1li5" _5" 18 19 l1li5" _5 ~ CH CHB CH I 2 --"'I2.l ClIBS f---- I c DATA BI T 8-8 ADDR BI T 3-8 DA.TA BIT 9-17 ADDR BI T 9-17 DATA BIT 11-8 I DATA BI T 9-17 ADDR BI T 3-8 AD DR BIT 9-17 DATA BIT '-8 DATA BIT 9-11 ADDR BIT 3-8 ADDn BIT 9-17 CH '. AODR BITS 83-11 CH 1 AOOR BITS 83-11 CH 2 AODR BITS 83-11 CH, CH 1 DATA DnA BITS BITS 18-14 ,88-14 CH 2 DATA BITS ,88-14 B W~31 CH 4-- D SPARE W£l31 W031 WIZ'31 1831 We:J31 W031 CH CH 1 All 1-8 9-17 (NEG) 1831 I AM (NEG) CONTRO SIGNAL I 1 can ~ r- DEVICE ~EYICE 2 AM SPARE ,8-8 (NEG) CONTRO All 9-17 SIGNAL (NEG) All SPARE lI-a (NEG) 2 1831 W612 G7115 -- eH AM ONTIIOL' ',1,2 9-'17 IGNALS LEYEl TERM (NEG) CH ," ADDR ACC W612 CH 2 AODR ACC '612 CH 1 AODR ROY WU2 CH. FUT CLR 20 21 ~ r-- 22 Ol8F LI.' B27D 92711 B27R 0240 04 1612 CH 2 DAn CLR CH 1 DATA ACC DleR SPARE RIll CH $I ADDR ACC IN I CH I AOOR ACC eH '. DATA RDY CH 2 DATA RDY CH I FAST CLR CH·ICH2 DATA DATA ACC ACC I I SLOW H!'- CYCLE A 0 PHASE IG~'4 0 ~ 37 ~ r-92. 25 OEV ,! t-- - CONTROl SLW 24 26 27 28 --.S2.I.L l..S2I.2. -.S2U ~?.II? ~?.II7 t-~TD , EN SET SET SET SYNC o ,8 o2 A 1 , SYNC 29 SET SET oI A, A 2. Rill S6!iJ~ S203 f\DY IN CH 2 CH 2 ADDP. DI71!... DATA P.DY IN SYNC 1 30 31 R 32 33 34 '" ID rJ<25E_ C2BP C25P C27E _ 2 0 ~V~'ir I-SET 1 (,n CH I DI1F _ DATA V CYC EN SEl V Clf\ 35 39 40 41 42 43 44 '" '" INH 0 DAP J. OAP t-°f~ &. 2 V OAP / 37 ~ C27P INH D20P. 36 ~ INH t-Df~ L D2rdF ~L V V V V / D 38 ""~ 39 40 '"'" 41 42 '"'" 43 c 44 L DEY 2 ONTROl fJ261.. V V CYC EN r---DEY I ~ V EN -Rll S-6.1II" 38 ./ CONTROl r - ClR SLW - t- R Clf\ SlW CYC 23 CH¢ OISR_ DATA t-D~~B.. 019P. f\OY IN IN - SLOWrYCLE CH 0' ACe. r- r---- r Rill AOOP. ACC IN S7JI': ~ S6.0i CH 1 AOOR AODP. ACC ACC IN IN CH 2 ADDR ACC IN ~ ~ SYNC r- 2 Ell ~E~D_ CH I SPARE r-- ~ll I EN DI~F 024H 024L 1112 36 ~ 1::>110 ( fi!o ~YNC C2.311 casT C23N CBSV C2.3U Cl'S SYNC B C1.IT ISYNC E 35 '"~ ~ A A I'tlASE B21L fllMEMA j'lMEMA 1_5 15603 .C23f C23L 33 34 AM GRNT SMlT[ ISMlT E r--- RQif; B21V 4 'K~31 LAII 32 P r - - ~MEMA r---- r-- I IAMEMAj LAII LAII 30 31 Al50 8zl~ r---AllL 29 1 824P ISNN 919Y , 28 G~~T r-r-- ~~~)1. 27 2 ~ 1::>61Z'~ r---- ~AlIK r-- 26 S r-- - 2 25 -.!W. :A PHAS '--- A17L R I 23 ~5 I!:'~ r---_'2IfI_ SPARE r--- (I) r-- B19L B169 All f - - r-A1BR~ AleF I 21 _1!J11 A23F rsYMC fMi~ r-- ONTROL FROM E/IORY LEVEL TERM. FRO!,! 9-17 - All 14 3 V V V '" ~./,/ V / I '" V V V ~'"I"'~ V V B ~ ~ • OPTIONAL MOOUlES. NOTE: FOR IIODULE COIIIT SEE A-PL-DI&89-A-5 A A 8 7 6 5 4 3 2 MU-DM09-A-5 Module Utilization 25 8 6 7 ~ D COMPUTER BASIC. C.YC.LE SINGLE'FA5T'INPUT CYCLE SYN IN .4 5 f1 I SINGLE. SLOW, OUTPUT CYCLE: SYNCiNG au 3 2 0 D A PHASE PULSES (i20 NS) (INTERNAL DM09A) D PJ-1ASE PULSES (I20NS) (INTERNAL DM0911) \ C.HX 81'1 R~ (F"ROM DEV X TO DIVl09A) Dl'r') 0 9fi TO ~~J------------------~~-_-_~-L ~ ~OW CYCLE (D). 01)( SK RQ (-3)'D PHASE AM 5 ,(NC ~ __~__-3___~-L~_~-~-'--------------------~~-_-_-'~________~/~~/~----------------U (I) B·1l PHASE c SYNCX-I~,--_ _S_Y_N_C._X___O ___________________~r::''---________________________________________~,~--------------------------- AM RGI (rRO,'vl \ ---- SYNC X (INTERNAL DN/0911) c ADDR ACCEPTED X FAST CLEAR:, ""Etr'ORY) : 200 NS MAX AM SYNC (i) B 200NS--: I ~ r---\ f--- MAX : ~ I : .!!----------.'-L--____________________________ MAX 4_0_0_N_S __---.----'-'-------'/r' ........ - - - - - - - - - , 1 . . -_______________________ ': (FROM M£MORYTO DM0911) YNC X (I)-A PHASE SErf! CC x (If'lTERNfiL DM0911) '--__---'I '----J SYNC x(o)· SET D X (I). i9 PHIlSE CH X FIIST Rq (FROM DM091l TO DE.V x) CHXRQIN (FROM DEV X TO DM0911) B 5£TM.A.""("B.~ SET D X (iNTERNAL D/'IJO 9/1) SLOW CYCL£:(O)-SETAX(O)'D SLOW CYCLE (INTERNAL DM0911) r PHASE . -----------------------~ CHX FAST RQ (-3)'SYNC.X(I}·Il'M RG/---3 to 9 /'liS /lI B A A 8 7 6 5 .4 3 2 TD-DM09-A-8 Sheet 1 of 2 Timing Diagram 27 DM09A 6 7 8 4 5 3 2 D D Ai';, GRANT u U(120 NS) (F i' (;M ME/IIOR f TO DWi0911) u AM STROBE (FROM MEMORY TO DM091i) ~SET D X (I)' SET II x{I)· A ADDR ACC£. PTED (Ui X) - - - - - - - - - - - t U (320 (FROM DM09-"l TO DEV X) PHIISE u NS) _ _ _ _ _ _ _ _ _ _ _----I~ SLOW C yeL£. (!IS) 'SET D X (I). D PHASE. c Dt'iTA READy (U/X) c u U(320 N5) (FROM DM09A TO DEY X) _ _ _ _ _ _ _ _ _ _ _----I~CHX RQ IN (-3)' SET D )«(1)'D PHASE CA-:-A ACCEPTED (CHX) . (FROM DIVI() '7/1 TO DEli X) C H X IlDOR (FROM DEY X TO D/Vi091l) Uf320 N5) ADPR ACC.EPTED X=" \ ---.l / Y DATI'! ACCEPTE.D ' - - - - - - " - - - - - -~'I X ~/~~~~~------------------------------~--~ DATA (FROM D£V' X TO DM09!1) CH X 5ET'lS£. /l MPS ((",,-..... \'-. - R3 7,500 3639B y1-+-lJ ~~l ~ "'fEj~, ~ >:~o - ~ . ~~ M~~ ~~D .. RI3 \ '-. DEC 3639B -1--,m ..l ~ ~~~ L "% ,,~~':~:~% R7 1,500 3639B ~"~%:" T RI4 1,500 RI5 1,500 RI6 750 RI7 7,500 R21 1,500 5~ J;" DEC 3639B -." R27 100 10% R26 7,500 () J ,----4 R28 1,500 R29 >750 R30 >750 L----+-----r-----r--------;-~ -1!lV UNLESS OTHERWISE INDICATEO; RESISTORS ARE 114W; !I' DIODES ARE 0664TRANSISTORS ARE DEC 3009B B-C5-B213-0-1 31 Jam Flip-Flop :: DID ~ I 0664 OS IiI1 0664 OF 09 ~: ~ 0864 04 ~ 0664 08 ~: ~ 0684 03 IiI1 0864 07 ',: :: .1 0864 02 ~ 0664 06 ~ 0664 01 IiI1 0684 J I I I B-CS- R002-Q- 1 OK ON Os OV Diode Cluster r-----------------------------~~----------------------------~~------------------------------OA+IOV(Al r------, r-----------------~------~----------------------_+------._--------~--~I_e--~C : I : I 02 01 DEC3639 I DE 3639 2 GND : I 019 o-ee2 ~ I I I I Oil I 0-882 : 017 I I o-el2 : I ,,0-..........-. 00---..1....,..... Eo--",~,--ol De 0-M4 L 0---1....-..--0111 010 0-884 I I O-ee2 : I I I I I I I Oil I I 1M 1l1,000 I I i ~----~--~~----------------~~----~----------------------~~----~------------~~~----~.-~V -3V I I : _____________ EXAMPLE DGL2 .J: I.. LSTRATE ______ JI UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4W; SOt. PRINTED CIRCUIT REV. FOR OGL BOARD IS SIB B-CS-Rl11-0-1 Diode Gate 32 r-----------_.------------~------------~------------._------------~----------~._--.--~--------------OA.IOV(A) .. ------j r------r----~~----~----~------+_----._------r_----~------+_--~~----r_rr--_.----~~~~~2----4I--oCGNO 08 : 0-662, 09 I 0-6621 , 010 0-662 ~--~----4-~~~------~_4~_+----~--~--~----~~_4--_+----~--~~~r_--+_~~~--+_.6 1 j 011 1 0-662' : I RI5 1,500 I : I I _.'--=+---7-4>------1--0 B -15V I -3V I L STRATE ______ JI R22 : 15,000 I I ____ .JI M UNLESS OTHERWISE INDICATE 0: RESI STOfIS ARE 1/4 W; 5% DIODES ARE 0-664 TRANSISTORS ARE DEC 36399 PRINTED CIRCUIT REV. FOR OGL BOARD IS SIA B-CS-S 107-0- 1 ]~O 43 ~~044 ~~46 ~~045 Inverter ~~047 4 ~049 ~~050 ~~048 ~P I-()L I--OE ~V ,... A.IOV(A) ----R4 100,000 "'04 CI ';.1 ... 0 ~l 1\ !3 ... ~6 ~~~ ' F .. ~ ~ '8~62 05 ?J ..... RI 12,000 10% r080,ooo~ '016 08 R3 .. ~IJ 09, H O~ C2 ~~ 1\ rP14.... ~ f-0-662 ~ '8~62 Oil ~ ~'025 C3 O~ .... N ~~ "K 1\ rozo ... ~~07 R5 3,000 R6 3,000 ~~~~ , ~2 ... ~ ~~012 R9 12,g~/~ ~.. \1 .a .. ~ '8~~62 ...~ o~ Ot7 R 13 OTHERWISE "9T 1 RIO 12rg~~ RII 12,000 10% R 12 121g~/~ .4. 026 D51 INDICATED 6 ~ 0";'4 ~ ,0:B' 0-662 3 ~ '8_ l62 B-CS-S202-0- 1 .... 052 33 Dual Flip-Flop ~~ GNO 1~,g~262 \\ 0j7 .... O~ .... ~, g~~2 U 030 S RI5 3,000 M TRANSISTORS ARE DEC 3639C RESISTORS ARE 15,000 RESISTORS ARE 114W\5% CAPACITORS ARE MMFO DIODES ARE 0- 664 ,... C C4 RI7 .... ~ UNLESS :b'g,ooo~ '035 ?;.I ... R2 12,000 10% ~4 v R7 R 14 100,000 RI6 3.000 ~~D31 ~,g~~62 ~6 ... RI9 12,000 10"1. C5 .01 MFO :.:: R20 12,000 10% " g:~62 ~ T ~ 1,500 B-15V A.IOV(A) C GND 046 0-662 0411 0-662 044 0-662 043 0-662 B-I!5V R211 1,Il00 UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4W; 5"1. CAPACITORS ARE MMFO DIODES ARE 0-664 TRANSISTORS ARE DEC 3639C B-CS-S203-0-1 Triple Flip-Flop A-IOV(A) R3 IOODO 5"1. ~ ....., ,,~Oll ... .. 02 ~ R 23 47 \b DEC 2894-2B .... ~ R2 15pOO 5"1. R5 .. I,!SOO 5"1. ~ _ P ~ ~010 R 7 .. 3,000 5% ~1 ... ..012 10,000 03 :~4 \b. M () AB RII V- ~ ~024 ~ .022 ~6 ... RI4 3,000 5"1. ~ GND ,,040 0-66 06 ~ ~ ~ ~g~2 C,H,N.U 10,000 05 :~5 ~'8~~62 0.1.2 ~ RI2 1.'500 5"1. -.. DEC 2894-28 ...- .... 4 ~D35 15% ~7 ~_~'62 ....-;:: : : iio R9 15,000 5"1. '~ 100,000 04 ~'8~~62 ) '~ ~~023 ~ F ;:r-i~o eJ t¥ ~5 Ojl ,'8?662 J~ ~ ~-2,ooc 10,000 01 ,,&..6662 '~! RIO .... ;;: ~9 ... 1'-----4 ~~~oo 5"1. RI9 .. 1.s00 5% R 15 RI8 7f 2iit2B ~3 T :::i~o ) .034 R21 .. 3,000 5% ~036 .01 ~t ~ "g~:6 C7 MFa;: =-..01 MFO ~ .-- ~8:36 ,,037 0-68 R22 ItlOO 5% B-15V E ..... 01 ~'D44 RI R4 ' 12,000 ~2d/~00 5"10 CI B~, 1\ ,... O...! ~09 ~20&200 ?! 0 ) f"'IIJ "045 L ) 0':"3 .., '''046 ~ '021 ~2~~00 ~2~00 ~; 1\ 0..!.8 ... S K C3 DjO "047 ... "04B O~ f"'IIJ UNLfSS OTHERWISE INOICATEO RESISTORS ARE 1/4Wi 10"10 CAPACITORS ARE MMFO 010 OE S ARE 0 - 664 TRANSISTORS AR E DEC 3639-C B-CS-S603-0-1 34 ~A7.°0 C5 8~1 0':"5 ,....- ~ '033 Pulse Amplifier ......... 032 R () ~~049 r------, r-----------~--------_.--------_1~------~~--------~--------~~------~._--------~--------.--~~--~,------Os-lev , , I I I R4 D4 o 5,000 De R8 3,000 8 R8 5,000 02:S I 0-862 I I 022 I 0-862 I I 021 I 0-682 I [10 E C2 .01 IIIFO III 020 I 0-882: I L2 -----t t-----~._----~~--~C 018 I 018 I GNO 0-e82: CI 0-'.82 1 I 1111'1> 017 I 0-882 1 I 018 I 0-e821 .01 C3 .01 IIIFO I , I I I , I : UNLESS OTHERWISE INDICATED: RESISTORS ARE V4W-, 5 .. DIDOES ARE 0-"" -3V 'STRATE L.. _____ ..JI B-CS-W005-0- 1 Clamped Loads RIO :S:SO ~ ~ 5 i !l ~ l! ~ 5 0 III AI-lev eA.IOV AC CJNO RII RI R8 1,100 no 1,100 C:s .01 IIIFO BT BN 7,!IOO R9 7,eoo !I"Io 5°/. R7 C4 .01 MFD aBB -lev IN.ESS OTHERWISE INDICATED' RESISTORS ARE 114W; 10 .. DEI - DE4 ARE DEC NO. 330-25E-I B-CS-W300-0- 1 35 Delay Line M GNO C GNO r-------------------------~----_+--------_4~----------------------~~----r_------__oA +IOV RI2 100,000 015 K~9 RI6 10,000 10'"1. 470 MMFO IOOV 5"10 022 0662 021 0662 020 0662 019 0662 -7. !IV RI7 1,500 .---+---O B -15V UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4W; 5 % DIODES ARE 0664 B-CS-W612-0-1 Pulse Amplifier A 018 032 0662 .....,:.::..:JL...:.::::...=..._____-I-_____.. 0662 0 III 031 0862 030 0682 0662 014 0682 013 0662 H 028 0662 027 0662 0682 011 0882 RI4 1,500 R26 7,1100 AI3 1,000 <:r-'"V\Ar-......---Q U 112W 05 07 R28 1,1100 R27 1,000 All 20,000 02 BOURNS OR DAYSTROM 018 UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4W; II ... CAPACITORS ARE .. MFO DIODES ARE 0664 TRANSISTORS ARE OEC3839 B-CS-R302-0-1 +CIO 39 -MFO 029 0682 ....·-+-.012 RI2 7,500 +IOV CGNO One-Shot De lay 36 021 023 R211 20,000 1/2W BOURNS OR OAYSTROM B -IIiV Digital Equipment Corporation Maynard, Massachusetts printed in U.S.A.