Delta-sigma Adc Conversion Time Reduction In Multiplexed Mode

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Delta-Sigma ADC Conversion Time Reduction in Multiplexed Mode AN44279 Author: Victor Kremin Associated Project: Yes Associated Part Family: CY8C24x94, CY8C24x23, CY8C27x43, CY8C29x66, CY8CLEDxx ® Software Version: PSoC Designer™ 5.1(SP1.1) Associated Application Notes: AN2239 H H H Application Note Abstract 0B Delta-Sigma (DelSig) ADCs are widely used in customer applications that require high resolution, good noise suppression, fine linearity, and good scanning speed. This application note describes how to reduce DelSig ADC scanning time in multiplexed mode, and how to adjust the ADC conversion time. The proposed method reduces the single channel scanning time by almost 30 percent. Figure 1. DelSig ADC Block Diagram Introduction 1B ® TM The PSoC Designer user module library provides different DelSig ADC configurations with resolutions from 6 to 14 bits, and scanning speeds from 65 ksp (6 bits) to 7.8 ksp (14 bits). Refer to the application note, AN2239, for comparisons and recommendations of different ADC types for different applications. H X Different PSoC devices have different hardware implementations of the decimator. The CY8C24x23 and CY8C27x43 devices have Type 1 decimator, which supports the hardware double integration function only. The differentiation function must be implemented in firmware, resulting in high CPU overhead at high sample rates. The CY8C24x94 and CY8C29x66 devices have the Type 2 decimator, which implements both integration and differentiation functions in hardware. All devices except the CY8C24x94 require an external timer to form a differentiator latch strobe signal. The decimator in the CY8C24x94 can operate with an external timer or an internal timer. This creates a DelSig ADC that uses no digital blocks used. This technique is used in the CSD/CSDADC and DelSigPlus UM, which leaves more digital blocks for other purposes. July 4, 2011 R+ - ∫ R+ R- - ∫ + Latch + Latch φ2 φ2 R- H The DelSig ADC consists of a sigma-delta modulator and a modulator bitstream filter. Figure 1 shows an implementation of a Delta-Sigma ADC with a second order modulator on a PSoC device. The user module library contains ADCs with first and second order modulators. The sigma-delta modulator converts analog values into a single-bit variable density bitstream. The digital filter processes the variable density bitstream to form the multibit readable values. The bitstream digital filter 2 implemented inside a PSoC device decimator is a Sinc 2 filter. The Sinc filter contains a cascade connection of the double integrator with a double differentiator. The integrator runs at modulator clock rate, and the differentiator operates at sample clock rate. X Double Integrator Second-order Sigma-Delta Modulator Vin Data Clock φ1 ÷4 yi Double Differentiator φ2 φ1,φ2 Fs Generator Sample Rate Counter Latch Fs Fs - Data Latch Dadc Fs DelSig Scanning Time Reduction 2 The decimator Sinc transfer function is written as: (1 − z ) H ( z) = (1 − z ) −M 2 −1 2 Equation 1 The denominator reflects the double integrator function, and the numerator corresponds to the differentiator, which is a second order FIR filter. M is the decimation ratio, that is, the number of accumulated double integrator samples within the sample interval. 2 Therefore, the Sinc filter latency is 2 samples caused by the numerator. This requires skipping 2 data samples before obtaining a valid third sample value after the ADC channel change. This latency does not create any issues in data-stream (for example, audio) processing applications. However, this may be strongly undesirable when ADC operates in the multiplexed mode or is part of the closed loop control system (for example, BLDC motor control, or servo control), where additional phase delay can create loop stability issues. Document No. 001-44279 Rev. *B 1 AN44279 The alternative to the DelSig ADC is an incremental ADC, which differs only by a digital filter. It operates in the single integration mode and produces the first valid sample after conversion starts. But the incremental ADC is slow, especially at higher resolutions, taking into account that R+2 (R: resolution in bits) column one sample requires 2 clock cycles. The Sinc' type filters are easy to implement in silicon (only adders, no complex multipliers), but they tend to be quite long and are slow to respond to a change in the input. The best method is to have FIR-type filters that are processed quickly and deliver a new output word after only one sampling cycle. Unfortunately, this approach is not supported natively by existing PSoC devices. Figure 2. The ADC Conversion Timing Diagram Ti – short cycle, Ts – full cycle y2 y1 y0 Ti Ts Ts The differentiator transfer function may be written as: Hd ( z) = 1 − 2 z − M + z −2 M (1 − z − M ) = 2 Equation 2 By solving the transformation to the time domain, the equation may be written as: Dadc =y2 − 2 y1 + y0 Equation 3 Here, Dadc is the output sample data and y is output of integrator. Equation 3 may be written in this equivalent form: un = ( y2 − y1 ) − ( y1 − y0 ) Equation 4 Here y2 is the freshest integrator sample, and y0 is the oldest. This means only two full integration intervals are required after a channel change to get a valid sample after the second sample interval. This reduces the single channel scanning time from 3 to 2 full samples. There are several possible methods to implement it in practice. The simplest way is to do the channel multiplexing inside the ADC’s conversion interrupt service routine (ISR). However, this solution has a drawback. The ISR latency time adds to the conversion error, which is proportional to the latency and signal difference between the ADC channels. Also, the new ADC channel input signal must be available before triggering the conversion ISR. The proposed solution has no ISR latency effect influence and allows the conversion to start at any time. On starting, the decimator latch is triggered within a short interval period to capture the first y0 sample. Later, two full conversion intervals are processed to capture y1 and y2 samples respectively. The conversion sample is now valid and can be read. Figure 2 illustrates this operation. In addition, the short conversion time is used to empty the sigma-delta modulator of the previous analog sample. This is an alternative to resetting the modulator integrators. X ts t0 t1 t2 t To implement the proposed technique, a decimator external counter period buffering feature is used. When the counter is disabled, a period value is loaded to the counter period register, and transferred automatically to the counter data register. When the conversion starts and the counter is enabled, a new sample conversion value is loaded in the period buffer register. When the counter underflows, a full period value is copied from the buffer register to the period register, and a normal conversion cycle is started. At the same time, the y0 value is passed from the integrator to the differentiator. When the counter underflows from two full conversion intervals, it captures the y1 and y2 samples. It is easy to implement the proposed method in the code using the DelSig UM. Only one assembly routine from UM library, called DelSig_StartAD, is modified. The new routine is named as DelSig_StartADOpt and is located in a separate assembly file. The newly added code is marked in italics in the following code. Code 1. A DelSig_StartADOpt Routine DelSig_StartADOpt: _DelSig_StartADOpt: RAM_PROLOGUE RAM_USE_CLASS_1 M8C_EnableIntMask DelSig_INT_REG, DelSig_INT_MASK and reg[DelSig_PWM_CR0_LSB], ~CONTROL_REG_ENABLE_BIT //stop PWM mov reg[DelSig_PWM_DR1_MSB], 0 mov reg[DelSig_PWM_DR1_LSB], 0x0F //load small period value to counter X or reg[DelSig_PWM_CR0_LSB], CONTROL_REG_ENABLE_BIT mov reg[DelSig_PWM_DR1_MSB], 0x1 //load integration interval mov reg[DelSig_PWM_DR1_LSB], 0xFF //write FF for 12 bits resolution by 4 increments RAM_EPILOGUE RAM_USE_CLASS_1 ret July 4, 2011 Document No. 001-44279 Rev. *B 2 AN44279 power supply voltage monitoring device under or over the voltage response time. Using the modified DelSig ADC in multiplexed mode is the same as a conventional ADC. Three samples (1 short, 2 full) are skipped and the valid sample is read. Code 2 illustrates this. H  H Code 2. An ADC_GetSample Routine for Multiplexed Operation To match the ADC count weight to reflect some physical meaning (for example, 1 Count = 1.00 mV) to avoid additional scaling. This is easy to do with a DelSig ADC too. You must adjust a full sample conversion counter period by loading different values in the counter period registers. The decimator overflow check must be adjusted inside the ADC conversion routine. The simplest way is to use the ADC UM with the maximum required resolution and limit conversion samples later in the user code. The ADC sample counter overflow period must be a multiple of 4, because it operates at a frequency four times higher than the decimator. This is sourced from the analog column clock directly, as shown in Figure 1 on page 1. Therefore, the allowed values for counter period values register are only: WORD ADC_GetSample() { WORD temp; DelSig_StartADOpt(); LED_ON(); while(0 == DelSig_fIsDataAvailable()); DelSig_wGetDataClearFlag(); while(0 == DelSig_fIsDataAvailable()); DelSig_wGetDataClearFlag(); X while(0 == DelSig_fIsDataAvailable()); temp = DelSig_wGetDataClearFlag(); X PK =4 ⋅ M − 1 LED_OFF(); Equation 5 Here M is an integer number, which sets the decimation ratio. The effective ADC resolution R in bits is evaluated by the following equation for the first (Rsng) and second (Rsec) order sigma-delta modulators [1], p.464: DelSig_StopAD(); return temp; X } The LED_ON() and LED_OFF() macros are used to measure the sample conversion time using a scope. A DelSig ADC with 12 bits of resolution is used. The second order modulator and the VC1 clock frequency are set to 8MHz (VC1=3). When the standard DelSig_StartAD() routine is called to start the ADC conversion operation, the single channel scanning time measured is 194 µs. Using the proposed method reduces the scanning time to 140 µs, including the function call. The CPU clock is set to 24 MHz at 5 V power supply. The design has been tested successfully at 3 V operation and a 12 MHz CPU clock. No inter-channel interference was observed for different channel input values. After DelSig_StartADOpt() is called, the second and all following samples are run through standard conversion intervals. This means the following values are read in same way as for the standard DelSig ADC. DelSig Resolution and Conversion Time Fine Tuning X  ln ( M )  R sng = 1.5 ⋅ ( log 2 ( M ) − 1) = 1.5 ⋅  − 1  ln ( 2 )   ln ( M )  − 1 R sec =2 ⋅ ( log 2 ( M ) − 1) =2 ⋅  ln 2 ( )   Equation 6 This application requires limiting the single channel scanning time, including the supported code execution to 130 µs. The supporting code execution time is 10 µs, leaving 120 µs for ADC conversion. Taking into account that the minimum analog column cycle time is 3/24 MHz = 0.125 µs, there are a total of 960 cycles for sample conversion. If the first sample requires 16 cycles, 472 (M=118) cycles are allocated for each following conversions. Therefore, write 471 (1d7h) must be written to the period register. The effective ADC resolution is 11, 75 bits according to Equation 6. 2B Some applications require precision DelSig conversion time tuning for the following reasons:    Summary 3B ADC To match the conversion time to the integer number of noise signal periods (for example, AC main’s frequency, some PWM signals, and others) for SNR maximization. This application note describes the simple mechanism of reducing the scanning time for a DelSig ADC in the multiplexed configurations, and precisely tuning the conversion time. References 4B 1. To adjust the conversion time to an external synchronization signal period. ® PSoC Programmable System-on-chip, Technical Reference Manual (TRM), Ver 2.10 To fit customer specifications for the response time. For example, to obtain the required multi-channel July 4, 2011 Document No. 001-44279 Rev. *B 3 AN44279 About the Author 5B Name: Victor Kremin Title: Ukraine Solution Center Applications Team Leader Background: Victor Kremin has spent more than 4 years in USC. His interests involve the full cycle of embedded systems design, including various processors, operation systems, and target applications. Contact: [email protected] July 4, 2011 Document No. 001-44279 Rev. *B 4 AN44279 Document History Document Title: Delta-Sigma ADC Conversion Time Reduction in Multiplexed Mode – AN44279 Document Number: 001-44279 Revision ECN Orig. of Change Description of Change Submission Date ** *A 2184046 2918133 VICK VICK 03/07/08 04/19/10 *B 3301682 ANBI_UKR 07/04/11 New Application Note. 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