Transcript
Ministry of Science, Research & Technology (MSRT)
Downloaded from isseem.ir at 0:27 +0330 on Monday October 23rd 2017
Iranian Research Organization for Science and Technology (IROST)
The third Iranian Conference on Engineering Electromagnetic (ICEEM 2014), Dec. 3-4, 2014
Design and analysis of a 3.1–10.6 GHz UltraWideband Low Noise Amplifier in 0.13μm CMOS Masumeh Shams*, Esmat Rashedi
Ahmad Hakimi
dept. Electrical Engineering Graduate University of Advanced technology Kerman, Iran *
[email protected]
dept. Electrical Engineering Shahid Bahonar University Kerman, Iran
Abstract—In this paper, a new low complexity ultra-wideband (UWB) 3–10.6 GHz low noise amplifier (LNA) is designed which is consisted of three stages. To overcome the input stage constraints such as broadband impedance matching and high gain while keeping low-power consumption, the combination of the current reuse and reactive feedback technique are applied as the first stage. The second and third stages are common source amplifier with an inductive peaking technique to achieve high flat gain and wide –3 dB bandwidth simultaneously. Analytical formulae are derived for describing the input impedance, gain, and noise figure. The LNA is designed in the standard 0.13 µm CMOS technology which provides 17 dB power gain while consuming 15 mW from a 1-V voltage supply. The average noise figure is 5.5 dB and the simulated input-referred IP3 (IIP3) is 7.7 dBm. The input return loss (S11) and output return loss (S22) are less than -10 dB and -25 dB, respectively. The reverse isolation (S12) is better than -54.52 dB. Keywords-component; Low noise amplifier; Ultra-Wideband; current reuse; reactive feedback.
I.
INTRODUCTION
A critical block in the Ultra-Wideband (UWB) receivers is low noise amplifier (LNA). It is the first block to amplify the received signal from the antenna [3]. Since it determines the overall system sensitivity, all the elements included in the structure must be studied and designed simultaneously [4]. UWB LNA must provide several stringent requirements such as a good broadband input impedance matching, sufficient and flat gain, a low noise figure (NF), low power consumption, and good linearity within the entire frequency band [1]. For reducing the noise figure of the entire receiver block, this stage should introduce as little noise as possible while giving sufficient power gain to the weak signal received from the antenna [4]. In order to provide sufficient power gain, different structures have been reported such as cascode structure [5,2], current reuse techniques [1,6], and cascaded structures [7,3]. To provide an appropriate broadband matching
network, numerous configurations were proposed such as the inductive degenerated common source [7], common gate structure [2], filter matching network [5,3,9] and feedback technique, such as resistive feedback [8] and dual reactive feedback [5]. Each of the forementioned topologies has some advantages and some disadvantages which forces the designer to select the one that provides a good trade-off between their arbitrary goals. In this paper, to overcome the shortcomings of previous LNA topologies, a three-stage cascaded LNA is proposed which is analyzed in next section. II.
DESIGN AND ANALYSIS OF LOW NOISE AMPLIFIER
A. The proposed circuit In this paper, a three-stage cascaded LNA is proposed. Since, the input stage should overcome several constraints such as broadband impedance matching for maximizing power transfer, high gain for reducing the noise figure of subsequent stages and keeping power consumption as low as possible, the first stage is designed based on the current reuse and reactive feedback topology. The second stage of the proposed LNA is a simple inductive degenerated common source with shunt peaking technique to provide high gain in the frequency range. To obtain more gain increment, besides using shunt peaking technique, a common source structure with gate-drain reactive feedback is applied as the third stage. The shunt peaking inductor, used in both second and third stages, is to resonate with output parasitic capacitors of the stage and input capacitors of subsequent stage in the desired frequency range. Hence, the plausible gain roll-off is compensated, and the bandwidth is extended. Two resistors are connected to the drain of the second and third stage in series with the shunt peaking inductor to reduce the quality factor of the inductor and extend
This paper is authentic if it can be found in www.isseem.ir.
Ministry of Science, Research & Technology (MSRT)
Iranian Research Organization for Science and Technology (IROST)
The third Iranian Conference on Engineering Electromagnetic (ICEEM 2014), Dec. 3-4, 2014
Downloaded from isseem.ir at 0:27 +0330 on Monday October 23rd 2017
the bandwidth of the LNA. However, the existence of the resistors causes some drawbacks like peaking in the gain response and additional noise. The third stage transformer feedback not only enhances the gain in the frequency range but also entwines inductors to further reduce the chip area. The schematic of the proposed ultra-wideband LNA is shown in Fig. 1.
Zin
1
R Cgs Cgd
´
2
2 gm M j Lg R Cgs Cgd ´
2
2 gm M Cgs Cgd ´
1
C 2
gs
Cgd
´
(1)
Where R represents the bias resistor and Cgs is equals to summation of Cgsp and Cgsn. The capacitor C gd ´ stands for the input Miller capacitance of Mp and Mn, which is equal to:
Cgd´ Cgdn Cgdp 1 Av1,low _ freq
(2)
The parameter Av1,low_freq is the low frequency gain of first stage and is approximately equal to -2gmR1. The parameter M represents the mutual coupling between the inductors Ld and Lg and is equal to M Ld Lg .
Figure 1. The proposed CMOS LNA circuit.
Analytical formulas for describing the impedance matching, gain, and noise figure are derived in sequel. B. Wideband input impedance matching The proposed impedance matching circuit consisted of a transformer Lg and Ld, and a transistor pair Mp and Mn, is shown in Fig. 1. By combining the current reuse and reactive feedback technique, a low power topology is designed which is suitable for ultra-wideband impedance matching. Comparing with conventional cascode topology, current reuse technique enhances overall equivalent transconductance from gmn to gmn+gmp for the same biasing current. So, it has lower power dissipation and provides low voltage capability [1]. By applying reactive feedback, two feedback paths are provided: series inductive feedback via transformer and shunt capacitive feedback via parasitic gate-drain capacitance (Cgd). Impedance matching at lower frequencies is achieved by the shunt capacitive feedback, and at the higher frequencies is achieved by the series inductive feedback of the transformer. Hence, the wideband matching is achieved by separating the desired bandwidth into low and high frequencies [1]. Furthermore, by using reactive feedback technique, the gain peaking at the middle of the frequency range is compensated and the flat gain is achieved. The input impedance of the proposed CMOS LNA is expressed by:
Since, NMOS and PMOS transistors operate almost equally in term of the amplification; they possess the same transconductance which means gm=gmn=gmp [6]. For input impedance matching, the real part value of Zin should be equal to the source impedance, Rs, which it can be expressed as: Real Zin =
1
R Cgs Cgd
´
2
2
2 gm Ld Lg
Cgs Cgd ´
RS 50
(3)
C. Noise analysis To understand noise performance of the proposed LNA, its noise figure should be extracted. This section analyzes the noise figure of the circuit. In this analysis, for simplicity, the thermal channel noise of the transistors and the thermal noise of resistors have been considered as the dominant noise sources in the circuit. However, the losses in other elements such as the loss of the transformer can appear as additional noisy elements in the circuit. For simplicity, the flicker noise and the gateinduced current noise are neglected [5]. Ten sources of noise have been considered: the thermal noise of source resistor, the thermal noise of the resistors Rs,R, R1, R2, RD1, and RD2 , and the thermal noise of the channel current of Mp, Mn, M1 and M2. Assuming that all the noise sources are uncorrelated, the total noise figure can be expressed as summation of the forementioned noise contributor noise figures as follows: NF 1
R 1 Rs 2 Rs gm RD12 RD 22 4 gm2 Rs RD12 RD 22 R1
The third Iranian Conference on Engineering Electromagnetic (ICEEM 2014), Dec. 3-4, 2014
Ministry of Science, Research & Technology (MSRT)
Iranian Research Organization for Science and Technology (IROST)
Downloaded from isseem.ir at 0:27 +0330 on Monday October 23rd 2017
4 Rs gm2 gm1R12 RD12
1 4Rs g m2 g m12 R12 RD1RD22
R2
4 Rs gm2 gm12 R12 RD12 RD22
2 gm gm1R1RD1 2 gm2 Rs
(4)
1 2
2 gm gm1gm2 R1RD1
RD2 Rs
The following parameters can be tuned to decrease the noise figure of each component. (RS is fixed at the system level):
Increasing gm, gm1, gm2.
Decreasing R and R2.
Increasing R1, RD1 and RD2. III.
D. Voltage gain transfer function To determine the voltage gain of the proposed amplifier, the gate-drain capacitances, Cgd, and the output resistances, rds, of the transistors are neglected. After applying KVL and KCL to form and solve the voltage and current equations, the voltage gain is derived as follows: Gain
Vout H1H 2 H 3 Vin
(5)
Where the parameters H1, H2 and H3 represent the transfer functions of the first, second and the output stages, respectively and are as (6)-(8). H1
2 g m R1 || Zin2
(6)
Lg 1 S 2 gm M S 2 Lg C gs R
H2
H3
m1Ls1 S
2
Ls1Cgs1
(7)
M ´Cgs 2 2 g m2 RD 2 Ld 2 S S g m2
1 M g ´
m2 S
Lg 2 Cgs 2 S 2
(8)
Zin2 and Zin3 are the equivalent input impedance of the second and third stages, respectively, which are Zin2
g L 1 m1 s1 , SCgs1 Cgs1
SIMULATION RESULTS AND DISCUSSIONS
The designed circuit shown in Fig. 1 is simulated with Agilent Advanced Design System (ADS) tools in 0.13μm CMOS process. Fig.2 shows that the proposed LNA provides a 17 dB power gain (S21) and reverse isolation (S12) better than 54.52 dB. Moreover, Output and input return loss (S22 and S11), shown in Fig. 3, are less than -10 dB and -25 dB, respectively. Fig. 4 demonstrates that the proposed LNA achieves an average noise figure of 5.5 dB, which is considered appropriate for wideband low noise application. From a single tone test at 6 GHz, the ICP1dB is achieved around -18 dBm, while a two-tone test at frequency of 6 GHz with a 500 MHz tone separation indicates an IIP3 of -7.7 dBm. Both of these points are plotted in Fig. 5. Table 1 summarizes the characteristics of the proposed UWB CMOS LNA compared to the recently published works. IV.
g m1 R2 || Zin3 || Ld1S RD1
1 Sg
The following parameters can be tuned to increase the voltage gain: Increasing gm, gm1and gm2. Increasing Ld1 and Ld2. Increasing the transconductance gm, gm1and gm2 can lead to gain enhancement and NF degradation, simultaneously. To increase the transconductances, either transistor width or channel current can be increased. Higher transistor width increases parasitic capacitance, reduces bandwidth, and higher channel current increases power consumption. Therefore, increasing the transconductance is set by the bandwidth and power consumption requirements. Hence, a reasonable width choice is necessary in order to achieve a trade-off between all performances and to meet specifications.
and Zin3 Lg 2 S
1 SCgs 2
. The
parameter M represents the mutual coupling between the inductors Ld3 and Lg3 and is M Ld 2 Lg 2 .
CONCLUSION
A three-stage UWB CMOS low noise amplifier has been proposed. At the first stage, the combination of the current reuse and reactive feedback topology has been applied which broadband impedance matching and high gain has been achieved. At the second and third stages, a simple common source with shunt peaking technique has been used to enhance the gain in the frequency range. Moreover, for more gain improvement, reactive feedback has been used in the third stage. Using a 0.13 μm CMOS technology, the designed LNA achieved a power gain of 17 dB in the frequency range 3.1– 10.6 GHz while consuming 15.21 mW from a 1 V supply voltage. The average noise figure was 5.5 dB and IIP3 was -7.7 dBm at the frequency of 6 GHz.
Ministry of Science, Research & Technology (MSRT)
Downloaded from isseem.ir at 0:27 +0330 on Monday October 23rd 2017
Iranian Research Organization for Science and Technology (IROST)
The third Iranian Conference on Engineering Electromagnetic (ICEEM 2014), Dec. 3-4, 2014
Figure 5. IIP3 and the 1 dB compression point for the proposed LNA at 6 GHz.
TABLE I.
Ref [9] Figure 2. S21and S12 of the proposed circuit.
[1] [10] This
COMPARISON OF THE SIMULATED RESULTS OF THE DESIGNED UWB CMOS LNA AND RECENTLY PUBLISHED WORKS. S21 (dB)
S11 (dB)
S22 (dB)
9.3
<-9.9
<-10
15.6 7.7-8.2 16.85±1.5
<-10 <-17.5 <-10
<-10 <-25
Pdc (mw)
NF (dB)
IIP3 (dBm)
Tech (nm)
9
4-9.2
-6.7
180
14.1 10.86 15.21
2.8-4.7 2.4-4.56 5.4-5.7
-7.1 -7.7
180 130 130
REFERENCES [1]
Figure 3. S11and S22of the proposed circuit.
Figure 4. Noise figure of the proposed LNA.
W. Chunhua, W. Qiuzhen, A 0.18 um CMOS low noise amplifier using a current reuse technique for 3.1–10.6 GHz UWB receivers, Journal of Semiconductors 32 (2011) 085002-1- 085002-6. [2] Y.T. Lo, F. Kiang, Design of wideband LNAs using parallel-to-series resonant matching network between common-gate and common-source stages, IEEE Transactions on Microwave Theory and Techniques, 599 (2011) 2285-2294. [3] A. Slimane, M. Trabelsi, M.T. Belaroussi, A 0.9-V, 7-mW UWB LNA for 3.1–10.6-GHz wireless applications in 0.18-mm CMOS technology, Microelectronics Journal 42 (2011) 1263–1268. [4] B. Razavi, RF Microelectronics, 2nd Edition, Englewood Cliffs, NJ: Prentice-Hall, 2011. [5] C.T., Fu, C.N., Kuo, S. S., Taylor, Low Noise Amplifier design with dual reactive feedback for broadband simultaneous noise and impedance matching. IEEE Transactions on Microwave Theory and Techniques, 58 (2010) 795-806. [6] M. Rezvani, Sh. Ardalan, K. Raahemifar, High gain, low power, CMOS current reused LNA with noise optimization. 26th IEEE Canadian Conference of Electrical and Computer Engineering (CCECE), (2013) 16. [7] MR. Salehi, E. Abiri, H. shahraki, MS. Mirzazadeh, A 0.7 dB noise figure UWB CMOS LNA with reactive feedback in 0.18µm technology, International Conference on Advances in Electrical and Electronics Engineering (ICAEE) Penang, Malaysia, (2012) 349-352. [8] M.T. Reiha, J.R. Long, A 1.2 V reactive-feedback 3.1–10.6 GHz lownoise amplifier in 0:13-um CMOS, IEEE Journal. Solid-State Circuits, 42 (2007) 1023–1033. [9] A. Bevilacqua, A. Niknejad, An ultra wideband CMOS low noise amplifier for 3.1–10.6-GHz wireless receivers, IEEE Journal Solid-State Circuits, 12 (2004) 2259–2268. [10] H.Y. Yang, Y.S. Lin, C.C. Chen, 2.5 dB NF 3.1–10.6 GHz CMOS UWB LNA with small group-delay variation, Electronic Letters, 44 (2008) 528–529.
