Design And Simulation Of Ddr3 Sdram Controller For High

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548 Vol 04, Article 06124; July 2013 http://ijves.com International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 – 6556 Design and Simulation of DDR3 SDRAM controller for High Performance in VHDL AJAY, ADESH KUMAR, DHIRENDRA SINGH GANGWAR M.Tech Scholar VLSI Design, Faculty of Technology, Uttarakhand Technical University, Assistant Professor, Department of Electronics Engineering, University of Petroleum & Energy Studies, Dehradun India, Dehradun India Assistant Professor, Faculty of Technology, Uttarakhand Technical University, Dehradun India [email protected], [email protected], [email protected] ABSTRACT As the requirement or the fastest, cheapest memory and system bandwidth increasing day by day. Hence, memory technologies have been optimizing for higher speed, performance and throughput. So, the complexity of the instructions is also increase with increase in technology. The next generation family of DDR RAMs (DDR3, DDR2) offers a number of advantages over the SDRAMS. In this paper, research is emphasized on the DDR3 memory based controller architecture implementation and synthesis in hardware description language. The DDR3 RAM devices are used for low power, higher speed, and offer higher performance with double bandwidth as compare with the DDR2. DDR3 memory devices provide a reduction in power consumption due to low supply voltage 1.5 V as compare to the DDR2 memory devices which operates at 1.8 V due to power consumption is direct proportional to square of supply voltage. This paper represents the overall architecture implementation of Double Data Rate 3 (DDR3) memory controller in Xilinx 14.2 software and Modelsim 10.1 b. Keywords Double Data Rate (DDR), Synchronous Random Access Memory (SRAM), Very high sped integrated circuit hardware description language (VHDL) 1. INTRODUCTION DDR3 SDRAM [1] use a double data rate to achieve a high speed synchronous dynamic random access memory operations with eight register bank [2] . The DDR3 SDRAM architecture is based on prefetch architecture with the design of two data words over clock cycle. DDR3 runs at a frequency between 800MHz to 1600 MHz. DDR3 SDRAM [2] [3]is operating at the doubles clock frequency of DDR2 SDRAM according to the JEDC standards. The early type of random access memory (RAM) is not directly compatible with the DDR3 SDRAM because of the different signaling voltage, timings and other relevant factors. The main advantage of DDR3 SDRAM over DDR2 SDRAM [1] [9] is that it can transfer data rate at double rate which is eight times the speed of its internal memory array, and higher bandwidth. A 64 bit wide DDR3 memory module can achieve a transfer rate up to 64 times to the memory clock speed which is in (MB/s) with a transfer of two cycle per quadruple clock. The DDR3 standard provides a chip capacity of up to 8 gigabits. The controller is a device which work a bridge is uses to interface with JESD73-3C[6] [7] standard compliant SDRAM devices. Such types of memories like DDR1 SDRAM, DDR2 SDRAM, and DDR3 SDRAM and as well as Asynchronous memories are not supported. The main function of DDR3 memory controller SDRAM is used to program and to store a data. The data is transmitted along with the differential data strobe (DQS, DQS#) to capture a data at DDR3 SDRAM input receiver [12] . For WRITE DQS [4] aligned at a center with a data. The DDR3 SDRAM transmitted the read data and data strobes are edge aligned. Read and write accesses to the DDR3 SDRAM are burst-oriented.. Access started to selected locations. The ACTIVATION [5] [8] command is help to begin the access than further followed by the read or write command. To select the bank and row to be access the address bits registered coincident with the read and write command and the starting column locations for the burst access. At the end of the burst access an auto precharge function may be enabled to provide a self timed row precharge which is initiated at the end. The multibank architecture of DDR3 SDRAM is allowed to follow pipelining concept for throughput or higher bandwidth for concurrent operations. A self refresh mode is provided, along with a power-saving, power-down mode. 2. FUNCTION DESCRIPTION ON DDR2 MEMORY MODULES 2.1 Initialization The top module of DDR3 SDRAM controller[1] [13] is shown in figure 1. It is having user interface and external signals generated by different peripherals to communicate and provide service through controller. External signal are generated by the peripherals and depends on the demand of service by the external peripherals. 2013 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 549 Vol 04, Article 06124; July 2013 http://ijves.com International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 – 6556 Figure 1. Functional Module of DDR3 SDRAM controller DDR3 controller directly interfaced with internal module of the memory which is divided into different register banks and data storage in banks and registers depends on address signal. Write signal enable to write the data in different register of banks and data from particular register is read based on enabling read control signal. Controller also has read and write signal which are synchronized to DDR3 memory module with read and write control signal. Data read and write in the controller also depends on the clock frequency. We can read and write the data on same clock pulse or different clock pulse with some latency. Data transfer is possible from memory to controller, controller to memory, memory to memory, memory to I/O devices, I/O devices to memory. We can also interface external device to memory and provide the service to different peripherals at a time because pipelining structure is followed in the implementation of DDR3 controller. Reset is used to reset the contents of all register. It is synchronized with clock signal and the duration of clock signal is depending on the duty cycle of clock pulse. DRR2 memory is limited to the register banks, data size, burst length, prefetch operation [7]and data rate as shown in the table 1. Table 1 Comparison on DDR2 and DDR3 Features DDR DDR3 DDR3 No No Yes Reset 2.5 V 1.8 V 1.5 V Source voltage 2 bits 4 bits 8 bits Prefetch Slow Moderate Fast Speed 4 4 or 8 banks 8 banks Banks 2, 4, 8 bits 4, 8 bits 8 bits Burst length 200-400 Mbps 400-800 Mbps 800-1600 Mbps Data rata Bidirectional data strobe Bidirectional data strobe Bidirectional data strobe Source (single ended default) (single differential default (Differential default synchronization 2.2 Register definition DDR3 SDRAM basically consist of four mode resisters namely MR0, MR1, MR2 and MR3. Mode resisters are use to define various modes of operations of DDR3 SDRAM. A mode register is a program with mode resister sets (MRS) command when initialization process is taking place. Data of the mode resisters can be change or modify by executing the mode registers commands. All the variables have to program when MRS command is issued if the user wanted to modify only a subset of the mode register variables. When user wants to reprogram the mode resisters will not alter the content of the memory array, provided it is performed correctly. When the banks are in ideal state and in precharge state no burst are in progress in that condition MRS command can be issues. Mode Register 0 (MR0); The base register, MR0, is used to define various DDR3 SDRAM modes of operation. These definitions include the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, write recovery, and precharge power-down mode, as shown in Figure 2.The mode resistor MR0 is the base resistor which is use to define the various mode of operations of DDR3 SDRAM. Basically which is use to define the burst length, burst type by MR0 [1:0]. A given burst may be programmed to either a sequential or interleaved order by selecting MR0 [3] 0 or 1 order. The burst type is selected via MR0 [3] as shown in figure 1. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. The 8th bit is use to change the value of DLL reset. 2013 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 550 Vol 04, Article 06124; July 2013 http://ijves.com International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 – 6556 Figure 2 Mode Register 0 (MR0) definition [1] If the value of MR0 [8] is 1 then DLL is activated otherwise it will be in off state. If the DLL RESET function is initiated, CKE must be HIGH. MR0 [11:9] define the WRITE recovery time as shown in figure 1. The value of write recovery values 5,6,7,8,10 or 12 may be use by the programming MR0[11:9] The precharge PD bit applies only when precharge power-down mode is being used. The DLL is off during precharge power-down providing a lower standby current mode. When MR0[12] is set to 0, the DLL continues to run during precharge powerdown mode to enable a faster exit of precharge power-down mode when MR0[12] is set to 1. The MR0 [6:4] show the latency by CL as shown in figure 1. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to the differentiate value such as to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM does not support half-clock latencies. Mode Register 1 (MR1) Definition The MR1 register is shown in figure 3. It consists of some additional features and functions. In which MR1 [16, 13, 10, 8] are reserved for future use and must be programmed to 0. During write leveling, if MR1 [7] and MR1 [12] are 1, then all RTT, nom values are available for use. During write leveling, if MR1 [7] is a 1, but MR1 [12] is a 0, then only RTT, nom write values are available for use. When the LOAD MODE command is applied then the DLL may be enabled or disabled by programming MR1 [0] as shown in figure 2. Figure 3 Mode Register 1` (MR1) definition [2] The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and should enable by resetting the DLL using the appropriate LOAD MODE command. The MR1 [12] define the output enable functions shown in figure 2. All output (DQ, DQS, DQS#) function when in the normal mode of operation when enable MR1 [12] = 0. When MR1 [12] = 1 (DQ and DQS, DQS#) are tri-stated. Configuration Termination data strobe (TDQS) is a feature of the DDR3 SDRAM which provides termination resistance. 2013 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 551 Vol 04, Article 06124; July 2013 http://ijves.com International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 – 6556 TDQS is not supported in X4 or X16 configurations. The TQDS is operated by the resister MR1 [11]. The DM function is not supported, when the TDQS function is enabled via the mode register. When the TDQS function is disabled, the DM function is provided. The TDQS function is available in the X 8 DDR3 SDRAM configuration only and it is disabled when the mode register for the X 4 and X16 configurations. The MR1 [7] enable the WRITE LEVELING function as shown in Figure 2. Write leveling is used (during initialization) to deskew the DQS For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. Figure 4: READ Latency (AL = 5, CL = 6) [3] In DDR3 SDRAM for sustainable bandwidth posted CAS ADDATIVE latency which is supported to make the command and data bus efficient. MR1[4,3] show the value of AL as shown in figure 3 which enable the user the DDR3 SDRAM with AL =0, CL – 1, CL-2. Mode Register 2 (MR2) .There are some other control functions and features which are not available in the other more resistors is provided in the MR2 mode resistor like CAS WRITE latency(SWL), AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), which are shown in the figure 5. The reprogramming of MR2 will not alter the memory contents. All the banks are in ideal when the MR2 resister is loaded and data burst are in progress. Figure 5 Mode Register 2 (MR2) definition [2] MR2 [5:3] define the CWL is the delay, in the clock cycles which is from the releasing of the internal write to the latching of the first data in. As shown in figure 6 correspondent to the operating clock frequency CWL have to be set correctly the total WRITE latency is the sum of CWL and AL as shown in figure 6 . Figure 6 CAS Write Latency [1] 2013 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 552 Vol 04, Article 06124; July 2013 International Journal of VLSI and Embedded Systems-IJVES http://ijves.com ISSN: 2249 – 6556 To disable/enable the ASR (Auto Self Refresh) function Mode register MR2 [6] is used. Mode register MR2 [7] is used to disable/enable the SRT (Self Refresh temperature) function. Mode Register 3 (MR3) The MR3 register is also called as a multiple purpose resister (MPR) which controls the additional functions and features which are not available in the other mode resisters as shown in figure 7. The LOAD MODE COMMAND is use to program the MR3 and it will remain same until the stored information is reprogrammed or until the device loses power. The MR3 register reprogramming will not alter the contents of the memory array,. When no data bursts are in progress then the MR3 register must be loaded and when all banks are idle. When MPR control is set for normal DRAM operation, MR3 [1, 0] will be ignored. Bit 2 is use as a master bit to enable or disable access the MRP (MULTIPL PURPOSE RESISTOR) which is use to output predefined system timing calibration bit sequence. The MPR access is disable when MR3 [2] is 0 than DRAM operate in the normal mode. When MR3[2] is 1 than no longer output normal read data but output MPR data define by MR3[0 1] as shown in figure 7. Figure 7 Mode Register 3 (MR3) Definition [1] Table 2 commands of DDR3 controller operations [3] Function Symbol MODE RESISTER SET REFRESH SELF REFRESH ENRY SELF REFRESH EXIT SINGLE BANK PRECHARGE PRECHARGE ALL BANKS BANK ACTIVE WRITE BL8MR S, BC4MR S BC40TF WRITE WITH AUTO PRECHAR GE READ BL8OT F BL8MR S BC4OT F BL8OT F BL8MR S Nex t cycl e H H L CS # RA S# CAS # WE # MRS REF SRE Prev cycl e H H H An L H H Ban k [2:0 ] BA V V L L L L L L L L L SRX L H H V V V PRE H H L L H PREA H H L L ACT WR H H H H L L WRS4 H H WRS8 H WRAP WRAP S4 WRAP S8 RD A1 2 A1 0 A1 1 [9:0 ] opcode V V V V V V V V V V V V V L BA V V L V H L V V L V L H H L H L BA BA Row Address(RA) RF V L CA U L H L H BA H L H L L BA H H L H L L BA H H L H L L BA H H L H L L BA H H L H L H BA RF U RF U RF U RF U RF U RF U L L CA H L CA V H CA L H CA H H CA V L CA 2013 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 553 Vol 04, Article 06124; July 2013 International Journal of VLSI and Embedded Systems-IJVES http://ijves.com BC4MR S BC4OT F READ BL8OT WITH F AUTO BL8MR PECHARG S E BC4MR S BC4OT F BL8OT F NO OPERATION DEVICE DESELECT POWER DOWN ENTRY POWER DOWN EXIT ZQ CALIBRATION LONG ZQ CALIBRATION ISSN: 2249 – 6556 RDS4 H H L H L H BA RF U RF U RF U L L CA RDS8 H H L H L H BA H L CA RDAP H H L H L H BA V H CA RDAPS 4 RDAPS 8 NOP DES PDE H H L H L H BA L H CA H H CA V X V RF U RF U V X V H H L H L H BA H H H H H L PDX L H ZQCL H H H L H L H L H X H V H V H H X H V H V H H X H V H V L V X V V X V V X V V V V V V X X X H X ZQCS H H L H H L X X X L X Table 2 shows the commands issued by the DDR3 SDRAM controller. Commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock. The MSB of BA, RA, and CA are device, density and configuration-dependent. In the table L represents Low, V- valid, H- High and X is forcing unknown. 3. BLOCK DIAGRAM OF DDR3 SDRAM Figure 8 DDR3 Operational Module First DDR3 SDRAM should be initialized as we have discussed in the definitions of mode registers. There are two FSMs (Finite State Machines) one is for initialization and other for command FSM which controller block consists. Read, write and refresh is handled by the command FSM. When the initialization is completed then the DDR3 SDRAM is ready for the write continuous with the refresh process. The signals are generated corresponding to the state when any of state are met a sequence. When the DDR3 initialize all the row are in closed status. The command decode logic block as shown in figure 8 receives the user commands from the local interface and command application logic block receives a commands and decode them to generate the sequence of internal memory commands depending on the current 2013 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 554 Vol 04, Article 06124; July 2013 http://ijves.com International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 – 6556 command and update row and banks of DDR3 SDRAM . The bank management is to open and close status of every bank and stores the row address of every bank which is open. For throughput the controller design implements a command pipeline. The next command is in the queue is decoded. The current command is present at the memory interface. The DDR3 SDRAM controllers access the memory to read the addressed data when the read command is accepted. The data bring back to the local user interface, when the read data is available on the local user interface. To indicate the valid read is on the read data bus the memory controller is assert the read data valid signal. 4. SIMULATION RESULTS The snapshot shown in figure 9 is taken from the Modelsim 10.1b software which shows the 8-bit data transfer among. Register bank selection is based on bank address of 3 bits. To address 8 banks there is an address of 3 bits bank [2:0]. Memory address is of 6 bits address [5:0]. The selection logic is shown in table 3. Each bank is having eight register each 8 bits wide. Reading and writing of data depends on read and write control signals which are synchronized with controller unit. Data_in [7:0] is the input data and data_out [7:0] is out data of controller as well as DDR3 memory module. Each bank is having 8 registers which are addressed by address [5:0] as shown in table 4. Simulation steps are listed below. Step input 1: reset =1, apply clock pulse directly then run. Step input 2: reset =0, same clk is used for synchronization. Select the address of bank [2:0] and register [5:0]. Force the eight bit value to any inlet. Step input 3: write_en = 0 and read_en =1 and run. Table 3 Bank selection logic Bank [2:0] Bank Selection 000 Register bank 1 001 Register bank 2 010 Register bank 3 011 Register bank 4 100 Register bank 5 101 Register bank 6 110 Register bank 7 111 Register bank 8 Table 4 Register selection based on bank logic Bank [2:0] Bank Selection Address [4:0] Register Selection 000 Register bank 1 000000 Register 0 : : 000111 Register 7 001 Register bank 2 001000 Register 8 : : 001111 Register 15 010 Register bank 3 010000 Register 16 : : 010111 Register 23 011 Register bank 4 011000 Register 24 : : 011111 Register 31 100 Register bank 5 100000 Register 32 : : 100111 Register 39 101 Register bank 6 101000 Register 40 : : 101111 Register 47 110 Register bank 7 110000 Register 48 : : 110111 Register 55 111 Register bank 8 111000 Register 56 : : 111111 Register 63 2013 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 555 Vol 04, Article 06124; July 2013 http://ijves.com Figure 10. Modelsim output of DDR3 memory Figure 12.RTL view of DDR3 memory International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 – 6556 Figure 11. Modelsim output of DDR3 memory Figure 11. Modelsim output of DDR3 memory 5. Device Utilization and Timing Report Device utilization summary is the report of used device hardware in the implementation of the chip such as RAM, ROM, slices, flip flops etc [25]. Synthesis report shows the complete details of device utilization as total memory utilization. Timing details provides the information of net delay, minimum period, minimum input arrival time before clock and maximum output required time after clock. Table 3 shows the hardware utilization for DDR3 memory module and table 4 shows the hardware required for DDR3 memory controller. Device Used Available Utilization 520 2448 21% Number of Slices 256 4896 5% Number of Slice Flip Flops 1038 4896 21% Number of 4 input LUTs 135 158 85 % Number of bonded IOBs 1 24 4% Number of GCLKs Speed Grade: -5 Minimum period: 2.943ns (Maximum Frequency: 339.841MHz) Minimum input arrival time before clock: 7.367ns Maximum output required time after clock: 4.207ns Maximum combinational path delay: 5.457ns Total Memory usage 126580 kB Selected Device: 3s250epq208-5, it is the targeted device for FPGA. Device Used Available 52 2448 Number of Slices 17 4896 Number of Slice Flip Flops 99 4896 Number of 4 input LUTs 49 158 Number of bonded IOBs 1 24 Number of GCLKs Speed Grade: -5 Minimum period: 2.943ns (Maximum Frequency: 339.841MHz) Utilization 2% 0% 2% 31% 0% 2013 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 556 Vol 04, Article 06124; July 2013 http://ijves.com International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 – 6556 Minimum input arrival time before clock: 8.070ns Maximum output required time after clock: 10.092ns Maximum combinational path delay: 12.110ns Total memory usage is 126580 kilobytes CONCLUSION The hardware chip of the DDR3 SDRAM controller is designed and modeled in Xilinx 14.2 software and functionality checked in Modelsim 10.1 b software. The DDR3 memory is designed of 512 MB. Device utilization summary results Total memory usage is 126580 kilobytes. We have tested the DDR3 controller for different test cases and data transfer from memory to memory, memory to controller, controller to memory and I/O to memory. In future we can enhance the size for memory with the help of register bank , can be used for dedicated controller. REFERENCES [1]. DDR3 SDRAM Specification (JESD79-3A), JEDEC Standard, JEDEC Solid State Technology Association, Sept. 2007. [2]. “Double Data Rate (DDR3) IP Core User’s Guide”, Lattice Semiconductors Corporation, Dec.2010. [3]. http://www.xilinx.com [4]. “High-Performance DDR3 SDRAM Interface in Virtex-5 Devices”, Xilinx, XAPP867 (v1.0), Sept24, 2007. [5]. J. Bhasker “A VHDL Primer”, 3rd Edition ,Pearson Education. [6].www.altera.com/literature/ug/ug_altmemphy.pdf, External DDR Memory PHY Interface Megafunction User Guide (ALTMEMPHY), accessed on 23 Feb. 2009 [7]. Micron 1GB DDR3 SDRAM , Micron Technology Inc. , 2006. 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Biography Ajay is B.Tech in Electronics & communication from Graphic Era Institute of technology, Dehrradun in 2009. Now is M.Tech scholar in VLSI Design Uttarkhand Technical University Dehradun India. His Area of interest include VLSI Design, VHDL & FPGA based design and Low power VLSI. Adesh Kumar is B.Tech in Electronics & Communication Engineering from Veera College of Engineering, Bijnor (UPTU, Lucknow) India in 2006. M.Tech in Embedded Systems Technology from SRM University, Chennai in 2008. Currently he is working as an Assistant Professor with the Department of Electrical, Electronics and Instrumentation Engineering in “University of Petroleum & Energy Studies” , Dehradun India. He has also worked as Senior Engineer in TATA ELXSI LIMITED Bangalore and faculty member in ICFAI University, Dehradun. His are of interest are VLSI Design, Microprocessors and Embedded System. He has published 20 research papers in international journal and conferences. Dhirendra Singh Gangwar is Assistant Professor, Faculty of Technology, Uttarakhand Technical University, Dehradun India. He has published many research papers in international conference and journals. His area of interest includes VLSI Design, Microwave Engineering. 2013 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc.,