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FAKULTI KEJURUTERAAN ELEKTRIK
Fakulti:
Semakan Tarikh Keluaran Pindaan Terakhir No. Prosedur
ECAD PB Lab Kod Matapelajaran : SEL 4722
Nama Matapelajaran:
:1 : 2013 : 2013 : PK-UTM-FKE-(0)-10
SEL SEL 472 4722 FAKULTI FAKULTI KEJURUTERAAN ELEKTRIK UNIVERSITI TEKNOLOGI MALAYSIA KAMPUS SKUDAI JOHOR
ECAD PROBLEM BASED LAB Design of a Cyclic Redundancy Check (CRC) Calculator
Disediakan oleh Nama Tandatangan Cop
: : Dr. Rabia Bakhteri : :
Disahkan oleh Nama Tandatangan Cop
: Ketua Jabatan : Dr. Nasir Shaikh Hussein : :
Tarikh
: 2 September 2013
Tarikh
: 12 September 2013
Introduction:
An embedded system is a mini-computer that consists of an embedded processor, a system bus, memory, I/O interface unit, and dedicated hardware blocks such as Digital Signal Processors (DSP), accelerators, timers, Phase Locked Loop (PLL) etc. and their interconnections. General purpose computers are designed to perform a variety of tasks on a fixed set of hardware by using the software called operating system to control and run the tasks. On the other hand, embedded systems are usually designed to perform one, specific task, usually in real time and are part of a larger electrical or mechanical machine. Examples of embedded systems range from mobile phones and digital cameras to cars with digital controls and smart home systems.
Embedded System
Memory UART
Embedded CPU
General Purpose IO
Software Module
Ethernet DSP Processor Others (PLL, Timer etc)
HW Module System Bus
Fig. 1: Embedded System Architecture
In this lab, we will build a simple embedded system prototype meant to perform one, specific task on a FieldProgrammable Gate Array (FPGA) board.
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There are a few basic steps required to design any digital system.
Step 1: Design Specification In this step, we must figure out the design and functionality of the system. Identify the input and output of the system. What are the computational blocks required by the design and how are they interconnected to each other and the input/output ports. To complete your understanding of the design, you should manually perform all the steps to transform the input into output. This is called mathematical modeling for systems where the output [f(x)] is a function of the input values [x,y…]. To complete this step, select suitable input values for your digital system, perform the mathematical calculation manually and get the expected output for your design. This output value will be used in the next steps to verify that your system is working correctly by comparing it to the output produced by the system when given the same input values.
Step 2: Software Design Before the hardware digital system can be designed, it is wise to design it in software. This refers to using high-level programming languages such as C or tools such as MATLAB to create the software version of the digital system. In this lab, you will use C language (compiled on any available C compiler software such as Visual Studio) to create the software version of your digital system. By providing the same input values as in Step 1, check to see if your software can give the right output.
Step 3: Hardware Design Next, we use RTL Design Methodology to create the hardware version of the digital system. A digital system usually consists of a Control Unit and a Datapath Unit and functions as a Finite State Machine. The Control Unit supplies the right control signals according to the current state and the Datapath Unit performs the computations which are enabled by the Control Unit. The hardware design is compiled and simulated using the Altera Quartus II software. The correctness of the design is verified by using waveform simulation and comparing the output signal with the expected output that was obtained in Step 1.
Step 4: Hardware Implementation The last step is implementing the design on the FPGA board. The hardware code is synthesized and programmed on the FPGA board. An additional hardware module is added to activate the interfaces such as LEDs and Seven Segment Displays on the FPGA board (The ECAD Lab Tutorial can be downloaded and used for guidance). The performance of the digital system is measured in logic cost and computation cycle count. The software version of the digital system is also downloaded and run on the FPGA’s processor as ‘embedded software’ to compare the timing with the hardware version of the same digital system.
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Fig. 2: Digital System Design – Process Flow
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Problem Pack 2: Design of a Cyclic Redundancy Check (CRC) Calculator Data communication is the process of sending data over a channel such as a transmission line or in packets over a network such as the internet. Checksum Calculators are error detecting algorithms used to ensure that data is not tampered, changed or lost during transmission. CRC is a common type of checksum algorithm that processes a string of data (message) in a cyclic pattern and produces a 16 bit code also known as the data’s ‘CRC code’. This 16-bit value is appended to the data before it is sent. When the data is received on the other end of the transmission line/network, the CRC calculator is used to calculate a new CRC value. Then the new CRC value is compared to the sent ‘CRC code’. If both values are the same, the data (message) is proven to be correct and error-free. The block diagram and pseudo code for the CRC16-CCITT algorithm are given below:
Fig. 3: CRC Checksum Calculator
CRC Pseudo Code: POLYNOMIAL = 0x1021 DATA = Message; if this is the continuation of CRC computation from previous message CRC = CRCi else CRC = 0 from (LSB of message) to (MSB of message) if ( (MSB of Data) xor (MSB of CRC) ) CRC = ( (CRC<<1) ^ POLY ); else CRC = CRC << 1; DATA = DATA<<1; return CRC
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Project tasks: Week 1: 1) Work out a mathematical calculation of the proposed module by hand by providing suitable input values. 2) Create the software module for the CRC calculator using C language. 3) Draw the functional block diagram for the hardware module of the CRC calculator.
Week 2: 1) Design the hardware module for the CRC calculator using Verilog language. a) The Control Unit uses the Finite State Machine concept to send control signals b) The Datapath Unit receives control signals and performs computation operations 2) Verify the correctness of the hardware module by checking the waveform of the timing simulation 3) Compare the performance between using resource-constrained versus unconstrained hardware module.
Week 3: 1) Download the hardware design of the CRC calculator onto the FPGA board. 2) Create an interface module in Verilog to connect the CRC module to IO peripherals. 3) Download the software version of the CRC module and run as embedded software on the FPGA. 4) Compare the timing performance of the software with the hardware version
Week 4: 1) Present all your results in a presentation with demonstration session 2) Create a written report detailing your Lab work, to be submitted one week later.
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