Transcript
OPA602
®
High-Speed Precision Difet ® OPERATIONAL AMPLIFIER FEATURES
APPLICATIONS
● ● ● ● ● ●
● ● ● ● ● ●
WIDE BANDWIDTH: 6.5MHz HIGH SLEW RATE: 35V/µs LOW OFFSET: ±250µV max LOW BIAS CURRENT: ±1pA max FAST SETTLING TIME: 1µs to 0.01% UNITY-GAIN STABLE
PRECISION INSTRUMENTATION OPTOELECTRONICS SONAR, ULTRASOUND PROFESSIONAL AUDIO EQUIPMENT MEDICAL EQUIPMENT DATA CONVERSION
DESCRIPTION
+V S
The OPA602 is a precision, wide bandwidth FET operational amplifier. Monolithic Difet (dielectrically isolated FET) construction provides an unusual combination of high speed and accuracy. Its wide-bandwidth design minimizes dynamic errors. High slew rate and fast settling time allow accurate signal processing in pulse and data conversion applications. Wide bandwidth and low distortion minimize AC errors. All specifications are rated with a 1kΩ resistor in parallel with 500pF load. The OPA602 is unity-gain stable and easily drives capacitive loads up to 1500pF.
(7)
–In (2)
+In (3)
Cascode
Output (6)
Laser-trimmed input circuitry provides offset voltage and drift performance normally associated with precision bipolar op amps. Difet construction achieves extremely low input bias currents (1pA max) without compromising input voltage noise. The OPA602’s unique input cascode circuitry maintains low input bias current and precise input characteristics over its full input common-mode voltage range.
–V S (4) (1)
(5)
Difet® Burr-Brown Corp.
International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • ©
SBOS155
1987 Burr-Brown Corporation
• Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-753E
Printed in U.S.A. August, 1995
SPECIFICATIONS ELECTRICAL At VS = ±15VDC and TA = +25°C unless otherwise noted. OPA602AM/AP/AU PARAMETER
CONDITIONS
MIN
TYP
INPUT NOISE Voltage: fO = 10Hz fO = 100Hz fO = 1kHz fO = 10kHz fB = 10Hz to 10kHz fB = 0.1Hz to 10Hz Current: fB = 0.1Hz to 10Hz fO= 0.1Hz to 20kHz OFFSET VOLTAGE Input Offset Voltage: M Package P Package U Package Over Specified Temperature M Package P, U Packages Average Drift Supply Rejection BIAS CURRENT Input Bias Current Over Specified Temperature SM Grade OFFSET CURRENT Input Offset Current Over Specified Temperature SM Grade
MAX
OPA602BM/SM/BP MIN
* * * * * * * *
±300 1 1
VCM = 0VDC
TA = TMIN to TMAX ±VS = 12V to 18V
70
±550 ±1.5 * *
TYP
MAX
OPA602CM MIN
23 19 13 12 1.4 0.95 12 0.6
±1000 2 3
±15 80
TYP
MAX
* * * * * * * *
UNITS nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fAp-p fA/√Hz
±150 0.5
±500 1
±100
±250
µV mV mV
±250 ±0.75 ±3 100
±1000 ±1.5 ±5
±200
±500
* *
±2
µV mV µV/°C dB
86
VCM = 0VDC
±2 ±20
±10 ±500
±1 ±20 ±200
±2 ±200 ±2000
±0.5 ±10
±1 ±100
pA pA pA
VCM = 0VDC
1 20
10 500
0.5 20 200
2 200 1000
0.5 10
1 100
pA pA pA
INPUT IMPEDANCE Differential Common-Mode
1013 || 1 1014 || 3
* *
INPUT VOLTAGE RANGE Common-Mode Input Range
*
*
±10.2
* *
Ω || pF Ω || pF
Common-Mode Rejection
VIN = ±10VDC
75
*
88
+13, –11 100
OPEN-LOOP GAIN, DC Open-Loop Voltage Gain
RL ≥ 1kΩ
75
*
88
100
92
*
dB
Gain = 100 20Vp-p, RL = 1kΩ VO = ±10V, RL = 1kΩ Gain = –1, RL = 1kΩ CL = 500pF, 10V Step
3.5
4 24
6.5 570 35 0.6 1.0
5
20
* * * * *
28
* * * * *
MHz kHz V/µs µs µs
RL = 1kΩ
±11
*
±11.5
*
*
V
VO = ±10VDC 1MHz, Open Loop Gain = +1
*
* * * *
±15
*
* * * *
mA Ω pF mA
*
VDC
FREQUENCY RESPONSE Gain Bandwidth Full Power Response Slew Rate Settling Time: 0.1% 0.01% RATED OUTPUT Voltage Output Current Output Output Resistance Load Capacitance Stability Short Circuit Current POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent Over Specified Temperature TEMPERATURE RANGE Specification SM Grade Operating: M Package P, U Packages Storage: M Package P, U Packages θ JA
±25
* IO = 0mADC
* *
* * *
±5
–25 –55 –55 –25 –65 –40
Ambient Temperature
*
*
Ambient Temperature
* –25 * –40
* +85 * +125
Ambient Temperature
*
®
2
*
V
92
*
dB
*
±15
*
* Same specifications as OPA602BM.
OPA602
±30
+12.9, –13.8 ±20 80 1500 ±50
*
3 3.5
200
±18 4 4.5
*
+85 +125 +125 +85 +150 +125
* * *
VDC mA mA
*
*
*
*
*
*
°C °C °C °C °C °C °C/W
* *
*
PACKAGE INFORMATION
ABSOLUTE MAXIMUM RATINGS Supply Voltage .............................................................................. ±18VDC Internal Power Dissipation (TJ ≤ +175°C) .................................... 1000mW Differential Input Voltage ............................................................... Total VS Input Voltage Range ............................................................................ ±VS Storage Temperature Range M Package .................................................................. –65°C to +150°C P and U Packages ....................................................... –40°C to +125°C Operating Temperature Range M Package .................................................................. –55°C to +125°C P and U Packages ........................................................ –25°C to + 85°C Lead Temperature M and P Packages (soldering, 10s) ............................................ +300°C U Package, SOIC (3s) ................................................................ +260°C Output Short Circuit to Ground (+25°C) ................................... Continuous Junction Temperature .................................................................... +175°C
MODEL OPA602AM OPA602BM OPA602CM OPA602SM OPA602AP OPA602BP OPA602AU
PACKAGE
PACKAGE DRAWING NUMBER(1)
TO-99 TO-99 TO-99 TO-99 Plastic DIP Plastic DIP Plastic SOIC
001 001 001 001 006 006 182
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
ORDERING INFORMATION MODEL OPA602AM OPA602BM OPA602CM OPA602SM OPA602AP OPA602BP OPA602AU
PACKAGE
TEMPERATURE RANGE
OFFSET VOLTAGE MAX (µV) AT 25°C
TO-99 TO-99 TO-99 TO-99 Plastic DIP Plastic DIP Plastic SOIC
–25 to +85°C –25 to +85°C –25 to +85°C –55 to +125°C –25 to +85°C –25 to +85°C –25 to +85°C
±1000 ±500 ±250 ±500 ±2000 ±1000 ±3000
PIN CONFIGURATIONS Top View — DIP
Top View — TO-99 NC 8 Offset Trim 1
–In
7
2
Offset Trim
1
8
NC
–In
2
7
+VS
+In
3
6
Output
–VS
4
5
Offset Trim
+VS
6 Output
3
5
+In
Offset Trim 4 –VS
Case Connected to +VS.
Top View — SOIC Offset Trim
1
8
NC
–In
2
7
+VS
+In
3
6
Output
–VS
4
5
Offset Trim
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ®
3
OPA602
DICE INFORMATION
7
1 2
PAD
FUNCTION
1 2 3 4 5 6 7
Offset Trim –In +In –VS Offset Trim Output +VS
Substrate Bias: –VS NC: No Connection.
MECHANICAL INFORMATION
3
Die Size Die Thickness Min. Pad Size
6 4
MILS (0.001")
MILLIMETERS
63 x 58 ±5 20 ±3 4x4
1.60 x 1.47 ±0.13 0.51 ±0.08 0.10 x 0.10
Backing Transistor Count
5
None 36
OPA602 DIE TOPOGRAPHY
TYPICAL PERFORMANCE CURVES TA = +25°C, VS = ±15VDC unless otherwise noted.
INPUT CURRENT NOISE SPECTRAL DENSITY
INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k
Voltage Noise (nV/√Hz)
Current Noise (fA/√Hz)
100
10
1
0.1
100
10
1 1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
POWER SUPPLY REJECTION AND COMMON-MODE REJECTION vs TEMPERATURE
TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY AT 1kHz vs SOURCE RESISTANCE 1k
110 Voltage Noise, EO (nV/√Hz)
CMR and PSR (dB)
EO
105
CMR 100 PSR 95
RS
100
OPA602 + Resistor 10
Resistor Noise Only 1
90 –75
–50
–25
0
25
50
75
100
100
125
®
OPA602
1k
10k
100k
1M
Source Resistance ( Ω)
Temperature (°C)
4
10M
100M
TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±15VDC unless otherwise noted. COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE
OPEN-LOOP FREQUENCY RESPONSE 140 RL = 1kΩ
Common-Mode Rejection (dB)
120
–45
CL = 100pF Voltage Gain (dB)
110
100
90
100 φ
80
–90
60 –135
40 AOL
80
Phase Shift (Degrees)
120
20 0
70 –15
–10
–5
0
+5
+10
+15
–180 10
1
100
Common-Mode Voltage (V)
1k
10k
100k
1M
10M
Frequency (Hz)
GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE
GAIN BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE 37
10
38
8
6
33 Slew Rate
4
31
2
29
7
36 GBW
6
34
Slew Rate (V/µs)
35
GBW
Gain Bandwidth (MHz)
8
Slew Rate (V/µs)
Gain Bandwidth (MHz)
AV = –1
Slew Rate –75
–50
–25
0
25
50
75
100
5
125
32 0
5
Ambient Temperature (°C)
15
20
Supply Voltage (±VCC)
MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY
OPEN-LOOP GAIN vs TEMPERATURE 120
30
Output Voltage (V p-p)
110
Voltage Gain (dB)
10
100
90
20
10
RL = 1kΩ 80
0 –75
–50
–25
0
25
50
75
100
125
10k
Ambient Temperature (°C)
100k
1M
10M
Frequency (Hz)
®
5
OPA602
TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±15VDC unless otherwise noted.
LARGE SIGNAL TRANSIENT RESPONSE
SMALL SIGNAL TRANSIENT RESPONSE
10
Output Voltage (mV)
Output Voltage (V)
110
0
–10
100 50 0 –50 –100 –150
0
1
2
3
4
5
0
1
Time (µs)
SETTLING TIME vs CLOSED-LOOP GAIN
SUPPLY CURRENT vs TEMPERATURE
5
3.5
Supply Current (mA)
4
Settling Time (µs)
2
Time (µs)
3 0.01%
2
0.1%
1
3.25
3.0
2.75
RL = 1kΩ CL = 100pF
2.5
0 –1
–10
–100
–75
–1k
–50
–25
0
50
75
Ambient Temperature (°C)
OPEN-LOOP GAIN vs SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION vs FREQUENCY
1
104
40.2kΩ
THD + Noise (%rms)
402Ω
Voltage Gain
25
Closed-Loop Gain (V/V)
100
96
100
125
AV = +101V/V 6.5Vrms
0.1
1kΩ
A V = +101V/V 0.01 A V = +1V/V
92
0.001 5
0
10
15
20
0.1
Supply Voltage (±VCC)
10
100 Frequency (Hz)
®
OPA602
1
6
1k
10k
100k
TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±15VDC unless otherwise noted.
BIAS AND OFFSET CURRENT vs TEMPERATURE
BIAS AND OFFSET CURRENT vs INPUT COMMON MODE VOLTAGE
100
100
10
10
1
1 Offset Current 0.1
0.1
1
0.1
0.1 –50
–25
0
25
50
75
100
0.01
0.01
125
–15
–10
–5
0
5
10
Ambient Temperature (°C)
Common-Mode Voltage (V)
POWER SUPPLY REJECTION vs FREQUENCY
COMMON-MODE REJECTION vs FREQUENCY
140
140
120
120
Common-Mode Rejection (dB)
Power Supply Rejection (dB)
Bias Current 1
Offset Current (pA)
1nA Bias Current (pA)
1nA
10
10
Offset Current (pA)
10nA
Bias Current (pA)
10nA
100 80
–
+
60 40 20 0
15
100 80 60 40 20 0
1
10
100
1k
10k
100k
1M
10M
1
Frequency (Hz)
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
APPLICATIONS INFORMATION
INPUT BIAS CURRENT GUARDING Leakage currents across printed circuit boards can easily exceed the input bias current of the OPA602. A circuit board “guard” pattern (Figure 1) is an effective solution to difficult leakage problems. This guard pattern must be repeated on all layers of a multilayer board. By surrounding critical high impedance input circuitry with a low impedance circuit connection at the same potential, leakage currents will flow harmlessly to the low impedance node.
Unity-gain stability with good phase margin and excellent output drive characteristics bring freedom from the subtle problems associated with other high speed amplifiers. But with any high speed, wide bandwidth circuitry, careful circuit layout will ensure best performance. Make short, direct interconnections and avoid stray wiring capacitance— especially at the inverting input pin. Power supplies should be bypassed with good high frequency capacitors positioned close to the op amp pins. In most cases 0.1µF ceramic capacitors are adequate. Applications with heavier loads and fast transient waveforms may benefit from use of additional 1.0µF tantalum bypass capacitors.
Input bias current may also be degraded by improper handling or cleaning. Contamination from handling parts and circuit boards may be cleaned with appropriate solvents and deionized water. Each rinsing operation should be followed by a 30-minute bake at +85°C.
®
7
OPA602
Noninverting
Buffer
2
2 OPA602
6
Out
OPA602
3
In
6
Out
3
In
Inverting
TO-99 Bottom View
In 4
3
2 OPA602
6
5 Out
3
2
6 7 1
Board Layout for Input Guarding: Guard top and bottom of board. Alternate—use Teflon® standoff for sensitive input pins. Teflon® E.I. Du Pont de Nemours & Co.
8
To Guard Drive
FIGURE 1. Connection of Input Guard.
APPLICATION CIRCUITS MSB
+VS
B1 •
7
•
•
•
•
•
•
•
•
• B12
2 3
OPA602
6
16
1
5 4
±10mV Typical Trim Range
17
4 5 6 7 8 9 10 11 12 13 14 15 +15V DAC7541A
C1 15pF
1
Out 1
VREFERENCE
VOUT
Out 2
2
3
(1)
–VS
18
RF
OPA602
100kΩ
NOTE: (1) 10kΩ to 1M Ω Trim Potentiometer (100kΩ Recommended)
Single-Point Ground –VCC
FIGURE 2. Offset Voltage Trim.
(
VOUT = –VREF
B1 2
B2 + 4
B3 + 8
B12 + ••• + 4096
–10V ≤ VREF ≤ +10V 0 ≤ VOUT ≤ –
4095 4096
VREF
Where: BN = 1 if the BN digital input is high BN = 0 if the BN digital input is low
FIGURE 3. Voltage Output D/A Converter.
®
OPA602
8
)
(2) HP 5082-2835 2kΩ
2kΩ
50Ω +15V
47pF 1µF High Quality Pulse Generator
+
2kΩ 510Ω
+15V
1µF 1µF Tantalum
Pulse in ±5V
+
2kΩ
+ 1/2 2N5564
51Ω
Output
OPA602
Error Out ±0.5mV (0.01%)
1µF Tantalum + CL 500pF –15V
1/2 2N5564 1µF + 510Ω 1µF +
–15V
FIGURE 4. Settling Time and Slew Rate Test Circuit.
®
9
OPA602
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
