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Dip Ipm Vers.2, Application Note

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November 2018
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MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Chapter 1 DIP-IPM Product Outlines 1.1 DIP-IPM Series and Typical Applications 1.2 Functions and Features 1.2.1 Functions Outlines 1.2.2 Product Features Chapter 2 Electrical Characteristics 2.1 Static Characteristics 2.2 Dynamic Characteristics Chapter 3 Package 3.1 Package Outlines Drawing 3.2 List of Input / Output Terminals 3.2.1 3.2.2 3.2.3 3.2.4 Input / Output Terminals Description Structure and Detailed Description of Input / Output Terminals Description of Drive and Protection Functions Structure of Control Input Terminals and Application Examples 3.3 Installation Guidelines (Flatness / Mounting Strength / Screw Type /Grease) Chapter 4 Applications 4.1 System Connection Diagram 4.2 Mono Drive-Voltage-Supply Scheme 4.2.1 Initial charging 4.2.2 Charging and Discharging of Bootstrap Capacitor During Inverter Operation 4.3 Interface Circuit Examples and Guidelines 4.3.1 Direct Input (without Opto-Coupler) Interface Example 4.3.2 Interface Example when a Fast Opto-Coupler is used 4.3.3 Interface Example when a Slow Opto-Coupler is used 4.4 Short Circuit Protective Function 4.4.1 Timing Charts of Short Circuit Protection 4.4.2 Selecting the Current Sensing Shunt Resistor Value 4.4.3 SOA of the DIP-IPM (For short-circuit switching) 4.4.4 Filter Circuit Setting (RC Time Constant) for Short-circuit Operation 4.5 Guidelines for Control Supply 4.5.1 Timing Charts of Under-voltage Protection 4.5.2 Control Supply Starting-up and Shutting-down Sequence 4.5.3 Other Guidelines 4.6 Power Loss and Heat Dissipation Design 4.6.1 Power Loss Calculation (Example) 4.6.2 Temperature Rise Considerations and Calculation Example 4.7 Noise Withstand Capability 4.7.1 Example of Measurement Circuits 4.7.2 Countermeasures and Precautions Chapter 5 Additional Guidelines 5.1 Packaging Specification 5.2 Handling Notice Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Chapter1 DIP-IPM Product Outlines 1.1. DIP-IPM Series and Typical Applications Table 1. The DIP-IPM Series and Some Typical Applications Type Name IGBT Ratings (IC /VCES) PWM Frequency (Typ,) Motor Ratings Typical Applications PS21202 PS21212 PS21213 PS21204 PS21214 PS21205 5A/600V 5A/600V 10A/600V 15A/600V 15A/600V 20A/600V 5kHz 15kHz 15kHz 5kHz 15kHz 5kHz 0.2kW/AC220V 0.2kW/AC220V 0.4kW/AC220V 0.75kW/AC220V 0.75kW/AC220V 1.5kW/AC220V PS21402 PS21412 PS21413 PS21404 PS21414 PS21405 5A/600V 5A/600V 10A/600V 15A/600V 15A/600V 20A/600V 5kHz 15kHz 15kHz 5kHz 15kHz 5kHz 0.2kW/AC220V 0.2kW/AC220V 0.4kW/AC220V 0.75kW/AC220V 0.75kW/AC220V 1.5kW/AC220V Refrigerator etc. Refrigerator etc. Washing machine etc. Air conditioner etc. Washing machine etc. Air conditioner, sewing machine etc. Refrigerator etc. Refrigerator etc. Washing machine etc. Air conditioner etc. Washing machine etc. Air conditioner, sewing machine etc. Note Visol = 1500Vrms (Sinusoidal, 1min) Visol = 2500Vrms (Sinusoidal, 1min) [under development] 1.2. Functions and Features 1.2.1. Functions Outlines Figure-1(a) and Figure-1(b) show the photograph and internal functions block diagram of the DIP-IPM. The DIPIPM is the ultra-compact intelligent power module which integrates power parts, and drive and protection circuit of AC 100-220V class inverter drive for small power motor control in dual-in-line transfer-mold package. Figure-1(a). Photograph of the DIP-IPM Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE VUFS VUFB P VP1 UP +VCC Input Signal Condition Level Shift HVIC VVFS Gate Drive & UV lock out VVFB VP1 VP +VCC Input Signal Condition HVIC VWFS 5V Logic Interface to MCU Level Shift Gate Drive & UV lock out U VWFB VP1 WP VPC +VCC Input Signal Condition Level Shift HVIC VN1 UN VN WN Fo CFO Gate Drive & UV lock out V Motor W +VCC Input Signal Conditioning Gate Drive Fault Logic & UV lock out Protection Circuit CIN VNC LV-ASIC N + 15V Figure 1(b). Internal Functions Block Diagram of the DIP-IPM 1.2.2. Product Features ² Built-in IGBT inverter circuit for three phase AC output. Ø ² Mono drive-power-supply. ² Control and Protection Functions – P-side : Control circuit Under-Voltage (UV) protection (without fault signaling). – N-side : UV and Short-Circuit (SC) protection (with Fault signaling). (External shunt resistor is required for the SC protection function.) ² Small packaging using transfer mold materials realizes miniaturized inverter designs. ² By virtue of integrating an application specific type HVIC (High Voltage IC) inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. Thus, at least six isolation circuits, which were required in the past, can be eliminated. ² By virtue of fast and high voltage elements, and built-in peripheral circuits, mono drive-power-supply scheme is possible. Thus, three of the four external power supplies, which were required in the past, can be eliminated. High integration of power parts, and built-in drive and protection functions miniaturize the overall inverter set size and reduce design time. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Chapter 2 Electrical Characteristics 2.1. Static Characteristics Table 2. Characteristics of 15A/600V class DIP-IPM (medium-speed: PS21204; high-speed: PS21214) Symbol VCES VCE(sat) VEC Parameter Collector-emitter voltage Condition Collector-emitter saturation VD=VDB=15V, VCIN=0V, IC=15A Tj=25°C voltage -IC=15A, Tj=25°C, VCIN=5V FWDi forward voltage Rating 600V Max. PS21214 600V Max. 1.8V (Typ.) 2.0V (Typ.) 2.2V (Typ.) 2.2V (Typ.) 2.2. Dynamic Characteristics Table 3, Characteristics of 15A/600V class DIP-IPM (medium-speed: PS21204; high-speed: PS21214) ton/toff tc(on)/tc(off) Psw(on)/Psw(off) Switching times VCC=300V, VD=15V, IC=15A Tj=125°C, VCIN=0⇔5V 0.7/1.9µs (Typ.) 0.7/1.1µs (Typ.) Switching times VCC=300V, VD=15V, IC=15A Tj=125°C, VCIN=0 ⇔ 5V 0.4/0.9µs (Typ.) 0.4/0.4µs (Typ.) Switching losses VCC=300V, VD=15V, IC=15A Tj=125°C, VCIN=0 ⇔ 5V 0.5/1.5 mj/pulse 0.5/0.9 mj/pulse (Typ.) (Typ.) Conditions : VCC=300V, VD=VDB=15V, Tj=125°C, Inductive Load Half-Bridge Circuit (L=1mH) IC : 5A/div IC : 5A/div VCE :100V/div VCE :100V/div t : 200ns/div t : 200ns/div Figure 2. Switching Waveform of DIP-IPM PS21204 (medium-speed, 15A/600V class) (Typ.) DC 5V P-Side IGBT VP1 VB L IN VCIN(P) VPC OUT VS A P-Side Input Signal VCC B VD VN1 OUT IN VCIN(N) VNC VNO CIN L N-Side IGBT N-Side Input Signal Figure 3. Half-Bridge Evaluation Circuit Diagram (Inductive Load) `Note : B is connected during P-side switching, while A is connected during N-side switching. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Chapter-3 : 3.1. Package Package Outlines Drawing Figure 4. Package Outlines Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 3.2. List of Input / Output Terminals 3.2.1. Input / Output Terminals Description Control Terminals 1 2 3 4 22 5 6 7 8 23 9 10 11 24 12 13 25 14 15 16 17 18 19 20 21 26 Power Terminals Figure 5. Configuration of the DIP-IPM Terminals Table 4. Description of the DIP-IPM Terminals Terminal Terminal Description No. Name 1 UP U-phase P-Side control input terminal. 2 VP1 U-phase P-Side control supply terminal. 3 VUFB U-phase P-Side drive supply terminal. 4 VUFS U-phase P-Side drive supply GND terminal. 5 VP V-phase P-Side control input terminal. 6 VP1 V-phase P-Side control supply terminal. 7 VVFB V-phase P-Side drive supply terminal. 8 VVFS V-phase P-Side drive supply GND terminal. 9 WP W-phase P-Side control input terminal. 10 VP1 W-phase P-Side control supply terminal. 11 VPC P-side GND terminal. 12 VWFB W-phase P-Side drive supply terminal. 13 VWFS W-phase P-Side drive supply GND terminal. 14 VN1 N-side control supply terminal. 15 VNC N-side control GND terminal. 16 CIN Short-circuit trip voltage sensing terminal. 17 CFO Fault output time setting terminal (connected to external capacitor). 18 FO Fault output terminal. 19 UN U-phase N-Side control input terminal. 20 VN V-phase N-Side control input terminal. 21 WN W-phase N-Side control input terminal. 22 P Inverter DC-link positive terminal. 23 U U-phase inverter output terminal. 24 V V-phase inverter output terminal. 25 W W-phase inverter output terminal. 26 N Inverter DC-link negative (GND) terminal. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 3.2.2. Structure and Detailed Description of Input / Output Terminals Table 5. Structure and Detailed Description of the DIP-IPM Input and Output Terminals Item Symbol Description P-side drive supply VUFB-VUFS • These are drive supply terminals for the P-side IGBTs. terminal VVFB-VVFS • By virtue of the ability to use the boot-strap circuit scheme, no external power VWFB-VWFS supplies are required for the DIP-IPM P-side IGBTs. P-side drive supply • Each boot-strap capacitor is generally charged from the N-side VD supply during GND terminal ON-state of the corresponding N-IGBT in the loop. • An abnormal operation may result if the VD supply is not aptly stabilized or has insufficient loading capability. In order to prevent malfunction caused by such unstability, or by noise and ripple in supply voltage, a smoothing capacitor of favorable frequency and temperature characteristics should be mounted very close to each pair of these terminals. VP1 P-side control • These are control supply terminals for the built-in Ics (LVIC & HVICs). supply terminal • VP1 and VN1 should be connected externally. VN1 • In order to prevent malfunction caused by noise and ripple in the supply voltage, N-side control a smoothing capacitor of favorable frequency characteristics should be mounted supply terminal very close to these terminals. • Careful design work is, however, necessary so that the voltage ripple caused by noise or by system operation is kept below the maximum specified values. VPC P-side control • These are control grounds for the built-in Ics (LVIC & HVICs). GND terminal • VPC, VNC should be connected externally. VNC N-side control • Line current of the power circuit, however, should not be allowed to flow GND terminal through these terminals to avoid noise influences. Control input UP,VP,WP • Input terminals for controlling the DIP-IPM switching operation. terminal UN,VN,WN • Operate by voltage input signals. These terminals are internally connected to Schmitt trigger circuit composed of 5V-class CMOS. • Each signal line should be pulled up to plus side of the 5 V power supply with approximately 4.7kΩ resistance. (The value might change depending on wiring patterns.) • The wiring of each input should be as short as possible (less than 2 cm) to protect the DIP-IPM against noise influences. • To prevent signal oscillations, an RC coupling is reccomended. Short-circuit trip CIN • Current sensing resistance should be connected between this terminal and VNC to voltage sensing detect short-circuit situations (short-circuit voltage trip level). Input impedance terminal for CIN terminal is approximately 600kΩ. • CR filter should be connected in order to eliminate noise. Fault output FO • This is the terminal for fault output. Active low output is given from this terminal terminal indicating a faulty state of the DIP-IPM (SC and UV operation at N-side). • This output is open collecter type. FO signal line should be pulled up to the 5V power supply with approximately 5.1kΩ resistance. Fault pulse output CFO • This is the terminal for setting the fault pulse output time. time setting terminal • An external capacitor should be connected between this terminal and VNC to set the fault pulse output time. • A capacitor with the capacitance of 22nF is recommended (corresponding to 1.8ms typical value of fault pulse output time). Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Item Inverter positive power supply terminal Inverter GND Terminal Inverter power output terminal Symbol P N U, V, W Description • DC-link positive power supply terminal of the inverter. • Internally connected to the collecters of the P-side IGBTs. • In order to suppress surge voltage caused by DC-link wiring or PCB pattern inductance, connect the smoothing capacitor very close to the P and N terminals. It is also effective to add a small film capacitor of good frequency characteristics. • DC-link negative power supply terminal (power ground) of the inverter. • This terminal is connected to the emitters of the N-side IGBTs. • Inverter output terminals for connection to inverter load (e.g. AC motor). • Each terminal is internally connected to the intermidiate point of the corresponding IGBT half bridge arm. 3.2.3. Description of Drive and Protection Functions Table 6. Description of Drive and Protection Functions Function Symbol Description Normal drive — • The drive logic is based on “active-low” input format. • Off-level input signal (VCIN > Vth(off) ) drives IGBT off, and on-level input signal (VCIN < Vth(on) ) drives IGBT on. Short circuit SC • The external shunt resistance detects collector forward current of the DC-link. When the protection current exceeds a preset SC trip level, it is judged as a short circuit state, and the N-side IGBTs are turned off immediately. • A fault pulse signal is outputted from Fo terminal when this abnormal current flows through the external shunt resistance and the pulse duration is determined by the capacitance of the capacitor connected between CFO and VNC. After it is being outputted continuounsly for a certain period of time (depends on the capacitor), fault resetting takes place when the next input signal reaches the on-level. Control circuit UVD • An internal logic monitors the N-side control supply voltage. If the voltage falls below under voltage the UVD trip level for a given period of time, input signals to the N-side IGBTs are blocked. protection(UV) • The state of control circuit under-voltage protection remains until the voltage exceeds the UVDr reset level. • UVD fault pulse signal output period is determined by the capacitance of the external capacitor (CFO-VNC ). After fault signal is being outputted for a certain period of time (depends on the capacitor and the voltage level), the fault resetting takes place at the next input signal if control supply voltage is over the reset level. UVDB • An internal logic monitors the P-side floating voltage supplies. If the voltage level drops below the UVDB trip level for a given period of time, input signals for the P-side IGBTs concerned are not accepted. • The state of control circuit under-voltage protection remains until the voltage exceeds the UVDBr reset level. • Fault signal is not outputted for the P-side UV state. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 3.2.4. Structure of Control Input Terminals and Application Examples 5V line DIP-IPM Vreg=6.2V 5.1kΩ 4.7kΩ UP, VP, WP UN, VN, WN CPU Fo 1nF 1nF VNC(Logic) Note) RC coupling at each input may change depending on the PWM control scheme used in the application and on the wiring patterns. Figure 6. Structure of DIP-IPM Control Input Terminals Input Voltage The structure of the DIP-IPM control input terminals is described in Figure 6. FO output and input signals of the DIP-IPM should be 5V-class interface, in order to interface directly with CPU. Signal input terminals are internally connected to 5V-class Schmitt trigger circuits. Therefore, if an opto-coupler is used, its supply voltage should be 5V. Maximum ratings for input and FO output voltages are shown in the following table. As FO is open collector type and its rating is VD+0.5, 15V-class supply is possible. However, 5V-class supply is recommended for Fo output same as the input signals. Table 7. Maximum Ratings for Input Voltage and Fault Output Voltage (Tj=25°C, unless otherwise noted) Item Symbol Input voltage VCIN Fault output supply voltage VFO Condition Applied between UP,VP,WP-VPC, UN,VN,WN-VNC Applied between Fo-VNC Ratings Unit -0.5~+5.5 V -0.5~VD+0.5 V Value of Input Current Table 8. Input Current Ratings (VD=15V, Tj=25°C) Item S ym b o l Condition L level input current ICINL H level input current ICINH UP, VP, WP terminals (VCIN=0V) UN, VN, WN terminals (VCIN=0V) UP, VP, WP terminals (VCIN=5V) UN, VN, WN terminals (VCIN=5V) L level input current ICINL + 15V Ratings Typ. -100 -100 Max. -50 -50 Unit -50 -50 -20 -20 -7 -7 µA µA µA µA H level input current VP1 ,VN1 UP ,VP ,WP , UN ,VN ,WN Min. -150 -200 ICINH + 15V A A VP1 ,VN1 UP ,VP ,WP , UN ,VN ,WN 5V VPC ,VNC VPC ,VNC Figure 7. Diagram of Input Current Measurement Circuit Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 3.3. Installation Guidelines (Flatness / Mounting Strength / Screw Type / Grease) Fastening with excessive uneven stress when installing a module to a heat sink might cause devices to be damaged or to be degraded because the silicon chips inside the module will be stressed. An example of recommended fastening order is shown in Figure 8. R Temporary fastening → Permanent fastening → Q Figure 8. Recommended Fastening Order of Mounting Screws ` As a standard rule, set the temporary fastening torque to 20~30 % of the maximum rating. Table 9. Mounting Torque and Heat Sink Flatness Specifications Item Mounting torque Condition Min. 10 0.98 -50 Mounting screw : M4 Reccomended 12kg·cm Reccomended 1.18 N·m | Heat sink flatness Heat sink flatness is prescribed as seen in Figure 9. Ratings Typ. — — — Max. 15 1.47 +100 Unit I·F N·m µm DI P -IP M Measurement point \| 3m m Place to contact a heat sink Heat sink | \ Heat sink Figure 9. Measurement Point of Heat Sink Flatness For most effective heat-radiation it is necessary to enlarge, as much as possible, the contact area between the module and the heat sink while minimizing the contact thermal resistance. Regarding the heat sink flatness (warp/concavity and convexity) on the module installation surface (refer to Fig. 10), please follow the guidelines below. Also, the surface finishing-treatment should be 12s or less. Surface applied grease cho |hol + Base-plate edge – Heat sink flatness range Figure 10. Heat Sink Flatness Specifications Evenly apply 100µ ~200µ of thermally-conductive grease over the contact surface between a module and a heat sink. It is also useful for preventing the contact surface from being corroded. Further, use a grease type of stable quality within the operating temperature range and have long endurance. Use a torque wrench to fasten up to the specified recommended torque. Exceeding the Max. torque limit might cause the modules to be damaged or to be degraded as the above-mentioned fastening with uneven stress. Pay attention not to put any foreign matter onto the contact surface between a module and a heat sink. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Chapter 4 Applications 4.1. System Connection Diagram CBW+ CBV+ CBW- CBU+ CBV- CBU- High-side input (PWM) (5V line) Note 1,2) C3: Tight tolerance, temp-compensated electrolytic type (Note The capacitance value depends on the PWM control scheme used in the applied system.) C4: 0.22~2µF R-category ceramic capacitor for noise filtering C4 Input signal conditioning Input signal conditioning Input signal conditioning Level shifter Level shifter Level shifter C3 Note 6) UV circuit UV circuit UV circuit DIP-IPM Drive circuit Drive circuit Drive circuit Inrush current limiter circuit P AC input P-side IGBTs U Note 4) C V W Fig. 30 M Ac line output Z N1 N-side IGBTs N VNC CIN Z : Surge absorber C : AC filter (Ceramic capacitor 2.2~6.5nF) (protection against common mode noise) Drive circuit Input signal conditioning Fo logic SC Protection i Low-side input (PWM) (5V line) Note 1,2) i Control supply Under-voltage protection Fo CFO Fault output(5V line) Note 3,5) VNC VD (15V line) Figure 11. System Block Diagram of the DIP-IPM Note 1) To prevent the input signals oscillation, an RC coupling at each input is recommended. Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. Note 3) This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance. Note 4) The wiring between the power DC-link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltage. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N1 DC power input terminals. Note 5) Fo output pulse width (tFO) should be decided by connecting external capacitor between CFO and VNC terminals. (Example F CFO = 22nF → tFO = 1.8ms (Typ.)). Note 6) High voltage diodes (600V or more) should be used for the bootstrap circuit. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.2. Mono Drive-Voltage-Supply Scheme 4.2.1. Initial Charging : Charging current loop P(VCC) Bootstrap capacitor P-side IGBT + HVIC VDB U,V,W High voltage fast recovery diode LVIC VD N-side IGBT VCIN(n) N(GND) Bootstrap circuit VCC PWM Start 0V VD 0V VDB 0V VCIN(n) on Timing chart of bootstrap operation Figure 12. Charging Current Loop and Timing Chart of Bootstrap Circuit Charging In order for the DIP-IPM to start, initial bootstrap charging signals are required. By turning on the N-side IGBT, as shown in Figure 12, the bootstrap capacitor should be charged. Enough pulse width to fully charge the bootstrap capacitor should be applied. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.2.2. Charging and Discharging of the Bootstrap Capacitor During Inverter Operation High-side IC R1 D1 VB P C1 ID IGBT1 M1 R2 Q1 VCC FWDi1 VS M IGBT2 FWDi2 N N VCE(sat) of IGBT2 is Vsat2, VEC of FWDi2 is VEC2, and VF of D1 is VF1. Figure 13. Illustrative Inverter Circuit Diagram (1) Charging Timing Chart of Bootstrap Capacitor (C1) Case 1-1 : IGBT2 ON (Figure 14) When IGBT2 is in the ON state, charging voltage at C1 (VC1) is calculated by the equations : VC1(1) = VCC–VF1–Vsat2–ID·R2 (Transient state) VC1(1) = VCC (Steady state) Following this, IGBT2 is turned OFF. While both arms are OFF (the dead time of IGBT1 and IGBT2), regenerative mode conducted by FWDi1 generally starts. As the electric potential of VS rises close to that of P, C1 is not charged. When IGBT1 is turned ON, the voltage at C1 gradually declines from the potential VC1(1) due to the current consumed by drive circuit. OFF IGBT1 ON OFF IGBT2 Spontaneous discharge of C1 ON Declining due to current consumed by drive circuit VC1 Potential of C1 VC1(1) VS Figure 14. Timing Chart for Case 1-1 Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Case 1-2 : IGBT2 OFF and FWDi2 ON (Figure 15) When IGBT2 is OFF and FWDi2 is ON, the supply voltage across C1 (VC1) is calculated by the equation: VC1(2)=VCC–VF1+VEC2 While both IGBT2 and IGBT1 are OFF, regenerative mode conducted by FWDi2 is maintained. Thus the potential of VS drops to -VEC2, C1 is charged to restore the declined potential and its voltage starts to rise. Then, when IGBT1 is turned ON, the potential of VS rises to that of P, hence charging stops and the voltage across C1 gradually declines from the potential V C1(2) due to the current consumed by the drive circuit. OFF IGBT1 ON OFF IGBT2 ON VC1 VC1(2) Potential of C1 Declining due to current consumed by drive circuit VS Figure 15. Timing Chart for Case 1-2 (2) Guidelines for Selecting the Bootstrap Capacitor (C1) and Resistance (R2) The capacitance of bootstrap capacitor can be selected by this equation: C1=IBSxT1/∆V where T1 is the maximum ON pulse width of IGBT1 and IBS is the drive current of the IC (depends on temperature and frequency characteristics), and ∆V is the allowable discharge voltage. Additional margin value should also be added to the calculated capacitance. Resistance R2 should be basically selected such that the time constant C1·R2 will enable the discharged voltage (∆V) being charged again into C1 within the minimum ON pulse width (T2) of IGBT2. However, if only IGBT1 has an ON–OFF–ON control mode (Figure 16), the time constant should be set so that the consumed charge during the ON period can be charged during the OFF period. OFF IGBT1 ON OFF Declining due to current consumed by drive circuit IGBT2 ON Vc1 Charging area Potential of C1 VS Figure 16. Timing Chart of ON–OFF–ON Control Mode Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE (3) Current characteristics of P-side floating supply (VB- VS) are described in Fig.17 to 20 (typical for PS21204): ConditionsF VD=VDB = 15V, Tj =–10, 25, 100, 125°C, DUTY = 10, 30, 50, 70, 90%, fc = 1.5, 3, 7kHz Carrier frequency vs. Circuit current characteristics 1000 Circuit current (µA) DUTY=10% DUTY=30% DUTY=50% DUTY=70% DUTY=90% 500 10 1 Carrier frequency (kHz) Figure 17. Characteristics under the Condition of Tj=–10°C (typical for PS21204) Carrier frequency vs. Circuit current characteristics 1000 Circuit current (µA) DUTY=10% DUTY=30% DUTY=50% DUTY=70% DUTY=90% 400 1 Carrier frequency(kHz) 10 Figure 18. Characteristics under the Condition of Tj=25°C (typical for PS21204) Carrier frequency vs. Circuit current characteristics 1000 DUTY=10% Circuit current (µA) DUTY=30% DUTY=50% DUTY=70% DUTY=90% 300 1 Carrier frequency (kHz) 10 Figure 19. Characteristics under the Condition of Tj=100°C (typical for PS21204) Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Carrier frequency vs. Circuit current characteristics 1000 DUTY=10% Circuit current (µA) DUTY=30% DUTY=50% DUTY=70% DUTY=90% 300 1 Carrier frequency (kHz) 10 Figure 20. Characteristics under the Condition of Tj=125°C (typical for PS21204) Table 10. Example of the Circuit Current Value for Each Parameter (typical for PS21204; Unit:µA) DUTY(%) Tj(°C) Carrier Frequency 10 30 50 70 90 fc(kHz) –10 1.5 559 577 596 614 633 3 611 630 648 667 685 7 744 672 781 800 817 25 1.5 475 485 494 548 563 3 504 523 586 601 615 7 686 702 717 732 746 100 1.5 409 420 431 442 452 3 464 475 485 496 506 7 599 611 622 633 643 125 1.5 365 374 405 415 424 3 440 449 458 466 475 7 572 581 590 600 608 Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.3. Interface Circuit Examples and Guidelines 4.3.1. Direct Input (without Opto-Coupler) Interface Example Figure 21 shows a typical application circuit interface example, when signals are inputted directly from a microcomputer. For detailed circuit design, please contact Mitsubishi Electric. C1 : Electrolytic capacitor of good temperature characteristics C2,C3 : 0.22~2µF R-category ceramic capacitor for noise filtering 5V line C2 VUFB C1 VUF DIP-IPM P VP1 C3 UP C2 VVF C1 VVF VP1 C3 VCC VB IN HO COM VS VCC VB IN HO COM VS U VP C2 VWF C1 VWFS V M VP1 Controller C3 VCC VB IN HO WP VPC COM W VS + - UOUT VN1 VCC C3 5V line VOUT UN VN WN Fo UN VN WOUT If this wiring is too long, it WN Fo might cause short circuit. VNO CIN VNC GND N CFO C CFO C4(CFO) 15V line CIN B R1 C5 Shunt Resistor A Long wiring of GND might generate noise If this wiring is too long, SC level on input signals and cause the IGBT drive fluctuation might be large and cause to malfunction. SC malfunction. N1 Figure 21. Typical Application Circuit Interface Example with Direct Input (without Opto-Coupler). Note 1) To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short as possible. (Less than 2cm) Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. Note 3) Fo output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance. Note 4) Fo output pulse width should be decided by connecting an external capacitor between CFO and Vnc terminals (CFO). (Example : CFO=22nF→tFO=1.8ms(Typ.)) Note 5) Each input signal line should be pulled up to the 5V power supply with approximately 4.7kΩ resistance (other RC coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board). Approximately a 0.22~2µF by-pass capacitor should be used across each power supply connection terminal. Note 6) To prevent errors of the protection function, the wiring of A, B, C should be as short as possible. Note 7) In the recommended protection circuit, please select the R1C5 time constant in the range 1.5~2µs. SC intercept time might change depending on the wiring patterns. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Note 8) Each capacitor should be put as nearby the terminals of the DIP-IPM as possible. Note 9) To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 terminals should be as short as possible. Approximately a 0.1~0.22µF snubber between the P&N1 terminals is recommended. 4.3.2. Interface Example when a Fast Opto-Coupler is used Figure 22 shows a typical application circuit interface example, when a fast opto-coupler is used. VUFB DIP-IPM VUF C1 C2 C3 DC 5V HVIC1 VP1 UP VCC VB IN HO COM VS P DC 5V U VVF VVF Control Unit C1 C2 C3 HVIC2 VP1 VP VCC VB IN HO COM VS V VWF + M – VWFS C1 C2 CONTROLLER C3 HVIC3 VP1 WP VPC VCC VB IN HO COM W VS LVIC UOUT VN1 VCC C3 VOUT UN VN WN FO UN VN WOUT WN FO VNO CIN VNC GND N CFO CFO CIN Control Power Supply DC 15V R1 C4 C5 Shunt Resistor N1 Figure 22. Typical Application Circuit Interface Example when a Fast Opto-coupler is used. Note: 5V should be applied to the secondary side of the opto-coupler. The 5V supply line should be referenced to the same ground as the 15V supply line (VNC). For other precautions, please refer to the data sheets. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.3.3. Interface Example when a Slow Opto-Coupler is used Figure 23 shows a typical application circuit interface example, when a slow opto-coupler is used. VUFB DIP-IPM VUF C1 C2 VP1 C3 DC 5V HVIC1 UP DC 5V Control Unit VCC VB IN HO COM VS P U VVF VVF C1 C2 C3 HVIC2 VP1 VP VCC VB IN HO COM VS V VWF + M – VWFS C1 C2 CONTROLLER C3 HVIC3 VP1 WP VCC VB IN HO VPC COM W VS LVIC UOUT VN1 VCC C3 VOUT UN VN WN FO UN VN WOUT WN FO VNO CIN VNC GND N CFO CFO CIN Control Power Supply DC 15V R1 C4 C5 Shunt Resistor N1 Figure 23. Typical Application Circuit Interface Example when a Slow Opto-coupler is used. Note • Wiring between opto-coupler and DIP-IPM terminals should be as short as possible and a pattern layout that suppresses stray capascitance should be adopted. • Slow opto-coupler with the capacity of CTR 100~200% should be used. The input current should be set to 8~10mA in order to achieve active region operation. • Transient voltage change should be as small as possible by mouting capacitors of low impedence characteristics, etc. close to each control supply terminal. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.4. Short Circuit Protective Function 4.4.1. Timing Charts of Short Circuit Protection (Figure 24) A. Short-Circuit protection (Lower-arms only) : Protection by external shunt resistance and CR time constant circuit a1. Normal operation: IGBT ON and carrying current a2. Short circuit current detection (SC trigger). T h e o p tim u m settin g fo r th e C R circu it tim e co n stan t is 1 .5 ~ 2 .0 µ s. a3. Hard IGBT gate interrupt a4. IGBT turns OFF a5. Fo timer operation starts: The pulse width of the Fo signal is set by the external capacitor CFO. a6. Input “H”= IGBT OFF state a7. Input “L”= IGBT ON state a8. IGBT OFF state N-side control input a6 Protection circuit state a7 SET Internal IGBT gate RESET a3 a2 SC a4 a1 Output current Ic(A) a8 SC reference voltage Sense voltage of the Shunt resistance CR circuit time constant DELAY Error output Fo a5 Figure 24. Timing Chart of SC Operation If the protection is reset at LOW state (active) of N-side control input, IGBT is turned ON at the next HIGH-toLOW input signal. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.4.2. Selecting the Current Sensing Shunt Resistor Value The DIP-IPM short circuit protection accepts the voltage value across the external current sensing resistor into the control IC as SC trip level (reference voltage) and operates by internally interrupting the output. The scheme for setting the value of external current sensing resistor is shown below : (1) The current sensing resistor value is calculated using this expression : Current sensing resistor value R= VSC(ref)/Isc where VSC(ref) is the SC reference voltage (trip level) of the control IC and Isc is the current value to be interrupted. (2) The SC reference voltage (trip level) of the control IC is designed based on the following specifications, which include voltage spread parasitic and temperature variations. Therefore, the fluctuation range (shown in Table 11) should be taken into consideration. Table 11. Specification for VSC(ref) (Unit:[V]) MIN TYP MAX VSC(ref) specification at 0.45 0.50 0.55 Ta=25°C (Typ.) Specification for 0.42 — 0.57 ALL Conditions including Temperature variations (3) (4) (5) Figure 25 shows the relationship between sensing resistor values and interrupted current values, based on various conditions including fluctuation range described in Table 11. In Fig. 25, crossing a certain value of sensing resistor with the graph curve enables you to achieve MIN / MAX values of interrupted current for the resistor value. The solid line in the graph indicates the specification at the typical condition (Ta=25°C), and the dotted line indicates the specification for all conditions including temperature variations. Optimum value of sensing resistor can be selected by examining the range of current to be interrupted in this graph. One example for calculating the value is given below. As a reference, temperature characteristics of VSC(ref) (an example of measured values) is also shown in Figure 26. Maximum current rating depends on Ic(sat) of the IGBTs. When designing, please contact Mitsubishi Electric. There are situations when resonant signals caused by parasitic inductance and parasitic capacity falsely start the short –circuit protection. In that case, appropriate filter circuit would be necessary. Finally, the sensing resistor value should be evaluated on the actual design. Calculation Example (For PS21204–15A/600V) When the sensing current value is set to the MIN value of short-circuit current specification (MIN value of IGBT saturation current): • MIN value of specification = 25.5A (Rating : 1.7 times of 15A) • In Figure 25, a horizontal line should be drawn from the current value 25.5A on the Y-axis. If the line crosses with the VSCth graph curve, that intersection indicates the appropriate resistor value. • Voltage dispersion of VSCth should be taken into consideration. In this case, the intersection of current value 25.5A and VSCth MAX value (=0.57V; All Condition) should be the appropriate resistor value. Thus, the sensing resistor value is 22.4mΩ . It is found by this simple expression : R=V/I = 0.57/25.5 = 22.4mΩ • As a result, even if there are some voltage dispersion of VSCth, 25.5A current or less will activate the shortcircuit protection (e.g. For VSCth MIN=0.42V, protection is activated at 18.8A). Therefore, high short –circuit currents will no longer be conducted. • In the above calculation, however, resistance dispersion is not taken into consideration. In order to consider it, MIN value of resistor should be set to 22.4mΩ. When the sensing current value is set to an optional one below the MIN value of IGBT saturation current: • Same as the above, a horizontal line should be drawn from an optional current value below 25.5A. • The intersection of the line and the graph curve of VSCth MAX value (0.57V) indicates the appropriate resistor value. The value is found by this expression: Sensing resistor value R = V/I = 0.57/Set current value. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Figure 25 Relationship between Sensing Resistance and Interupted Current Va lu e of in t er r u pt ed cu r r en t D[A] 100.0 VSCt h MAX va lu e for a ll con dit ion s in clu din g t em per a t u r e va r ia t ion s(0.57V) 95.0 90.0 85.0 80.0 75.0 70.0 65.0 60.0 55.0 50.0 45.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 VSCt h MAX va lu e for a ll con dit ion s in clu din g t em per a t u r e va r ia t ion s(0.42V) VSCth MAX value 0.55V VSCth TYP value 0.50V VSCth MIN value 0.45V E xa m ple of SC cu r r en t specifica t ion MIN va lu e (=IGBT sa t u r a t ion cu r r en t ) 0 5 10 15 20 25 30 35 40 45 50 Sensing resistor value R [mΩ] Figure 26,Example of VSC(ref) Temperature Characteristics (Control supply voltage VD=15Vj F igu re 2 7 . E x am p le of I c(sat) C h aracteristics (M IN valu e) 50 Temperature characteristics of VSCth (Example of measured values) 45 40 0.575 35 0.55 30 IC(A) 0.6 0.525 0.5 VD=16.5V VD=15V 25 20 0.475 VD=13.5V 15 0.45 10 0.425 5 0.4 -60 -40 -20 0 20 40 60 80 Temperature Ta [°C] 100 120 140 160 0 0 2 4 6 8 10 VCE(V) Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.4.3. SOA of the DIP-IPM (For short-circuit switching) • SOA of the DIP-IPM is described below. (It is not recommended to operate the DIP-IPM under these conditions.) VCES : MAX rating of IGBT collector-emitter voltage inside DIP-IPM VCC : P-N supply voltage VCC(surge) : Calculated by adding to VCC the surge voltage, which is generated by the wiring inductance between the DIP-IPM and the DC-link capacitor. VCC(PROT) : Indicates the P-N supply voltage value up to which the DIP-IPM can protect itself. ≤VCES Collector current Ic ≤VCES ≤VCC(PROT) VCE=0, IC=0 ≤VCC(PROT) Short-circuit current VCE=0, IC=0 ≤2µs Figure 28. SOA for Switching and Short-circuit Turn-off switching VCES represents the 600V voltage rating of the IGBTs incorporated into the DIP-IPM. Subtracting the surge voltage (100V or less), generated by wiring inductance inside the DIP-IPM, from VCES is VCC(surge), that is, 500V. Moreover, subtracting from VCC(surge) the surge voltage (50V or less) generated by the wiring inductance between the DIP-IPM and the DC-link capacitor is VCC, that is, 450V. For short-circuit operation VCES represents the 600V voltage rating of the IGBTs incorporated into the DIP-IPM. Subtracting the surge voltage (100V or less) generated by wiring inductance inside the DIP-IPM from VCES is VCC(surge), that is, 500V. Moreover, subtracting from VCC(surge) the surge voltage (100V or less) generated by the wiring inductance between the DIP-IPM and the electrolytic capacitor is VCC, that is, 400V. Fig. 29 shows short-circuit conduction capability of the IGBTs incorporated into the DIP-IPM (Example of PS21204). Conditions: VCC=400V, Tj=125°C (initially), non-repetitive, VCES≤600V, VCC(surge)=500V (including surge voltage), load short-circuit. Ic(Short-circuit current)—Pulse width characteristics 160 For VD=16.5V 140 120 100 1?i)j 80 60 Saturation current max value(VD=16.5V) 40 SC operation range 20 0 0 1 2 3 4 Pulse width (µs) 5 6 7 Figure 29. PS21204 Short-circuit Current and Pulse Width Characteristics For other DIP-IPM types, please contact Mitsubishi Electric. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.4.4. Filter Circuit Setting (RC Time Constant) for Short-circuit Operation • Example of DIP-IPM Short-circuit Protection External Parts DIP-IPM Drive circuit P H-side IGBTs U V W L-side IGBTs SC Protection External Parts N1 External shunt resistance Note1) N A VNC R C Drive circuit CIN B C SC protection Note2) Figure 30. Example of External Protection Circuit • Characteristics of RC filter circuit Ic(A) SC protection level Collector current waveform 0 2 Tw(µs) Figure 31. Characteristics of CR Filter Circuit Short-circuit Protection Figure 30 shows the example of external SC protection circuit. When the line current on N-side DC-link is detected, protective operation starts through the RC filter. If the current exceeds the SC reference voltage, all the gates of the N-side three-phase IGBTs are interrupted and the fault signal is outputted. As short–circuit protection is non-repetitive, operation should be stopped immediately after the fault output. Setting of RC Time Constant When the RC filter circuit is connected, SC protection malfunction caused by noise on shunt resistance can be prevented. Moreover, the RC filter circuit immediately interrupts short-circuit currents due to its characteristics (shown in Figure 31). It also allows the conduction of the FWDi reverse recovery current. In order to set the time constant, the IGBT ability (shown in Figure 29) should be considered. Figure 29 shows example of an IGBT with Min. ON threshold voltage value (thus having high saturation current). For example, when the drive-voltage is the MaxD16.5V of the recommended range, 8.5 times of the rating collector current (maximum current at VD=16.5V) conduct under the above conditions. In this case, if the ON period of the IGBT (pulse width) is less than 4µs, it indicates that the IGBT has the ability to safely turn off. As for the DIP-IPM, the recommended RC time constant is 2µs or less in consideration of margins. Note: In order to avoid SC protection malfunction caused by wiring inductance influences, wiring between A, B, and C should be as short as possible. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.5. Guidelines for Control Supply 4.5.1. Timing Charts of Under-Voltage Protection (Figure 32,33) B. Under-Voltage Protection (N-side, VD) a1. Normal operation : IGBT ON and carrying current a2. Under-voltage trip (UVDt) a3. IGBT turns OFF inspite of control input condition. a4. Fo timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a5. Under-voltage reset (UVDr) a6. Normal operation : IGBT ON and carrying current Control input Protection circuit state Control supply voltage V D SET RESET UV D r a5 UV D t a2 a1 a3 a6 Output current Ic(A) a4 Error output Fo Figure 32. Timing Chart for N-side UV Operation C. Under-Voltage Protection (P-side, VDB) a1DControl supply voltage rises : After the voltage level reaches UVDBr, the circuits start to operate when the next input is applied. a2. Normal operation : IGBT ON and carrying current a3. Under-voltage trip (UVDBt) a4. IGBT OFF inspite of control input condition, but there is no Fo signal output. a5. Under-voltage reset (UVDBr) a6. Normal operation : IGBT ON and carrying current Control input Protection circuit state RESET RESET SET UVDB r Control supply voltage VDB a1 a5 UVDB t a2 a3 a4 a6 Output current Ic(A) High-level output (no fault output) Error output Fo Figure 33. Timing Chart for P-side UV Operation Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.5.2. Control Supply Starting up and Shutting Down Sequence Control supply VD should be started up prior to the main supply (P-N supply). Control supply VD should be shut down after the main supply (P-N supply). 5V-class power supply for input pull-up is required for the DIP-IPM, which is driven by 5V input. This 5V-class power supply should be started up when the control supply VD reaches the reset level of under-voltage protection (UVDr). If the main supply had been started up before the control supply becomes stable, or if the main supply remains after control supply was shut down, external noise might cause the DIP-IPM to malfunction. 4.5.3. Other Guidelines DIP-IPM state in each range of control supply voltage The voltage range including ripples should meet the specification. Table 12. DIP-IPM State in Each Range of Control Supply Voltage Range of control supply State voltage(VD, VDB) It is almost same as no power supply. 0~4.0 External noise may cause the DIP-IPM to malfunction (turns ON). Supply under-voltage protection is not operated and no Fo signals are outputted. Even if control input signals are applied, switching operation remains 4.0~12.5 stopped. Supply under-voltage protection starts operation and outputs Fo signals. Switching operation starts. This range of control supply voltage, however, 12.5~13.5 is below the recommended one. Thus, both VCE(sat) and switching time become against the DIP-IPM specification values, it might cause collector dissipation increase and junction temperature rise. 13.5~16.5 Normal operation starts. This range is recommended. Switching operation starts. This range, however, is over the recommended 16.5~20.0 one. Thus, too fast switching time might cause the chips to be damaged, because they fall short of capabilities for short-circuit operation. 20.0~ The control circuit of the DIP-IPM might be damaged. Note) UV fault signals are outputted for VD supply only. Specifications for Ripple Noise High frequency noise is super imposed on the control IC supply line, IC malfunction might be caused and fault signals might be outputted. Finally IC might stop (interrupt gates). To avoid such a malfunction, the supply circuit should be designed such that the noise fluctuation is softer than ±1V/µs, and the ripple voltage is less than 2 V. Specification : dV/dt≤±1V/µs, Vripple≤2Vp-p Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.6. Power Loss and Heat Dissipation Design 4.6.1. Power Loss Calculation (Example) Simple expressions for calculating average power loss ♦ Scope In preparation for applying the DIP-IPM in VVVF inverter, it is possible to calculate overall loss in normal operation in order to select (or compare) power modules. This calculation, however, cannot be applied to thermal design under extreme conditions. ♦ Assumptions Sine waveform current output PWM control VVVF inverter PWM signals generated by the comparison of sine waveform and triangular waveform. Duty amplitude of PWM signals varies within the range: 1− D 1+ D (%/100) ~ 2 2 Output current is given by Icp · sinx and it does not have ripple. Load power factor for output current is cosθ, while ideal inductive load is assumed for switching. IGBT saturation voltage VCE(sat) is in proportion to the collector current Ic. Forward voltage drop of free-wheeling diode VEC is in proportion to the forward current IEC. Switching losses PSW(on) and PSW(off) are in proportion to the collector current. Reverse current of free-wheeling diode is constant regardless of the forward current IEC. ♦ Expressions Static loss of IGBT 1 D Icp × Vce( sat )(@ Icp ) × ( + cosθ ) 8 3π Dynamic loss of IGBT ( Psw(on) + Psw(off )) × fc × 1 π Static loss of free-wheeling diode 1 D Iecp × Vec(@ Ifp = Icp) × ( − cosθ ) 8 3π Dynamic loss of free-wheeling diode 1 × ( Irr × Vcc × trr × fc) 8 ♦ Expressions Derivation For the time t, duty ratio of PWM signals is presented by 1 + D × sin t . This corresponds to the change of 2 output voltage. Thus, with the power factor cosθ• indicating the relationship between output current and voltage, the expressions to calculate output current and PWM duty will be derived as follows: Output(current = Icp × sin x 1 + D × sin(t + θ ) PWM(Duty = 2 Thus, VCE(sat) and VEC at the phase x for linear approximation is calculated by: Vce( sat ) = Vce( sat )(@ Icp) × sin x) Vec = Vec(@ Iecp = Icp)(−1) × sin x) Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Thus, the static loss of transistor is calculated by: 1 + D sin( x + θ ) -dx 0 2 1 π 1 + D sin( x + θ ) -dx = Icp × Vce( sat )(@ Icp) × ( Icp × sin 2 x) × ∫ 2π 0 2 1 D = Icp × Vce( sat )(@ Icp) × + cosθ 8 3π 1 2π ∫ π ( Icp × sin x ) × (Vce( sat )(@ Icp ) × Similarly, the static loss of free-wheeling diode is calculated by: 1 2π ∫ 2π π ((−1) × Icp × sin x) × ((−1) × Vec(@ Icp) × sin x) × 1 + D sin( x + θ ) -dx 2 1 D = Icp × Vec(@ Icp) × ( − cosθ ) 8 3π On the other hand, the dynamic loss of transistor, which does not depend on PWM duty, is calculated by: 1 2π π ∫ 0 ( Psw(on)(@ Icp) + Psw(off )(@ Icp)) × sin x) × fc-dx = ( Psw(on)(@ Icp) + Psw(off )(@ Icp)) × fc × 1 π If dynamic loss of free-wheeling diode is idealized as shown in Figure 34, it is calculated by: trr Iec Vec t Irr Vcc Figure 34 , FWDi Dynamic Loss Psw = Irr × Vcc × trr ( (const.) 4 Recovery occurs in the middle of output current period. Thus, the dynamic loss is calculated by: Irr × Vcc × trr 1 × fc × 4 2 1 × ( Irr × Vcc × trr × fc ) 8 ♦ Guidelines for applying the power-loss expressions in inverter designs Divide the output current period into fine-steps and calculate the losses at each step based on the actual values of : PWM duty; output current; the values of VCE(sat), VEC, Psw corresponding to the output current. • PWM duty depends on the way of generating signals. • The relationship between output current waveform or output current and PWM duty changes depending on the way of generating signals, load, and other various factors. Thus, calculation should be performed based on actual waveforms. • The value of VCE(sat). (@Tj=125°C) should be used. • The value of half bridge operation switching loss (Psw) at 125°C should be used. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.6.2. Temperature Rise Considerations and Calculation Example • The result of loss calculation performed using the typical characteristics of PS21204 (15A/600V) is given in Figure 35 as “Effective current Io vs carrier frequency characteristics”. Conditions; VCC=300V, VD=VDB=15V, VCE(sat)=Typ., Switching loss=Typ. Value, Tj=125°C, Tc=100°C Rth(j-c)=Max. specification, Simulation model 3-phase modulation 60Hz sine waveform output Effective output current Io(Arms) 100 10 1 1 10 Carrier frequency fc(kHz) 100 Figure 35. Carrier Frequency – Effective Current Characteristics Note; The characteristics above may vary depending on the control schemes and the motor drive types. Ø Figure 35 indicates an example of an inverter operated under the condition of Tc=100°C. It presents the effective current Io rms which can be outputted when the junction temperature Tj rises to the average junction temperature of 125°C (up to which the DIP-IPM operates safely). Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 4.7. Noise Withstand Capability 4.7.1. Examples of Measurement Circuits Noise withstand capability Note: For noise test of DIP-IPM, ±2.0kV or more withstand capability has been confirmed under the conditions given in Figure 36. However, noise withstand capability heavily depends on the test conditions, the wiring patterns of control substrate, parts layout, and other factors; therefore the actual system test should be performed. Measuring circuit H ea t sin k C1 R Br ea k er U V W DIP-IPM S T 3-phase 200V M FO Volt a ge slider I/F Con t rol su pply (15V sin gle power-sou rce) Isola tion t ra n sform er N oise sim u la t or In ver t er DC supply AC100V Figure 36. Noise Test Circuit C1: AC line common-mode filter 4700pF PWM signals have been inputted from microcomputer both directly and through opto-coupler. 15V single power-source drive Test is performed for both IM and DCBLM motors. Measurement conditions VCC=300V, VD=15V, Ta=25°C, no load The scheme for applying noise : From AC line (R, S, T), Period T=16ms, Pulse width tw=0.05~1µs, RANDOM input. 4.7.2. Countermeasures and Precautions Noise countermeasures implemented within the DIP-IPM The DIP-IPM improves noise withstand capabilities by reducing parts count, lowering inductance by the internal wiring optimization, and reducing leakage current by the isolation structure optimization. Noise countermeasures outside the DIP-IPM For malfunction caused by external noise overcurrent • Improving power supply filtering (close to DIP-IPM terminals) • Lowering impedance of input parts (reducing pull-up resistance) • Connecting filter between input parts and GND (bypassing noise) Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Example of overcurrent operation caused by DIP-IPM noise Malfunction example when the input signal wiring of DIP-IPM is long: • The evaluation circuit and conditions are given below. Conditions: Vcc=280V, VD=15V (external supply), VDB=15V (External supply), Opto-coupler 5V supply (external supply), Ta=25°C Evaluation circuit Input wiring DC5V VDB VP1 VCIN(P) P-side IGBT VB L IN OUT VS VPC N-side IGBT VD VCC VN1 OUT VCIN(N) IN VNC VNO CIN 25mΩ Figure 37. Half Bridge Evaluation Circuit (Inductive Load) • When the DIP-IPM input wiring is long, noise can be easily imposed on the wiring inductance. As a result, the opto-coupler output voltage drops and arm short occurs. The wiring of the DIP-IPM output and input might also cause inductive coupling. Noise caused by current fluctuation of the DIP-IPM and bus inductance might cause cross talk on the wiring between the opto-coupler and the DIP-IPM as shown in Figure 38. In du ct ive cou plin g Load Load Load IPM input-side IPM output-side Figure 38. Cross Talk Model • When an input signal changes from Low to High, the transistor on the light receiving parts of the opto-coupler is OFF. The DIP-IPM input wiring is connected to the +5V supply through the load resistance of the opto-coupler. Thus, if the transistor on the light receiving parts of the opto-coupler is OFF, the signal lines impedance looking from the DIP-IPM becomes high and inductive noise can easily affect the DIP-IPM. The longer the wiring between the opto-coupler output and the DIP-IPM input is, the more it tends to receive inductive noise. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE •Four countermeasures are described below. 5V R C1 IPM input C2 Ligh t -r eceivin g pa r t s of opt o-cou pler GND Figure 39. DIP-IPM Input Parts Circuit Example 1. Signal wiring impedance can be lowered by reducing the load resistance. 2. Signal wiring impedance can be lowered by connecting a capacitor in parallel with the load resistor. 3. Noise can be bypassed by connecting C2 between the DIP-IPM input terminals and GND. 4. Inductive coupling factors of both output and input sides should be minimized by shortening wiring lengths (reducing inductance). Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Chapter 5 Additional Guidelines 5.1. Packaging Specification (44) (22) P la st ic t ube P er t u be DIP – IP M 6 pieces of DIP -IP M per t u be (450) 5 colu m n s of t u be P a r t it ion 6 r ows P er pa ck a ge box (Ma x.) of t u be Tot a l n u m ber of t u bes is 30. (5 colu m n sˇ6 r ows) Tot a l n u m ber of DIP -IP Ms is 180. (30 t u besˇ6 pieces) (250) (180) Weigh t Appr oxim a t ely 53g /P er DIP –IP M Appr oxim a t ely 420g/P er t u be Appr oxim a t ely 13.7kg/P er pa ck a ge The a bove weigh t s a r e on es wh en t he m a xim u m n u m ber of DIP -IP Ms a r e pa cka ged. (600) P a cka ge box Figure 40. DIP-IPM Packaging Specification Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE 5.2 5.2,Handling Notice Transportation • Put package boxes in the correct direction. Putting them upside down, leaning them or giving them uneven stress might cause electrode terminals to be deformed or resin case to be damaged. • Throwing or dropping the packaging boxes might cause the devices to be damaged. • Wetting the packaging boxes might cause the breakdown of devices when operating. Pay attention not to wet them when transporting on a rainy or a snowy day. Storage • We suggest room temperature and humidity in the ranges 5~35°C and 45~75%, respectively, for the storage of modules. The quality or reliability of the modules might decline if the storage conditions are quite different from the above. Long storage • When storing modules for a long time (more than one year), keep them dry. Also, when using them after long storage, make sure that there is no visible flaw, stain or rust, etc. on their exterior. Surroundings • Keep modules away from places where water or organic solvent may attach to them directly or where corrosive gas, explosive gas, fine dust or salt, etc. may exist. They might cause serious problems. Disposal • The epoxy resin and the case materials are made of approved products in the UL standard 94V0, still they are incombustible. Static electricity • Exclusive ICs of MOS gate structure are used for the DIP-IPM power modules. Please keep the following notices to prevent modules from being damaged by static electricity. (1)Notice of breakdown by static electricity Excessively high voltage (over the Max. rated input terminal voltage) resulting from the static electricity of human bodies and packaging materials, might cause the modules to be damaged if applied on the control terminals. For countermeasures against static breakdown, it is important to control the static electricity as much as possible and when it exists, discharge it as soon as possible. Do not use containers which are easy to be electrostaticly charged during transportation. Be sure to short the control terminals with carbon cloth, etc. just before using the module. Also, do not touch between the terminals with bare hands. During assembly (after removing the carbon cloth, etc.), earth machines used and human bodies. We suggest putting a conductive mat on the surface of the operating table and the surrounding floor. When the terminals on the printed circuit board with mounted modules are open, the modules might be damaged by static electricity on the printed circuit board. When using a soldering iron, earth its tip. (2)Notice when the control terminals are open When the control terminals are open, do not apply voltage between the collector and emitter. Short the terminals before taking a module off. Feb. 1999 MITSUBISHI SEMICONDUCTOR DIP-IPM APPLICATION NOTE Notice for Safe Designs • We are making every effort to improve the quality and reliability of our products. However, there are possibilities that semiconductor products be damaged or malfunctioned. Pay much attention to take safety into consideration and to adopt redundant, fireproof and malfunction-proof designs, so that the breakdown or malfunction of these products would not cause accidents including human life, fire, and social damages. Notes When Using This Specification • This specification is intended as reference materials when customers use semiconductor products of Mitsubishi Electric. Thus, we disclaim any warranty for exercise or use of our intellectual property rights and other proprietary rights regarding the product information described in this specification. • We assume absolutely no liability in the event of any damage and any infringement of third party’s rights arising from the use of product data, diagrams, tables, and application circuit examples described in this specification. • All data including product data, diagrams, and tables described in this specification are correct as of the day it was issued, and they are subject to change without notice. Always verify the latest information of these products with Mitsubishi Electric and its agents before purchase. • The products listed in this specification are not designed to be used with devices or systems, which would directly endanger human life. Should you intend to use these products for special purposes such as transportation equipment, medical instruments, aerospace machinery, nuclear-reactor controllers, fuel controllers, or submarine repeaters, please contact Mitsubishi Electric and its agents. • Regarding transmission or reproduction of this specification, prior written approval of Mitsubishi Electric is required. • Please contact Mitsubishi Electric and its agents if you have any questions about this specification. Feb. 1999

Dip Ipm Vers.2, Application Note

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