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Cover 88PG8218 Field Programmable, Analog Self-Compensated Regulators Low Quiescent Current, Dual Output Step-down Switching Regulator and LDO for General Purpose Applications Datasheet Doc. No. MV-S105108-01, Rev. D July 31, 2009 M a r ve ll. M ovin g For w a r d Fa st e r Document Classification: Proprietary 88PG8218 Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: 3.0 Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. 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At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright © 1999–2009. Marvell International Ltd. All rights reserved. Marvell, Moving Forward Faster, the Marvell logo, Alaska, AnyVoltage, DSP Switcher, Fastwriter, Feroceon, Libertas, Link Street, PHYAdvantage, Prestera, TopDog, Virtual Cable Tester, Yukon, and ZJ are registered trademarks of Marvell or its affiliates. CarrierSpan, LinkCrypt, Powered by Marvell Green PFC, Qdeo, QuietVideo, Sheeva, TwinD, and VCT are trademarks of Marvell or its affiliates. Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications. Doc. No. MV-S105108-01 Rev. D Page 2 Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 88PG8218 Field Programmable, Analog Self-Compensated Regulators PRODUCT OVERVIEW The 88PG8218 is a high performance general purpose power management regulator housed in a 3mm X 4mm DFN-12 package. This device has multiple outputs to power I/O and core voltages for DSP or CPU applications. It includes a switching regulator and a Low Dropout (LDO) regulator. The switching regulator utilizes a proprietary internally compensated PWM control to regulate the output voltage, which offers fast transient response and minimal external components. The 88PG8218 operates from 2.7V to 5.5V input voltage range. The step-down switching regulator can deliver up to 1.2A output current while the LDO is capable of sourcing up to 200mA. The switching regulator output voltage can be set to one of eight standard voltages through the VSET resistor or can be programmed from 0.72V to 3.63V through the EN/SDI input. The LDO output can be set from 1V to 5V by a resistor divider. The switching frequency is 2MHz (typical), allowing the use of low profile surface mounted inductors and low value capacitors. Other features include internal current limit, soft start, under/over voltage lockout, and thermal shutdown. The input quiescent current of the 88PG8218 at a light load is 210µA (typical), resulting in high efficiencies at both light and full loads. Applications Features Input voltage range 2.7V to 5.5V Two outputs: • Switching regulator: - VSET: 0.8V, 1.0V, 1.2V, 1.5V, 1.8V, 2.5V, 3.0V, 3.3V - SDI: 0.72V to 3.63V • LDO regulator: 1V to 5V ̈ ̈ 210µA quiescent current (including 50µA for the feedback resistors) 2MHz (typical) switching frequency Use small and low profile inductors Stable with Low-ESR ceramic output capacitor Up to 95% efficiency Built-in under voltage lockout and over voltage protection and thermal shutdown Soft start to minimize the in-rush current One wire serial interface ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ Smart phones PDA’s Digital cameras ̈ ̈ ̈ Figure 1: Typical Application Circuit U1 VOUT2 C3 4.7uF/6.3V R1 30.1KOhm FBLDO 1 2 R2 20.0KOhm VIN 3 4 5 88PG8218 VIN VLDO SVIN FBLDO VSET ENLDO PFM EN / SDI SGND PG SFB 12 C1 0.1uF/10V 11 VSET 10 PFM 9 8 EN/SDI PG R3 2.0uH C4 10uF/6.3V Caution! 6 SW PVIN 13 L2 VOUT1 PGND 1MOhm 7 VIN C2 10uF/6.3V This is a very high frequency device, and proper PCB layout is required. Refer to Section 6, Application Information, on page 51 for further information. Copyright © 2009 Marvell July 31, 2009, 3.0 Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 3 88PG8218 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S105108-01 Rev. D Page 4 Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 Table of Contents Table of Contents Table of Contents ....................................................................................................................................... 5 List of Figures............................................................................................................................................. 7 List of Tables .............................................................................................................................................. 9 1 Signal Description ....................................................................................................................... 11 1.1 Pin Configuration.............................................................................................................................................11 1.2 Pin Descriptions ..............................................................................................................................................11 2 Electrical Specifications ............................................................................................................. 15 2.1 Absolute Maximum Ratings ............................................................................................................................15 2.2 Recommended Operating Conditions .............................................................................................................16 2.3 Electrical Characteristics .................................................................................................................................17 2.4 Switching Step-down Regulator ......................................................................................................................18 2.5 LDO Regulator ................................................................................................................................................21 3 Functional Description................................................................................................................ 23 3.1 Overview .........................................................................................................................................................23 3.2 Output Voltage Setting ....................................................................................................................................24 3.2.1 Serial Programmability of Switching Regulator (SDI) .......................................................................24 3.2.2 Logic Programmability ......................................................................................................................25 3.2.3 Programmability of Switching Regulator with AnyVoltage™ Technology (VSET) ............................26 3.2.4 LDO Regulator Voltage Set ..............................................................................................................27 3.3 Switching Regulator Enable and Serial Data Input (EN/SDI) ..........................................................................27 3.4 LDO Regulator Enable (ENLDO) ....................................................................................................................27 3.5 PFM or PWM Mode Selection .........................................................................................................................27 3.6 Under Voltage Lockout (UVLO) ......................................................................................................................27 3.7 Over Voltage Protection (OVP) .......................................................................................................................28 3.8 Thermal Shutdown ..........................................................................................................................................29 3.9 Power Good (PG)............................................................................................................................................29 4 Functional Characteristics ......................................................................................................... 31 4.1 Start-up Waveforms ........................................................................................................................................31 4.2 Short-Circuit Waveform ...................................................................................................................................33 4.3 Switching Waveforms......................................................................................................................................34 4.4 Load Transient Waveforms .............................................................................................................................36 4.4.1 Step-Down Regulator .......................................................................................................................36 5 Typical Characteristics ............................................................................................................... 39 5.1 Efficiency .........................................................................................................................................................39 Copyright © 2009 Marvell July 31, 2009, 3.0 Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 5 88PG8218 Datasheet 5.2 Load Regulation ..............................................................................................................................................40 5.2.1 Step-Down Regulator .......................................................................................................................40 5.2.2 LDO Regulator ..................................................................................................................................40 5.3 LDO Regulator Dropout ..................................................................................................................................41 5.4 RDS (ON) Resistance .....................................................................................................................................42 5.5 IC Case and Inductor Temperature.................................................................................................................43 5.6 Input Voltage ...................................................................................................................................................44 5.6.1 Step-Down Regulator .......................................................................................................................45 5.6.2 LDO Regulator ..................................................................................................................................46 5.7 Temperature....................................................................................................................................................47 5.7.1 Step-Down Regulator .......................................................................................................................48 5.7.2 LDO Regulator ..................................................................................................................................49 6 Application Information .............................................................................................................. 51 6.1 PC Board Layout Considerations and Guidelines ...........................................................................................51 6.1.1 PC Board Layout Examples..............................................................................................................53 6.2 Bill of Materials ................................................................................................................................................55 7 Mechanical Drawings .................................................................................................................. 57 7.1 Mechanical Drawings ......................................................................................................................................57 7.2 Typical Pad Layout Dimensions ......................................................................................................................58 7.2.1 Recommended Solder Pad Layout ...................................................................................................58 8 Part Order Numbering/Package Marking .................................................................................. 59 8.1 Part Order Numbering Scheme.......................................................................................................................59 8.2 Part Ordering Options .....................................................................................................................................59 8.3 Package Marking ............................................................................................................................................60 A Revision History .......................................................................................................................... 61 Doc. No. MV-S105108-01 Rev. D Page 6 Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 List of Figures List of Figures Figure 1: 1 Typical Application Circuit...................................................................................................................3 Signal Description ........................................................................................................................... 11 Figure 2: DFN-12 Pin Diagram (Top View) ......................................................................................................11 2 Electrical Specifications ................................................................................................................. 15 3 Functional Description.................................................................................................................... 23 4 Figure 3: 88PG8218 Block Diagram ................................................................................................................23 Figure 4: Serial Programmability......................................................................................................................24 Figure 5: Startup Sequence .............................................................................................................................27 Figure 6: Soft Startup.......................................................................................................................................27 Figure 7: UVLO and OVP Waveforms .............................................................................................................28 Figure 8: Power Good Operating Waveform....................................................................................................29 Functional Characteristics.............................................................................................................. 31 Figure 9: 5 Startup Using the Enable Pin ...........................................................................................................31 Figure 10: Turn Off Using the Enable Pin ..........................................................................................................31 Figure 11: Soft Start Input Voltage.....................................................................................................................32 Figure 12: Hot Plug Input Voltage ......................................................................................................................32 Figure 13: UVLO & OVP Thresholds .................................................................................................................32 Figure 14: Step-Down Short-Circuit ...................................................................................................................33 Figure 15: PWM Mode ......................................................................................................................................34 Figure 16: DCM Mode .......................................................................................................................................34 Figure 17: PWM Output Ripple Voltage ............................................................................................................35 Figure 18: Fast Load Rise Time ........................................................................................................................36 Figure 19: Slow Load Rise Time ........................................................................................................................36 Figure 20: Fast Load Fall Time .........................................................................................................................36 Figure 21: Slow Load Fall Time .........................................................................................................................36 Figure 22: Load Transient Response.................................................................................................................37 Typical Characteristics ................................................................................................................... 39 Figure 23: Efficiency vs. Output Current ............................................................................................................39 Figure 24: Efficiency vs. Output Current in Log Scale .......................................................................................39 Figure 25: Output Voltage vs. Output Current ...................................................................................................40 Figure 26: Output Voltage vs. Output Current ...................................................................................................40 Figure 27: Regulator Dropout vs. Load Current .................................................................................................41 Figure 28: Resistance vs. Input Voltage ............................................................................................................42 Figure 29: Resistance vs. Temperature .............................................................................................................42 Figure 30: Input Current vs. Output Current ......................................................................................................43 Figure 31: IC Case Temperature vs. Output Current .........................................................................................43 Copyright © 2009 Marvell July 31, 2009, 3.0 Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 7 88PG8218 Datasheet Figure 32: 6 7 8 Inductor Temperature vs. Output Current .........................................................................................43 Figure 33: Supply Current vs. Input Voltage ......................................................................................................44 Figure 34: Shutdown Supply Current vs. Input Voltage .....................................................................................44 Figure 35: Enable Threshold vs. Input Voltage ..................................................................................................44 Figure 36: Output Voltage vs. Input Voltage ......................................................................................................45 Figure 37: Efficiency vs. Input Voltage...............................................................................................................45 Figure 38: Load Regulation vs. Input Voltage ....................................................................................................45 Figure 39: Frequency vs. Input Voltage .............................................................................................................45 Figure 40: Avgerage Output Current Limit vs. Input Voltage .............................................................................45 Figure 41: Output Voltage vs. Input Voltage ......................................................................................................46 Figure 42: Load Regulation vs. Input Voltage ....................................................................................................46 Figure 43: Avgerage Output Current Limit vs. Input Voltage .............................................................................46 Figure 44: Supply Current vs. Temperature.......................................................................................................47 Figure 45: UVLO Threshold vs. Temperature ....................................................................................................47 Figure 46: OVP Threshold vs. Temperature ......................................................................................................47 Figure 47: Enable Threshold vs. Temperature ..................................................................................................47 Figure 48: Shutdown Supply Current vs. Temperature......................................................................................47 Figure 49: Output Voltage vs. Temperature.......................................................................................................48 Figure 50: Efficiency vs. Temperature ...............................................................................................................48 Figure 51: Load Regulation vs. Temperature ....................................................................................................48 Figure 52: Line Regulation vs. Temperature......................................................................................................48 Figure 53: Frequency vs. Temperature..............................................................................................................48 Figure 54: Average Output Current Limit vs. Temperature ................................................................................48 Figure 55: Output Voltage vs. Temperature.......................................................................................................49 Figure 56: Load Regulation vs. Temperature ....................................................................................................49 Figure 57: Line Regulation vs. Temperature......................................................................................................49 Figure 58: Average Output Current Limit vs. Temperature ................................................................................49 Application Information .................................................................................................................. 51 Figure 59: PCB Board Schematic ......................................................................................................................52 Figure 60: Top Silk-Screen, Top Traces, Vias, and Copper (Not to Scale) .......................................................53 Figure 61: Bottom Silk-Screen, Bottom Trace, Vias, and Bottom Copper (Not to Scale) ..................................54 Mechanical Drawings ...................................................................................................................... 57 Figure 62: 3mm x 4mm 12-Lead DFN Mechanical Drawing ..............................................................................57 Figure 63: 3mm x 4mm DFN-12 Land Pattern (mm)..........................................................................................58 Part Order Numbering/Package Marking....................................................................................... 59 Figure 64: Sample Part Number ........................................................................................................................59 Figure 65: Package Marking and Pin 1 Location ...............................................................................................60 Doc. No. MV-S105108-01 Rev. D Page 8 Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 List of Tables List of Tables 1 2 3 Signal Description ............................................................................................................................ 11 Table 1: Pin Types..........................................................................................................................................11 Table 2: Pin Descriptions ................................................................................................................................12 Electrical Specifications .................................................................................................................. 15 Table 3: Absolute Maximum Ratings ..............................................................................................................15 Table 4: Recommended Operating Conditions...............................................................................................16 Table 5: Electrical Characteristics ..................................................................................................................17 Table 6: Switching Step-down Regulator........................................................................................................18 Table 7: LDO Regulator ..................................................................................................................................21 Functional Description..................................................................................................................... 23 Table 8: Default Value of Data Field ...............................................................................................................25 Table 9: Voltage and Percent Set ...................................................................................................................25 Table 10: Switching Regulator Output Voltages (V) Programmed by SDI........................................................25 Table 11: VSET Programming ..........................................................................................................................26 Table 12: Switching Regulator Output Voltage Programmed by VSET Resistor..............................................26 4 Functional Characteristics............................................................................................................... 31 5 Typical Characteristics .................................................................................................................... 39 6 Application Information ................................................................................................................... 51 Table 13: BOM..................................................................................................................................................55 7 Mechanical Drawings ....................................................................................................................... 57 8 Part Order Numbering/Package Marking........................................................................................ 59 Table 14: Part Ordering Options .......................................................................................................................59 Table 15: Revision History ................................................................................................................................61 Copyright © 2009 Marvell July 31, 2009, 3.0 Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 9 88PG8218 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S105108-01 Rev. D Page 10 Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 Signal Description Pin Configuration 1 Signal Description 1.1 Pin Configuration Figure 2: DFN-12 Pin Diagram (Top View) VLDO 1 12 SVIN FBLDO 2 11 VSET ENLDO 3 1.2 10 PFM SGND 4 9 EN/SDI SFB 5 8 PG SW 6 13 PGND 7 PVIN Pin Descriptions . Table 1: Pin Types Pi n Typ e D e f in it io n I Input Only O Output Only S Supply NC Not Connected GND Ground Copyright © 2009 Marvell July 31, 2009, 3.0 Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 11 88PG8218 Datasheet Table 2: Pin Descriptions Pi n Number P in N a m e P in Ty pe P in F u nc t io n 1 VLDO O LDO Output • Connect a ceramic capacitor from VLDO to ground. SeeSection 6, Application Information for the recommended value. 2 FBLDO I LDO Feedback • Connect directly to VLDO output if desired LDO voltage is 1V. • Connect to LDO output through a resistor divider if desired LDO voltage is higher than 1V. 3 ENLDO I LDO Enable • Logic high enables the LDO regulator. • Logic low disables the LDO regulator. When EN/SDI is low and ENLDO is high, the LDO is disabled. See Table 5, Electrical Characteristics, on page 17 for detailed logic high and logic low specifications. • Do not float this pin. 4 SGND GND 5 SFB I Switching Regulator Output Voltage Sense Feedback • Senses the output voltage of the switching regulator. • Connect to the output capacitor of the switching regulator. 6 SW O Switch Node • Internally connected to the drains of the high side and low side MOSFETs. • Connect to the external inductor. 7 PVIN S Switching Regulator Power Input • Power input voltage. Internally connected to the source of the high side MOSFET. Connect a ceramic capacitor between PVIN and PGND and place it as close as possible to PVIN and PGND pins. See Section 6, Application Information for further reference. • The voltage between SVIN and PVIN should equal to 50mV or less. 8 PG O Switching Regulator Power Good Output • It is an open-drain output. • Connect a 1MΩ pull-up resistor from this pin to VOUT or a logic rail that is equal to or less than SVIN. • The PG is held low when the output voltage is outside its regulation band and goes high after the output voltage is within regulation. • In shutdown, the PG will be actively on. Signal Ground • This pin must be connected to PGND and make a star connection to system ground. Doc. No. MV-S105108-01 Rev. D Page 12 Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 Signal Description Pin Descriptions Table 2: Pin Descriptions Pi n Number P in N a m e P in Ty pe P in F u nc t io n 9 EN/SDI I Enable / Serial Data Input • Logic high enables the switching step-down regulator. In shutdown, the switch node for the step-down regulator is high impedance. Logic low disables the step-down switching and LDO regulators. • The low signal has to be at least 20ms to disable the switching regulator. See Table 5, Electrical Characteristics, on page 17 for detailed logic high and logic low specifications. • EN must be kept high to enable the shutdown function. • It also serves as a serial data input when it is connected to a programming device. The input data to this pin is used to program the output voltage. See Section 3.2.1, Serial Programmability of Switching Regulator (SDI), on page 24. • Do not share this pin with other serial interface pins. • Do not float this pin. 10 PFM I Pulse Frequency Modulation • Logic input to set the operation mode. Connect PFM to SVIN to select PFM mode under light load conditions and connect PFM to SGND to select forced PWM mode in light load condition. • Do not float this pin 11 VSET I Switching Regulator Voltage Set To set the nominal output voltage values: • Connect VSET to SVIN or GND to set two nominal output voltages. • Connect a resistor from VSET to GND to set eight nominal output voltages. See Table 12, Switching Regulator Output Voltage Programmed by VSET Resistor, on page 26 for resistor values and Output Voltage Settings. • The total capacitance across this pin and SGND must be 25pF or less. Use resistor values with a 5% tolerance or better. • Do not float this pin. 12 SVIN S Signal Input Voltage • Input voltage to the internal circuitry. SeeTable 5, Electrical Characteristics, on page 17 for input voltage range. • Connect a decoupling capacitor between SVIN an SGND and position it as close as possible to the IC. See Section 6, Application Information for further reference. • The voltage between SVIN and PVIN should equal to 50mV or less. 13 PGND GND Power Ground • It must connect to the negative terminals of the input and output capacitors. Copyright © 2009 Marvell July 31, 2009, 3.0 Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 13 88PG8218 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S105108-01 Rev. D Page 14 Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 Electrical Specifications Absolute Maximum Ratings 2 Electrical Specifications 2.1 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings1 Note: Stesses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter Range U n its VPVIN to PGND -0.3 to 6.0 V VPVIN to VSVIN -0.3 to +0.3 V PGND to SGND -0.3 to +0.3 V 2 -0.3 to (VPVIN +0.3) V VSFB to SGND -0.3 to (VSVIN +0.3) V VFBLDO to SGND -0.3 to (VSVIN +0.3) V VLDO to SGND -0.3 to (VSVIN +0.3) V VEN/SDI, VSET, VPFM and VENLDO to SGND -0.3 to (VSVIN +0.3) V VPG to SGND -0.3 to (VSVIN +0.3) V -40 to 85 C 150 C -65 to +150 C VSW to PGND Operating Ambient Temperature Range3 Maximum Junction Temperature Storage Temperature Range 1. Exceeding the absolte maximum ratings may damage the device. 2. Capable of -1.0V for less than 50ns and 7V for less than 200ns. 3. Specifications over the -40 C to 85 C operating temperature ranges are assured by design, characterization and correlation with statistical process controls. Copyright © 2009 Marvell July 31, 2009, 3.0 Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 15 88PG8218 Datasheet 2.2 Recommended Operating Conditions Table 4: S y m bo l Recommended Operating Conditions1 Parameter VSVIN Signal Input Voltage VPVIN Power Input Voltage θJA Min Package Thermal Resistance Max U n i ts 2.7 5.5 V 2.7 5.5 V 2 θJC TJMAX Ty p 48.1 C/W 4.4 Operating Junction Temperature C/W 125 C 1. This device is not guaranteed to function outside the specified operating range. 2. Tested on 4-Layer (JESD51-7) and vias (JESD51-5) boards. Doc. No. MV-S105108-01 Rev. D Page 16 Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 Electrical Specifications Electrical Characteristics 2.3 Table 5: Electrical Characteristics Electrical Characteristics The following applies unless otherwise noted. Refer to schematic shown in Figure 1. VSVIN = VPVIN = VEN = VENLDO = 3.6V, VPFM =GND, SGND = PGND = GND, VBUCK = 1.5V, VLDO = 2.5V, TA = 25 C. Bold values indicate -40 C ≤ TA ≤ 85 C. Sy m b o l P a r a m e te r C o nd i ti on s M in VSVIN Signal Input Voltage VSVIN = VPVIN VPVIN Power Input Voltage VSVIN = VPVIN IQ_PFM Total Quiescent Current (PFM Mode) No Load VPFM = VSVIN = VPVIN 105 IQ_PWM Total Quiescent Current (PWM Mode) No Load VPFM = VSGND 5 ISHDN Shutdown Supply Current VEN/SDI = VENLDO = 0V 1 10 μA VUVLO Under Voltage Lockout High Threshold, VSVIN increasing 2.6 2.7 V 5.95 V Low Threshold, VSVIN decreasing VOVP Over Voltage Protection VIH VIL IEN Over Temperature Shutdown EN, ENLDO and PFM Input Voltage Threshold Enable Input Current Enable LDO Input Current IPFM PFM Input Current 5.5 V 2.7 5.5 V 315 μA 210 mA 2.5 5.85 5.5 5.75 147 TJ decreasing (Enable regulators) 105 Logic high 1.4 Logic low 0.4 VEN = 3.6V -10 -10 VPFM = 0V Copyright © 2009 Marvell V 10 μA μA 10 1 μA μA 1 1 -10 1.6 1 1 VPFM = 3.6V C 0.8 1 VENLDO = 3.6V VENLDO = 0V July 31, 2009, 3.0 2.7 TJ increasing (Disable regulators) VEN = 0V IENLDO Units High Threshold, VSVIN increasing Low Threshold, VSVIN decreasing TOTS Max 2.4 Ty p 10 μA μA Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 17 88PG8218 Datasheet 2.4 Table 6: Switching Step-down Regulator Switching Step-down Regulator The following applies unless otherwise noted. Refer to schematic shown in Figure 1. VSVIN = VPVIN = VEN = VENLDO = 3.6V, VPFM =GND, SGND = PGND = GND, VBUCK = 1.5V, VLDO = 2.5V, TA = 25 C. Bold values indicate -40 C ≤ TA ≤ 85 C. Sy m b o l P a r a m e te r C o nd i ti on s VOUT Output Voltage RVSET = 11K, PFM mode, ILOAD = 10mA M in Ty p Max 0.8 Units V TA = 25 C -6 6 % Over Temperature -7 7 % RVSET = 18K, PFM mode, ILOAD = 10mA 1.0 V VVSET = SGND, PFM mode, ILOAD = 10mA TA = 25 C -6 6 % Over Temperature -7 7 % RVSET = 30K, PFM mode, ILOAD = 10mA 1.2 V TA = 25 C -6 6 % Over Temperature -7 7 % RVSET = 51K, PFM mode, ILOAD = 10mA 1.5 V TA = 25 C -6 6 % Over Temperature -7 7 % RVSET = 100K, PFM mode, ILOAD = 10mA 1.8 V VVSET = VSVIN, PFM mode, ILOAD = 10mA TA = 25 C -6 6 % Over Temperature -7 7 % RVSET = 160K, PFM mode, ILOAD = 10mA 2.5 TA = 25 C -6 6 % Over Temperature -7 7 % RVSET = 270K, PFM mode, ILOAD = 10mA 3.0 V TA = 25 C -6 6 % Over Temperature -7 7 % RVSET = 470K, PFM mode, ILOAD = 10mA 3.3 V TA = 25 C -6 6 % Over Temperature -7 7 % Doc. No. MV-S105108-01 Rev. D Page 18 V Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 Electrical Specifications Switching Step-down Regulator Table 6: Switching Step-down Regulator The following applies unless otherwise noted. Refer to schematic shown in Figure 1. VSVIN = VPVIN = VEN = VENLDO = 3.6V, VPFM =GND, SGND = PGND = GND, VBUCK = 1.5V, VLDO = 2.5V, TA = 25 C. Bold values indicate -40 C ≤ TA ≤ 85 C. Sy m b o l P a r a m e te r C o nd i ti on s VOUT Output Voltage RVSET = 11K, PWM mode, ILOAD = 100mA M in Ty p Max 0.8 Units V TA = 25 C -3.5 3.5 % Over Temperature -4.5 4.5 % RVSET = 18K, PWM mode, ILOAD = 100mA 1.0 V VVSET = SGND, PWM mode, ILOAD = 100mA TA = 25 C -3.0 3.0 % Over Temperature -4.0 4.0 % RVSET = 30K, PWM mode, ILOAD = 100mA 1.2 V TA = 25 C -3.0 3.0 % Over Temperature -4.0 4.0 % RVSET = 51K, PWM mode, ILOAD = 100mA 1.5 V TA = 25 C -3.0 3.0 % Over Temperature -4.0 4.0 % RVSET = 100K, PWM mode, ILOAD = 100mA 1.8 V VVSET = VSVIN, PWM mode, ILOAD = 100mA TA = 25 C -3.0 3.0 % Over Temperature -4.0 4.0 % 2.5 RVSET = 160K, PWM mode, ILOAD = 100mA TA = 25 C -3.0 3.0 % Over Temperature -4.0 4.0 % 3.0 RVSET = 270K, PWM mode, ILOAD = 100mA Output Voltage Line Regulation TA = 25 C -3.0 3.0 % -4.0 4.0 % 3.3 V TA = 25 C -3.0 3.0 % Over Temperature -4.0 4.0 % VPVIN = 2.7V to 4.2V, ILOAD = 600mA Copyright © 2009 Marvell July 31, 2009, 3.0 V Over Temperature RVSET = 470K, PWM mode, ILOAD = 100mA VLNREG V 0.2 % Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 19 88PG8218 Datasheet Table 6: Switching Step-down Regulator The following applies unless otherwise noted. Refer to schematic shown in Figure 1. VSVIN = VPVIN = VEN = VENLDO = 3.6V, VPFM =GND, SGND = PGND = GND, VBUCK = 1.5V, VLDO = 2.5V, TA = 25 C. Bold values indicate -40 C ≤ TA ≤ 85 C. Sy m b o l P a r a m e te r C o nd i ti on s VLDREG Output Voltage Load Regulation VPVIN = 3.6V, ILOAD = 300mA to 1.2A RDSON_HS High Side Switch On Resistance VPVIN = 5V 96 192 288 VPVIN = 3.6V 110 220 330 VPVIN = 5V 72 143 215 VPVIN = 3.6V 80 160 240 1.5 1.8 RDSON_LS Low Side Switch On Resistance M in Ty p Max 1.4 Units % mΩ mΩ ILIM Minimum Peak Switch Current Limit ILSW_HS High Side Switch Leakage Current VPVIN = VSVIN = 5V, VEN = PGND, VSW = 5V 1 10 μA ILSW_LS Low Side Switch Leakage Current VPVIN = VSVIN = 5V, VSW = VEN = PGND 1 10 μA fSW Switching Frequency PWM mode 2 MHz DMAX Maximum Duty Cycle 100 % THICCUP Hiccup Mode Time Interval 2 ms tDEGLITCH Deglitch 25 μs VPGTH Power Good (PG) Threshold Voltage VOUT × 90% V VPGL Maximum PG Output Low Voltage 0.4 V tDELAY PG Delay Time IPG PG Leakage Current ISINK = 2mA, VEN = VSVIN μs 120 VEN = 0V Doc. No. MV-S105108-01 Rev. D Page 20 A 1 5 μA Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 Electrical Specifications LDO Regulator 2.5 Table 7: LDO Regulator LDO Regulator The following applies unless otherwise noted. Refer to schematic shown in Figure 1. VSVIN = VPVIN = VEN = VENLDO = 3.6V, VPFM =GND, SGND = PGND = GND, VBUCK = 1.5V, VLDO = 2.5V, TA = 25 C. Bold values indicate -40 C ≤ TA ≤ 85 C. Sy m b o l P a r a m e te r C o nd i ti on s VFBLDO LDO Feedback Voltage VSDI = VSVIN TA = 25 C Over Temperature M in Ty p Max Units -2 2 % -2.5 2.5 % 1 10 μA 1 V IFBLDO LDO Feedback Input Bias Current VLNREGLDO LDO Output Voltage Line Regulation VPVIN = 2.7V to 4.2V, ILOAD = 10mA 0.2 1 % VLDREGLDO LDO Output Voltage Load Regulation VPVIN = 3.6V, ILOAD = 10mA to 200mA 0.6 2.5 % VLDO_DROP LDO Drop Out Voltage ILOAD = 200mA, VOUT = 3V 60 ILOAD_MAX Maximum LDO Current 200 Copyright © 2009 Marvell July 31, 2009, 3.0 mV mA Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 21 88PG8218 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S105108-01 Rev. D Page 22 Copyright © 2009 Marvell Document Classification: Proprietary July 31, 2009, 3.0 Functional Description Overview 3 Functional Description 3.1 Overview The 88PG8218 is a high performance companion power management regulator for Marvell's SoCs as well as general purpose power management regulator for portable applications. It includes a switching regulator and a Low Dropout (LDO) regulator. The switching regulator utilizes a proprietary internally compensated PWM control to regulate the output voltage, which offers fast transient response and requires no external compensation. The 88PG8218 operates from 2.7V to 5.5V input voltage range. The step-down switching regulator can deliver up to 1.2A output current while the LDO is capable of sourcing up to 200mA. The switching regulator output can be programmed from 0.72V to 3.63V through the SDI input, and from 0.8V to 3.3V through the VSET resistor. The LDO output can be programmed from 1V to 5V by a resistor divider. The typical switching frequency is 2 MHz, allowing the use of low profile surface mounted inductors and low value capacitors. The switching regulator can achieve typically 95% efficiency under loaded condition. Figure 3: 88PG8218 Block Diagram VIN SVIN C1 REGISTRY & DETECTION CIRCUITRY EN /SDI INTERNAL CIRCUITRY POWER SUPPLY ON OFF OSCILLATOR & SWITCHING FREQUENCY CALIBRATION LDO VLDO FBLDO CURRENT SENSE + ON PVIN - C2 ERROR AMPLIFIER + PFM SW PWM CONTROL - C3 R3 ENLDO OFF V LDO R4 L1 V OUT C4 PFM PGND PWM FAULT THERMAL SHUTDOWN BAND-GAP VOLTAGE REFERENCE SGND UNDER/ OVER VOLTAGE LOCKOUT SFB RESISTOR NETWORK RESISTOR SENSING CIRCUITRY R2 PG Power Good PG VSET R1 Copyright © 2009 Marvell July 31, 2009, 3.0 Doc. No. MV-S105108-01 Rev. D Document Classification: Proprietary Page 23 88PG8218 Datasheet 3.2 Output Voltage Setting 3.2.1 Serial Programmability of Switching Regulator (SDI) The output voltage of the step-down switching regulator can be programmed by using serial data into the Serial Data Input (SDI) pin. Caution: Do not share the PWM pin with other serial interface pins. Figure 4: Serial Programmability WRITE MODE Stop Start Chip Select "1" Pulse "1" "0" pulse Pulse "0" pulse Register Address "1" Pulse "0" "0" pulse pulse The period of a pulse is 1μ s +/- 200 ns V HIGH >V IH VLow < V IL DATA FIELD "1" "0" Pulse pulse "1" Pulse D7 D6 D5 D4 D3 D2 D1 D0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 "0 " pulse The write operation: V LOW 1 ) Each write sequence needs 18 pulses to complete. 2 ) During a non- write operation , the input needs to be at V LOW (