Transcript
88PG877 Family Field Programmable DSP Switcher™ 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology Advance Datasheet, Patent Pending
Doc. No. MV-S103181-00, Rev. B October 30, 2007
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Document Status Advance Information
This document contains design specifications for initial product development. Specifications may change without notice. Contact Marvell Field Application Engineers for more information.
Preliminary Information
This document contains preliminary data, and a revision of this document will be published at a later date. Specifications may change without notice. Contact Marvell Field Application Engineers for more information.
Final Information
This document contains specifications on a product that is in final release. Specifications may change without notice. Contact Marvell Field Application Engineers for more information.
Revision Code:
Rev. B
Advance
Technical Publication: 0.2
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright © 2007. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners.
Doc. No. MV-S103181-00 Rev. B Page 2
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October 30, 2007, Advance
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
O VERVIEW
F EATURES
The 88PG877 device intelligent digital synchronous Step-Down (Buck) switching regulator housed in a 4 X 3 mm QFN-18 package. Internally self-compensated, these step-down regulators require no external compensation and work with low-ESR output capacitors to simplify the design, minimize board space, and reduce the amount of external components. The switching frequency for the step-down regulator is 1 MHz, allowing the use of low profile surface mount inductors and low value capacitors. The step-down regulator includes programmable output voltage to provide the user the ability to easily set the output voltage with external resistors, logic control, or serial data interface. The output voltage range is 0.72V to 3.63V.
• • • • • • • • • •
Other key features of the 88PG877 family include soft start, an internal current limit, an undervoltage lockout, thermal shutdown, over voltage protection, and a Power-On Reset (POR) signal.
• • • • • •
Tiny 4 X 3 mm QFN-18 package 1 MHz Switching frequency Low quiescent current of mA (typ.) Stable with ceramic output capacitors No external compensation required Over 95% efficiency Peak switch current limit up to 7.5A Input voltage range: 3.0V to 5.5V Serial / Logic Programmability Any Voltage™ Technology provides 64 output voltage selections to provide flexibility Programmable output voltage range: – 0.72V to 3.63V Built-in undervoltage lockout Over voltage protection Thermal shutdown protection Output voltage margining capability
A PPLICATION • • •
Portable computing Disk drive power supplies
R1 10 ohm
SDI
1 18 R3 11K
R5 0
13
7 PVIN
6 PVIN
SW 88PG877
SW
VSET
SW
PSET
SW
SGND
9
R6 10K
POR SDI
C4 22uF/6.3V
3 C2 47nF
PGND
16
VBS
C3 22uF/6.3V
SFB
4 L1
Vout 0.8V/5A
8 1.0uH 12 19
C5 22uF/6.3V
C6 22uF/6.3V
14
11
POR
C7 4.7uF/6.3V
EN
PGND
2 17
SVIN
10
15
5
U1
PVIN
C1 0.1uF
PGND
R2 100K
Vin 3.0V - 5.5V
Figure 1: Typical High Efficiency 5V to 0.8V/5A Step-Down Regulator
Caution
Copyright © 2007 Marvell October 30, 2007, Advance
Doc. No. MV-S103181-00, Rev. B Document Classification: Proprietary Information
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Table of Contents SECTION 1.
SIGNAL DESCRIPTION ................................................................... 9
1.1
Pin Configuration ...........................................................................................................9
1.2
Pin Type Definitions .....................................................................................................10
1.3
Pin Description .............................................................................................................10
SECTION 2.
ELECTRICAL SPECIFICATIONS ..................................................... 12
2.1
Absolute Maximum Ratings ........................................................................................12
2.2
Recommended Operating Conditions ........................................................................12
2.3
Electrical Characteristics.............................................................................................13
2.4
Switching Step-down Regulator .................................................................................14
SECTION 3. 3.1
Regulation and Start-up...............................................................................................16 3.1.1
3.2
FUNCTIONAL DESCRIPTION ......................................................... 16 Digital Soft Start................................................................................................................ 17
Output Voltage Setting.................................................................................................19 3.2.1 3.2.2 3.2.3
Serial Programmability ..................................................................................................... 19 Logic Programmability ...................................................................................................... 21 Output Voltage – AnyVoltageTM Technology ................................................................... 21
3.3
Undervoltage Lockout (UVLO) ....................................................................................24
3.4
Over Voltage Protection (OVP)....................................................................................24
3.5
Power-On Reset (POR).................................................................................................25
3.6
Thermal Shutdown .......................................................................................................25
3.7
Adaptive Transient Response .....................................................................................26
SECTION 4.
FUNCTIONAL CHARACTERISTICS ................................................. 27
4.1
Start-up Waveforms .....................................................................................................27
4.2
Short-Circuit Waveforms .............................................................................................28
4.3
Switching Waveforms ..................................................................................................29
4.4
Load Transient Waveforms .........................................................................................31 4.4.1
Step-Down Regulator ....................................................................................................... 31
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4.5
Output Voltage Transient Waveforms........................................................................ 33 4.5.1
4.6
Step-Down Regulator ....................................................................................................... 33
Line Transient Waveforms .......................................................................................... 34
SECTION 5. 5.1
TYPICAL CHARACTERISTICS ........................................................35
Efficiency Graphs ........................................................................................................ 35 5.1.1
Efficiency Graphs in log scale .......................................................................................... 35
5.2
Load Regulation ........................................................................................................... 35
5.3
Dropout Voltage ........................................................................................................... 36
5.4
RDS (ON) Resistance................................................................................................... 36
5.5
IC Case and Inductor Temperature ............................................................................ 37
5.6
Input Voltage Graphs................................................................................................... 38 5.6.1
5.7
Step-Down Regulator ....................................................................................................... 39
Temperature Graphs.................................................................................................... 40 5.7.1
Step-Down Regulator ....................................................................................................... 41
SECTION 6. 6.1
APPLICATIONS INFORMATION ......................................................42
PC Board Layout Considerations and Guidelines for 88PG877 .............................. 42 6.1.1 6.1.2
PC Board Layout Examples for 88PG877........................................................................ 45 Bill of materials for 88PG877............................................................................................ 47
SECTION 7.
MECHANICAL DRAWING ..............................................................49
7.1
88PG877 Mechanical Drawing .................................................................................... 49
7.2
88PG877 Mechanical Dimensions .............................................................................. 50
7.3
Typical Pad Layout Dimensions ................................................................................. 51 7.3.1
Recommended Solder Pad Layout .................................................................................. 51
SECTION 8.
ORDERING INFORMATION ............................................................52
8.1
Ordering Part Numbers and Package Markings ....................................................... 52
8.2
Sample Ordering Part Number ................................................................................... 52
8.3
Package Marking.......................................................................................................... 53 8.3.1
88PG877 Package Marking and Pin 1 Locations............................................................. 53
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11:
Pin Type Definitions.............................................................................................................................. 10 Pin Description ..................................................................................................................................... 10 Default Value of Data Field................................................................................................................... 20 Voltage and Percentage Set................................................................................................................. 20 Output Voltage Setting ......................................................................................................................... 21 Any Voltage Programming Table ......................................................................................................... 22 Any Voltage Programming Table for 5% Resistors .............................................................................. 22 Output Voltage Option Steps................................................................................................................ 23 88PG877 BOM ..................................................................................................................................... 47 Ceramic Capacitor Cross Reference .................................................................................................... 48 88PG877 Ordering Part Numbers ........................................................................................................ 52
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List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40:
Typical High Efficiency 5V to 0.8V/5A Step-Down Regulator ............................................................... 3 88PG877 Family 4X3 mm QFN-18 Package - Top View...................................................................... 9 88PG877 Block Diagram .................................................................................................................... 16 Output Voltage Window ...................................................................................................................... 17 Soft Startup......................................................................................................................................... 18 Soft Startup......................................................................................................................................... 18 Inductor Current Steps at Startup ....................................................................................................... 18 First Switching Cycle .......................................................................................................................... 18 Serial Programmability........................................................................................................................ 19 Startup Sequence .............................................................................................................................. 23 ............................................................................................................................................................ 23 UVLO and OVP Waveforms ............................................................................................................... 24 Power-On Reset Waveforms .............................................................................................................. 25 Adaptive Transient Response ............................................................................................................ 26 Startup Using the Enable Pin ............................................................................................................. 27 Turn Off Using the Enable Pin ............................................................................................................ 27 Soft Start ............................................................................................................................................ 27 Hot Plug .............................................................................................................................................. 27 UVLO and OVP Thresholds................................................................................................................ 28 Step-Down Short-Circuit Response ................................................................................................... 28 Switching Waveforms - PWM mode .................................................................................................. 29 Switching Waveforms - DCM Mode ................................................................................................... 29 Switching Waveforms - DCM Mode-Zoom ......................................................................................... 29 PWM Output Ripple Voltage ........................................................................................................... 30 Fast Load Rise Time .......................................................................................................................... 31 Slow Load Rise Time.......................................................................................................................... 31 Fast Load Fall Time ........................................................................................................................... 31 Slow Load Fall Time ........................................................................................................................... 31 Load Transient Response .................................................................................................................. 32 Double-Pulsed Load Response .......................................................................................................... 32 Load Transient Response .................................................................................................................. 32 Double-Pulsed Load Response .......................................................................................................... 32 VOUT = 1.0V to 1.2V with No Load .................................................................................................... 33 VOUT = 1.0V to 1.5V with No Load ..................................................................................................... 33 VOUT = 1.0V to 1.2V with ILOAD = 5A.................................................................................................. 33 VOUT = 1.0V to 1.5V with ILOAD = 5A.................................................................................................. 33 VOUT = 1.2V to 1.0V with ILOAD = 5A.................................................................................................. 34 VOUT = 1.5V to 1.0V with ILOAD = 5A.................................................................................................. 34 Line Transient @ VIN = 3.2V to 3.6V .................................................................................................. 34 Line Transient @ VIN = 4.1V to 4.5V .................................................................................................. 34
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46:
PCB Layout......................................................................................................................................... 43 88PG877 PCB Board Schematic ........................................................................................................ 44 Top Silk-Screen, Top Traces, Vias and Copper (Not to scale) ........................................................... 45 Bottom Silk Screen, Bottom Traces, Vias, and Copper (Not to scale)................................................ 46 Sample Part Number .......................................................................................................................... 52 88PG877 Package Marking and Pin 1 Location ................................................................................. 53
Doc. No. MV-S103181-00 Rev. B Page 8
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Signal Description Pin Configuration
Section 1. Signal Description
1.1 Pin Configuration Figure 2: 88PG877 Family 4X3 mm QFN-18 Package - Top View PSET
PG
PWM
18
17
16
VSET
1
15
SVIN
EN
2
14
SFB
VBS
3
13
SGND
SW
4
12
SW
PVIN
5
11
PGND
10
PGND
SW
19 PVIN
6
7
8
9
PVIN
SW
PGND
88PG877 3x4 QFN-18
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
1.2 Pin Type Definitions Table 1:
Pin Type Definitions
P in Typ e
D ef in i t io ns
I
Input only
O
Output only
S
Supply
NC
Not Connected
GND
Ground
1.3 Pin Description Table 2 provides pin descriptions for the 88PG877.
Table 2:
Pin Description
Pin #
Pi n Na me
Pi n Ty pe
Pin Fu nc ti o n
1
VSET
I
Voltage Set 1) This is used for selecting the output voltage level, when it is connected to SGND or SVIN in conjunction with PSET connection to SGND or SVIN. 2) Connect to an external resistor to ground to set the output voltage of the step-down switching regulator. See the “Electrical Characteristics” table for resistor values and Output Voltage Setting section. The total capacitance across this pin and SGND should be equal to 25 pF or less. Use resistors with tolerance
2
EN
I
3
VBS
O
Bootstrap Voltage. Connect a 47 nF capacitor from this pin to SW.
4,8,12,
SW
O
Switch Node. Internal power MOSFET . This pin must connect to an external inductor.
5,6,7
PVIN
S
Power Input Voltage. Internal power MOSFET . Connect the decoupling capacitors between PVIN and PGND and position it as close as possible to the IC.
9,10,11
PGND
GND
Power Ground. The power ground must connect to the negative terminal of the input and output capacitors.
13
SGND
GND
Signal ground. This pin must connect to the power ground.
14
SFB
I
Switching Regulator Feedback. Senses the output voltage of the switching regulator.
Doc. No. MV-S103181-00 Rev. B Page 10
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Signal Description Pin Description
Table 2:
Pin Description (Continued)
Pin #
Pi n Na me
Pi n Ty pe
Pin Fu nc ti o n
15
SVIN
S
Signal Input Voltage. The input voltage is V to 5.5V for internal circuitry. Connect a 0.1 µF decoupling capacitor between SVIN and SGND and position it as close as possible to the IC.
16
SDI
I
Serial Data Input: The input data into this pin is used to program the output voltage (see section 3.2). This pin must be connected to ground if not used.
17
P
O
Power-On Reset. Power-On Reset is an open drain output to indicate the status of the output voltage. The output pin goes high 40 ms after the output voltage is within the specified tolerance.
18
PSET
I
Percent Set 1) This is used for selecting the output voltage level when it is connected to SGND or SVIN in conjunction with VSET connection to SGND or SVIN. 2) Connect an external resistor to ground to set the output voltage of the step-down switching regulator. See the “Electrical Characteristics” table for resistor values and Output Voltage Setting section. Use resistor value with tolerance
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Section 2. Electrical Specifications 2.1 Absolute Maximum Ratings1 Pa r a m e te r
Symbol
R a n ge
U n its
Signal Input Voltage
SVIN
-0.3 to 6.0
V
Power Input Voltage
PVIN
-0.3 to 6.0
V
Switch Voltage
VSW
-0.6 to (SVIN +0.3)
V V
Switching Regulator Feedback Voltage
VSFB
-0.6 to (SVIN +0.3)
V
Voltage Set
VVSET
-0.6 to (SVIN +0.3)
V
Percentage Set Voltage
VPSET
-0.6 to (SVIN +0.3)
V
Shutdown Voltage
V
-0.6 to (SVIN +0.3)
V
P Voltage
VP
-0.6 to (SVIN +0.3)
V
VSDI
-0.6 to (SVIN +0.3)
V
TOP
-40 to 85
°C
Maximum Junction Temperature
TJMAX
125
°C
Storage Temperature Range
TSTOR
-65 to 150
°C
2
kV
SDI Voltage Operating Temperature Range
ESD Rating
2
3
1. Exceeding the absolute the maximum rating may damage the device. 2. Specifications over the –40 °C to 85 °C operat ing temperature ranges are assured by design, characterization and correlation with statistical process controls. 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5 kΩ in series with 100 pF.
2.2 Recommended Operating Conditions1 Pa r a m e te r
Symbol
R a n ge
U n its
Signal Input Voltage
SVIN
3.0 to 5.5
V
PVIN
3.0 to 5.5
V
Power Input Voltage Package Thermal Resistance
2
θJA
°C/W
θJC
°C/W
1. This device is not guaranteed to function outside the specified operating range. 2. Test on 3"x 4.5" 4-layer .
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Electrical Specifications Electrical Characteristics
2.3 Electrical Characteristics The following applies unless otherwise noted: SVIN = PVIN = VEN= VVSET = VPSET = 5.0V, VOUT = 1.5V, VSDI = SGND = PGND, L (BUCK) = 1.0 µH, COUT (BUCK) = 2 x 22 µF (Ceramic), TA = 25 °C. Bold values indicate -40 °C < TA < 85 °C.
Pa r a m e te r
S y m b ol
C o nd i ti on s
M in
Signal Input Voltage Range
SVIN
SVIN = PVIN
Power Input Voltage Range
PVIN
Total Quiescent Current
Ty pe
Max
U n its
3.0
5.5
V
3.0
5.5
V
No load
mA
Shutdown Supply Current
ISVIN
VEN = 0V
1
50
μA
Undervoltage Lockout
VUVLO
High threshold, SVIN increasing
2.85
3.00
V
Low threshold, SVIN decreasing Over-voltage Protection
VOVP
V
High threshold, SVIN increasing
5.7
V
Low threshold, SVIN decreasing
5.6
V
PVIN/2
V
Enable Threshold Voltage
VEN
Enable regulators
Enable Hysteresis
V
Disable regulators
Enable Pin Input Current
IEN
V = 5.0V
5.0
μA
V = 0V
5.0
μA
Over-temperature Thermal Shutdown
TOTS
TJ increasing (Disable regulators)
150
°C
TJ decreasing (Enable regulators)
120
°C
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mV
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
2.4 Switching Step-down Regulator The following applies unless otherwise noted: SVIN = PVIN = VEN =VVSET = VPSET = 5.0V, VOUT = 1.5V, VSDI = SGND = PGND, L = 1.0 µH, COUT = 2 x 22 µF (Ceramic), TA = 25 °C. Bold values indicate -40 °C < TA < 85 °C .
Pa r a m e te r
S y m b ol
C o nd i ti on s
Output Voltage
VOUT
RVSET = 11K, PWM mode
0.8
RVSET = 18.7K, PWM mode
1.0
RVSET = 31.6K, PWM mode
1.2
RVSET = 53.6K, PWM mode
1.5
RVSET = 97.6K, PWM mode
1.8
RVSET = 165K, PWM mode
2.5
RVSET = 280K, PWM mode
3.0
RVSET = 475K, PWM mode
3.3
RPSET = 11K
-10
RPSET = 18.7K
-7.5
RPSET = 31.6K
-5
RPSET = 53.6K
-2.5
RPSET = 97.6K
2.5
RPSET = 165K
5
RPSET = 280K
7.5
RPSET = 475K
10
PVIN = 3.0V to 5.0V VOUT = 1.5V ILOAD = A
0.10
Percentage Set
M in
Ty p
Max
U ni ts
V
%
Output Voltage Line Regulation
VLNREG
Output Voltage Load Regulation
VLDREG
PVIN = 5.0V VOUT = 1.5V ILOAD =
0.10
%
Switching Frequency
fSW
ILOAD = 2.5A
1.0
MHz
Minimum Peak Switch Current Limit
ILIM
7.5
A
Output Current
IOUT
L = 1.0 µH
5.0
A
Switch Leakage Current
ILSW
PVIN = VEN = 0V
1
μA
PVIN = VEN = 0V VSW =
1
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%
50
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Electrical Specifications Switching Step-down Regulator
2.4 Switching Step-down Regulator The following applies unless otherwise noted: SVIN = PVIN = VEN =VVSET = VPSET = 5.0V, VOUT = 1.5V, VSDI = SGND = PGND, L = 1.0 µH, COUT = 2 x 22 µF (Ceramic), TA = 25 °C. Bold values indicate -40 °C < TA < 85 °C .
Pa r a m e te r
S y m b ol
C o nd i ti on s
Power-On Reset Threshold Voltage
VPORTH
VOUT > 1.35V
Power-On Reset Output Low Voltage
VPORL
ISINK = 2 mA, VEN = SGND = PGND
Power-On Reset Leakage Current
IPOR
VEN = 0V
Power-On Reset Delay
tRESET
M in
VOUT < 1.32V
Copyright © 2007 Marvell October 30, 2007, Advance
Ty p
Max
VOUT* 90%
U n its V
VOUT130 mV 0.4
V
1
μA
40
ms
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Section 3. Functional Description Figure 3: 88PG877 Block Diagram R1 C1
SVIN
EN ON
Vin 3.0V to 5.5V
C3
INTERNAL CIRCUITRY POWER SUPPLY
PVIN
Current Sense
OSCILLATOR
+
VBS
-
OFF
C2
9.5 m ANALOGDIGITAL CONVERTER
L1 PWM CONTROL
DSP
7.5 m
SDI
Serial Data Interface
THERMAL SHUTDOWN 150 ° C
R6 BAND-GAP VOLTAGE REFERENCE
UNDERVOLTAGE LOCKOUT
Vout
SW
PVIN
C5
PGND
Vin SFB
RESISTOR NETWORK
FAULT
R2 PGood
RESISTOR SENSING CIRCUITRY
SGND
VSET R3
POR
V POR
40us/40ms
PSET R5
3.1 Regulation and Start-up The step-down switching regulator uses Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) modes to regulate the output voltage using digital control. The mode of operation depends on the level of output current and the output voltage. In steady states, the step-down switching regulator monitors the current flowing through the inductor to determine if the regulator is handling heavy or light load applications. For heavy load applications, the step-down regulator operates in the PWM mode (B and C Figure 4) to minimize the ripple current for optimum efficiency and to minimize the ripple output voltage. The step-down regulator operates in the PFM and Discontinuous Conduction Mode (DCM) (A Figure 4) to limit the switching actions for optimum efficiency in light load applications. In this mode, the average output voltage is slightly higher than the average output voltage for heavy transient load applications.
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Functional Description Regulation and Start-up
Figure 4: Output Voltage Window
A B C D
Typical V OUT
PFM Mode PWM Mode PFM Mode
3.1.1 Digital Soft Start During start-up, the 88PG877 provides a soft start function. Soft start reduces surge currents from input voltage and provides well-controlled output voltage rise characteristics. Figure 5 shows that the rise time for a 88PG877 increases from 20 µs at for a 0.8V output to 70 µs for a 3.3V output with a 20 mA load. Higher load current or larger output capacitance will increase the rise time. The load current is increased to 5A in Figure 6. The 3.3V output rise time nearly doubles to 130 µs with this load. The 88PG877 has an internal switch current limit that operates on a cycle-by-cycle basis and limits the peak switch current. During soft start, the current limit threshold begins at approximately 34% of the peak current limit threshold and ramps to 100% in 7 steps at 25 µs per step (see Figure 7). During the switch first cycle, the highside switch stays on until the switch current reaches the first current limit threshold (see Figure 8) which takes less than 1 µs. The high-side switch will then turn off for a fixed off-time. If the output voltage is still low in 25 µs, the current limit threshold increases to the next level. As can be seen from Figure 5, only 25 µs or 1 current step is required for the output to reach 0.8V and 75 µs or 3 current steps for 3.3V. During soft start, the 88PG877 feeds a relatively constant current to the output capacitor in the first two steps. The average switch current during this period is approximately 2A. If more than 2 steps are required, then the switch current limit (ILIM) will need to increase. The output voltage rise time is dependent on the value of the output capacitor, the output voltage, the load current (IOUT), and the internal switch current limit circuitry and can be calculated using the following equation. ( C OUT • V OUT ) RiseTime = ---------------------------------------( I LIM – I OUT ) 2 • 22μF • 3.3V = ---------------------------------------2.0A – 0A = 72.6μS
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Figure 5: Soft Startup
Figure 6: Soft Startup
(0.8V, 1.2V, 1.8V, 2.5V, 3.3V) 1V/DIV VBUCK
500 mV/DIV
VOUT
2A/DIV IIND
10 μs/DIV
0 μs/DIV
ILOAD = 20 mA
VOUT = 3.3V
COUT = 2 x 22 μF
ILOAD =
Figure 8: First Switching Cycle
Figure 7: Inductor Current Steps at Startup
1V/DIV
VBUCK
VSW
2V/DIV
VOUT
200 mV/DIV
1A/DIV
IIND 2A/DIV
IIND
50 μs/DIV
500 ns/DIV
ILOAD = Heavy Load
Doc. No. MV-S103181-00 Rev. B Page 18
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Functional Description Output Voltage Setting
3.2 Output Voltage Setting 3.2.1 Serial Programmability The output voltage of the step-down switching regulator can also be programmed by using 18-bit serial data into the SDI pin.
Figure 9: Serial Programmability WRITE MODE DATA FIELD
"1" Pulse
"1" "0" pulse Pulse
"0" pulse
"1" Pulse
"0" "0" "1" "0" pulse pulse Pulse pulse
The period of a pulse is 1 μs +/- 200 ns Vhigh > 2.4V Vlow < 0.8V
"1" Pulse
D7
D6
D5
D4
D3
D2
D1
D0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
"1" pulse The write operation:
V high
V low
For "1" pulse, the high is 0.75 μs +/- 150 ns and the low period is 0.25 μs+/-50 ns
1) Each write sequence needs 18 pulses to complete. 2) During a non-write operation, the input needs to be at Vlow (<0.8V) 3) In between two successive write operations, the input needs to be at Vlow (<0.8V) for a minimum of 10 μs
"0" pulse 1 st Write sequence
V LOW
Low for at least 10 μs
2 nd Write sequence
V HIGH
For "0" pulse, the high is 0.25 μs +/- 50 ns and the low period is 0.75 μs+/-150 ns
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Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
The first 4 bits (MSB-bits) of the data field are used to select the output voltage where the second 4 bits (LSB-bits) of the data field are used to trim the output voltage (percent of output voltage). The default value for the data field is as follows:
Table 3:
Default Value of Data Field Data Field
Description
Voltage Set
Bits
7
6
5
4
3
Percent Set 2
1
0
Default Value
0
0
1
0
0
1
0
0
On power up, the output voltage is set according to RPSET and RVSET. The output voltage can then be field programmed by setting bit 3 and bit 7 to “1”. The output voltage and percent set are selected according to Table 4.
Table 4:
Voltage and Percentage Set Data Field
V OUT (V)
Bits
7
6
5
4
Value
1
0
0
0
1
0
0
1
0
1 1
Data Field
Perce nt Set
3
2
1
0
0.8
1
0
0
0
-10%
1
1.0
1
0
0
1
-7.5%
1
0
1.2
1
0
1
0
-5.0%
0
1
1
1.5
1
0
1
1
-2.5%
1
0
0
1.8
1
1
0
0
+2.5%
1
1
0
1
2.5
1
1
0
1
+5.0%
1
1
1
0
3.0
1
1
1
0
+7.5%
1
1
1
1
3.3
1
1
1
1
+10%
Doc. No. MV-S103181-00 Rev. B Page 20
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Functional Description Output Voltage Setting
3.2.2 Logic Programmability The output voltage of the step-down switching regulator can be programmed by connecting the VSET and PSET pins to SGND and/or SVIN. This can be very useful for standard output voltages. This method will eliminate the use of an external resistor to set the output voltage.
Table 5:
Output Voltage Setting
V VSET
V PSET
V OUT
SGND
SGND
0.8V
SGND
SVIN
1.0V
SVIN
SGND
1.2V
SVIN
SVIN
1.5V
SGND
11 kΩ < RPSET< 475 kΩ
Hi-Z
3.2.3 Output Voltage – AnyVoltageTM Technology The output voltage of the step-down switching regulator is programmed by using Table 6 or Table 7 to select resistor values for VSET and PSET pin. The VSET pin sets the output voltage and the PSET pin trims the set voltage to a percentage value. For example, to program 2.25V output, a 165 kΩ resistor is selected for the VSET pin, and an 11 kΩ resistor is selected for the PSET pin. The 165 kΩ resistor sets the output voltage to 2.5V and the 11 kΩ resistor trims the set voltage by -10%. Using the VSET resistor’s value greater than 619 kΩ or less than 7.68 kΩ disables the step-down switching regulator and sets the SW pin to high impedance. If the VSET resistor’s value is outside the % tolerance, the output can be either higher or lower than the set voltage. Using resistor values greater than 619 kΩ or less than 7.68 kΩ for the PSET pin does not affect the set voltage. When the PSET pin is not used, it must be connected to ground. Like the VSET resistor, the percent value can be either higher or lower if the PSET resistor’s value is outside the % tolerance.
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Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Table 6:
Any Voltage Programming Table
VSET
PSET -10.0%
–7.5%
–5.0%
–2.5%
0%
2.5%
5.0%
7.5%
1 0.0 %
11k
18. 7k
3 1. 6k
53 .6 k
GND
9 7.6k
165 k
28 0k
4 75k
11 k
0.720
0.740
0.760
0.780
0.800
0.820
0.840
0.860
0.880
1 8.7 k
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
3 1.6 k
1.080
1.110
1.140
1.170
1.200
1.230
1.260
1.290
1.320
5 3.6 k
1.350
1.388
1.425
1.463
1.500
1.538
1.575
1.613
1.650
9 7.6 k
1.620
1.665
1.710
1.755
1.800
1.845
1.890
1.935
1.980
1 65k
2.250
2.313
2.375
2.438
2.500
2.563
2.625
2.688
2.750
2 80k
2.700
2.775
2.850
2.925
3.000
3.075
3.150
3.225
3.300
4 75k
2.970
3.053
3.135
3.218
3.300
3.383
3.465
3.548
3.630
2.5%
5.0%
7.5%
1 0.0 %
Table 7:
Any Voltage Programming Table for 5% Resistors PSET -10.0%
–7.5%
–5.0%
–2.5%
11k
VSET
11 k
0% GND
0.720
0.740
0.760
0.780
0.800
0.820
0.840
0.860
0.880
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.080
1.110
1.140
1.170
1.200
1.230
1.260
1.290
1.320
1.350
1.388
1.425
1.463
1.500
1.538
1.575
1.613
1.650
1.620
1.665
1.710
1.755
1.800
1.845
1.890
1.935
1.980
2.250
2.313
2.375
2.438
2.500
2.563
2.625
2.688
2.750
2.700
2.775
2.850
2.925
3.000
3.075
3.150
3.225
3.300
2.970
3.053
3.135
3.218
3.300
3.383
3.465
3.548
3.630
The VSET and PSET resistors are read once during start-up before the output voltage is turned on. After the output voltage is turned on, the output voltage can change to different values using serial programming interface. Otherwise to configure the output to a different voltage, power has to recycle or the 88PG877 has to turn OFF and back ON using the EN pin.
Doc. No. MV-S103181-00 Rev. B Page 22
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Functional Description Output Voltage Setting
Figure 10 shows the startup waveforms of the 88PG877. Once the input voltage (VIN) is above the under voltage lockout (UVLO) upper threshold (UTH), the VSET and PSET pin becomes active. Current is first sourced out of PSET pin and then the VSET pin, in exponentially increasing steps. After each step there is a blanking time before the VSET voltage is compared to an internal 1.2V reference. If the VSET voltage is below internal reference voltage, the current source proceeds to the next step. Once the VSET voltage is above the internal reference voltage the sequence stops and the output voltage (VOUT) is allowed to turn on. Figure 11 shows the VSET waveform for VSET = 2.5V and PSET = –5% output. The 88PG877 keeps track of how many steps are required to determine the appropriate output voltage. Table 8 provides the number of steps necessary for each output voltage option. Using a VSET resistor of 165 kΩ requires the current source to step 4 times, and a PSET resistor of 31.6 kΩ requires 7 steps.
Figure 10: Startup Sequence
Figure 11:
2V/DIV
VIN
500mV/DIV VOUT
1V/DIV
VVSET
2V/DIV
VPSET
2V/DIV
VPSET 500mV/DIV VVSET
200 μs/DIV
2.0 ms/DIV
Table 8:
Output Voltage Option Steps
St ep
VOUT (V)
R VSET ( kΩ)
St ep
PSET (%)
R PSET ( kΩ)
1
0
>619K1
1
0
>619K1
2
3.3
475
2
+10
475
3
3.0
280
3
+7.5
280
4
2.5
165
4
+5.0
165
5
1.8
97.6
5
+2.5
97.6
6
1.5
53.6
6
-2.5
53.6
7
1.2
31.6
7
-5.0
31.6
8
1.0
18.7
8
-7.5
18.7
9
0.8
11
9
-10
11
1. 619K or 0V tied to SVIN.
Copyright © 2007 Marvell October 30, 2007, Advance
Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
The 88PG877 provides an innovative technique to set the output voltage. During start-up it reads the value of external resistors, which are located outside the regulator’s feedback loop to program the output voltage. By placing the output voltage programming resistor outside the regulator’s feedback loop, its tolerance does not affect the accuracy of the output voltage. Normally, adjustable regulators use 1% resistors to set the output voltage. However, these resistors are located inside the feedback loop, introducing as much as 2% of initial accuracy error to the output voltage, resulting in an overall initial accuracy of 3%. Whereas, the 88PG877 initial accuracy is 2% for any of the eight output voltages. The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The output voltage can potentially be programmed to the lower output voltage if there is contamination, which introduces excessive leakage current on the VSET and PSET pin, especially for the 3.3V output or +10%. The parasitic resistance on these nodes must be greater than 3 MΩ and the stray capacitance must be less than 25 pF; otherwise, a 3.3V output can potentially end up at 3V.
3.3 Undervoltage Lockout (UVLO) At start-up, the 88PG877 incorporates undervoltage-lockout circuitry to enable the step-down switching regulator when the input voltage is above (typical). After the 88PG877 is enabled and the input voltage is lowered, the highest value of the minimum input voltage for both regulators to remain enabled is (typical).
3.4 Over Voltage Protection (OVP) The 88PG877 incorporates an over voltage protection circuitry to disable the step-down switching regulator when the input voltage is above 5.7V (typical). The step-down switching regulator is enabled when the input voltage is below 5.6V (typical).
Figure 12: UVLO and OVP Waveforms
V OVP_HTH VOVP_LTH
V UVLO_HTH V UVLO_LTH
VIN BUCK Output Enable Undefined BUCK Output Disable
Doc. No. MV-S103181-00 Rev. B Page 24
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Functional Description Power-On Reset (POR)
3.5 Power-On Reset (POR) The Power-On Reset pin is an active-high, open-drain output pin. This output is held low when the output voltage of the step-down regulator is below the threshold. When the output voltage is above the threshold, the Power-On Reset pin goes high 40 ms later. Setting the output voltage greater than 1.35V, the threshold voltage is 0.9% * VOUT (typical). Setting the output voltage less than 1.32V, the threshold voltage is VOUT – 130 mV (typical). A builtin 25 µs (tDELAY) delay is incorporated to prevent nuisance tripping.
Figure 13: Power-On Reset Waveforms
V POOD
t
DELAY
VPORH V PORL
40 ms
3.6 Thermal Shutdown When the junction temperature of the 88PG877 exceeds 150 °C (typical), the thermal shutdown circuitry disables the step-down regulator. The step-down switching regulator is enabled when the junction temperature is decreased to 120 °C (typical).
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Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
3.7 Adaptive Transient Response The 88PG877 device’s Smart Technology allows the step-down switching regulator to quickly respond to the multiple step loads and maintain stability over a wide range of applications. Figure 14 shows an example of a second step-load applied while the output voltage of the step-down switching regulator increased due to the inductive kick from the first step-load. Condition: VIN = 5.0V, RSVIN = 10Ω, CSVIN = 0.1 µF, CPVIN = µF, L = 1.0 µH, COUT = 2 x 22 µF, VOUT = 1.V, ILOAD = 1A to 5A.
Figure 14: Adaptive Transient Response
VOUT
100mV/DIV
ILOAD
5A/DIV
20 μs/DIV
The worst case overshoot (VSOAR) during a full-load to light-load transient due to stored inductor energy (Figure 14) can be calculated as: 2
ΔI LOAD ( MAX ) • L V SOAR = ----------------------------------------------2 • C OUT • V OUT Although the VSOAR cannot be eliminated, its amplitude can be controlled based on the COUT capacitor value. The appropriate COUT value can easily be calculated for the acceptable VSOAR level for each specific application. 2
ΔI LOAD ( MAX ) • L C OUT = ----------------------------------------------2 • V SOAR • V OUT
Doc. No. MV-S103181-00 Rev. B Page 26
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Functional Characteristics Start-up Waveforms
Section 4. Functional Characteristics The following applies unless otherwise noted: TA = 25°C, R SVIN = 10Ω, CSVIN = 0.1 µF, CPVIN = 2 x 22 µF, L = 1.0 µH, COUT (BUCK) = 2 X 22 µF.
4.1 Start-up Waveforms NOTE: When the input voltage rises above the UVLO’s upper threshold, then there is a delay (4 ms typ) before the stepdown regulator’s output voltage turns on.
Figure 15: Startup Using the Enable Pin
VEN
Figure 16: Turn Off Using the Enable Pin
1V/DIV
VEN 1V/DIV VBUCK 1V/DIV
VBUCK
1V/DIV VPOR
VPOR
5V/DIV
5V/DIV
2.0 ms/DIV
10 ms/DIV VIN = 5.0V
ILOAD = No Load
VIN = 5.0V
VBUCK= 1.2V
tDLY= 4.0 ms
VBUCK= 1.2V
Figure 17: Soft Start
Figure 18: Hot Plug
2V/DIV VIN
VIN
2V/DIV
1V/DIV VBUCK
1V/DIV
VBUCK
VPOR
5V/DIV
VPOR
5V/DIV
10 ms/DIV
10 ms/DIV VIN = 5.0V
VBUCK= 1.2V
VIN = 5.0V
ILOAD = No Load
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VBUCK= 1.2V ILOAD = No Load
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Figure 19: UVLO and OVP Thresholds
VIN
2V/DIV
VBUCK
1V/DIV
100 ms/DIV VIN = 0 to 6.0V
VUVLO(HTH) = 2.93V
VBUCK= 1.5V
VUVLO(LTH)= 2.87V
ILOAD(BUCK) = 1A
VOVP(HTH) = 5.74V VOVP(LTH) = 5.53V
4.2 Short-Circuit Waveforms Figure 20: Step-Down Short-Circuit Response
VSW 5V/DIV
VBUCK
500 mV/DIV
IIND 5A/DIV
200 μs/DIV
Doc. No. MV-S103181-00 Rev. B Page 28
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Functional Characteristics Switching Waveforms
4.3 Switching Waveforms NOTE: For repeatability of measuring output ripple (VBUCK (P-P)) for the BUCK regulator, the standard test procedure limits the scope bandwidth to 20 MHz and uses a coax cable with very short leads terminated into 50Ω. The coax leads must be routed away from the switching node as much as possible.
Figure 21: Switching Waveforms PWM mode VSW 5V/DIV IIND 1A/DIV VBUCK 5 mV/DIV VIN 100 mV/DIV
500 ns/DIV CIN = 2x22 μF
VIN(P-P) = 101 mV
VIN = 5.0V
IIND(P-P) = 1.2A
VBUCK= 1.5V
IIND(PK) = 5.4A
IOUT = 5.0A
Freq = 964 kHz
VOUT(P-P) = 7.3 mV (Note)
Figure 23: Switching Waveforms - DCM
Figure 22: Switching Waveforms DCM Mode
VSW
Mode-Zoom
2V/DIV
20 mV/DIV
VBUCK
VSW
2V/DIV
20 mV/DIV
VBUCK
IIND 1A/DIV
1A/DIV
IIND
5 μs/DIV
1.0 μs/DIV
VIN = 5.0V
IIND(PK) = 1.42A
VIN = 5.0V
VBUCK= 1.5V
Freq = 89 kHz
VBUCK= 1.5V
IOUT = 50 mA
IOUT = 50 mA
VOUT(P-P) = 37 mV (Note)
Ringing Freq = 5 MHz
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Figure 24: PWM Output Ripple Voltage
VBUCK
10 mV/DIV
100 ms/DIV VIN = 5.0V VBUCK= 1.5V IOUT = 5.0A VOUT(P-P) = 11.2 mV (Note)
Doc. No. MV-S103181-00 Rev. B Page 30
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Functional Characteristics Load Transient Waveforms
4.4 Load Transient Waveforms 4.4.1 Step-Down Regulator Figure 25: Fast Load Rise Time
VSW
Figure 26: Slow Load Rise Time
5V/DIV
VBUCK
200 mV/DIV
VSW
5V/DIV
VBUCK
200 mV/DIV
IIND
IIND ILOAD 5A/DIV
ILOAD
5A/DIV
5A/DIV
IIND
5A/DIV
IIND
2.0 μs/DIV
2.0 μs/DIV
VIN = 5.0V
COUT = 2 x 22 μF
VIN = 5.0V
COUT = 2 x 22 μF
VBUCK= 1.5V
tRISE = 27 A/μs
VBUCK= 1.5V
tRISE = 2.4 A/μs
IOUT = 1 A to 5A
IOUT = 1 A to 5A
Figure 27: Fast Load Fall Time
VSW
Figure 28: Slow Load Fall Time
5V/DIV VSW 200 mV/DIV
VBUCK
IIND
ILOAD IIND
5V/DIV
VBUCK
5A/DIV
ILOAD
5A/DIV
IIND
200 mV/DIV
IIND
5A/DIV 5A/DIV
2.0 μs/DIV
2.0 μs/DIV
VIN = 5.0V
COUT = 2 x 22 μF
VIN = 5.0V
COUT = 2 x 22 μF
VBUCK= 1.5V
tFALL = 190 A/μs
VBUCK= 1.5V
tFALL = 2.5 A/μs
IOUT = A to A
IOUT = A to A
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Figure 29: Load Transient Response
VBUCK
Figure 30: Double-Pulsed Load Response
200 mV/DIV 200 mV/DIV
VBUCK
ILOAD
5A/DIV
5A/DIV
ILOAD
10 μs/DIV
20 μs/DIV
VIN = 5.0V
ILOAD = 1A to 5A
VIN = 5.0V
ILOAD = 1A to 5A
VBUCK= 1.5V
tRISE = 27 A/μs
VBUCK= 1.5V
tRISE = 27 A/μs
COUT = 2 x 22 μF
tFALL = 190 A/μs
COUT = 2 x 22 μF
tFALL = 190 A/μs
Figure 32: Double-Pulsed Load Response
Figure 31: Load Transient Response
VBUCK
200 mV/DIV VBUCK
200 mV/DIV
5A/DIV
ILOAD
ILOAD
5A/DIV
10 μs/DIV
20 μs/DIV
VIN = 5.0V
ILOAD = 1A to 5A
VIN = 5.0V
ILOAD = 1A to 5A
VBUCK= 1.5V
tRISE = 27 A/μs
VBUCK= 1.5V
tRISE = 27 A/μs
COUT = 4 x 22 μF
tFALL = 190 A/μs
COUT = 4 x 22 μF
tFALL = 190 A/μs
VCG = GND
VCG = GND
Doc. No. MV-S103181-00 Rev. B Page 32
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Functional Characteristics Output Voltage Transient Waveforms
4.5 Output Voltage Transient Waveforms The following graphs show the effect of changing the step-down regulator’s output voltage using the serial interface. Depending on the change in the step-size of the output voltage, the output load, and the output capacitance, the power-on reset pin de-asserts when the changes of the output voltage occur beyond the 25 μs (typical) delay.
4.5.1 Step-Down Regulator Figure 33: VOUT = 1.0V to 1.2V with No Load
VBUCK
Figure 34: VOUT = 1.0V to 1.5V with No Load
500 mV/DIV
VPOR
VBUCK
500 mV/DIV
5V/DIV
SDI
VPOR
5V/DIV
SDI
5V/DIV
5V/DIV
20 μs/DIV
20 μs/DIV
VIN = 5.0V
VIN = 5.0V
COUT= (2 x 22) + 1000 μF
COUT= (2 x 22) +1000 μF
Figure 36: VOUT = 1.0V to 1.5V with ILOAD = 5A
Figure 35: VOUT = 1.0V to 1.2V with ILOAD = 5A
VBUCK
500 mV/DIV
500 mV/DIV
VBUCK VPOR
5V/DIV
VPOR
5V/DIV
SDI
5V/DIV
SDI
5V/DIV
20 μs/DIV
20 μs/DIV
VIN = 5.0V
VIN = 5.0V
COUT= (2 x 22) + 1000 μF
COUT= (2 x 22) +1000 μF
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88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Figure 38: VOUT = 1.5V to 1.0V with ILOAD = 5A
Figure 37: VOUT = 1.2V to 1.0V with ILOAD = 5A
VBUCK
500 mV/DIV
VBUCK 500 mV/DIV
VPOR
5V/DIV
SDI
5V/DIV
VPOR
5V/DIV
SDI
5V/DIV
20 μs/DIV
20 μs/DIV
VIN = 5.0V
VIN = 5.0V
COUT= (2 x 22)+1000 μF
COUT= (2 x 22)+1000 μF
4.6 Line Transient Waveforms Figure 40: Line Transient @ VIN = 4.1V to 4.5V
Figure 39: Line Transient @ VIN = 3.2V to 3.6V
1V/DIV VIN 1V/DIV
VIN
20 mV/DIV 20 mV/DIV
VBUCK
VBUCK
2.0 ms/DIV
2.0 ms/DIV
VIN = 3.6V
VBUCK = 1.2V
VIN = 4.5V
VBUCK = 1.2V
CIN= 22 μF
ILOAD = 5A
CIN= 22 μF
ILOAD = 5A
Doc. No. MV-S103181-00 Rev. B Page 34
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Typical Characteristics Efficiency Graphs
Section 5. Typical Characteristics
5.1 Efficiency Graphs Efficiency vs. Output Current Vin = 3.3V
100
100
90
90 Efficiency (%)
Efficiency (%)
Efficiency vs. Output Current Vin = 5.0V
80 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V
70 60
80 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V
70 60
50
50 0
1
2
3
4
Output Current (A)
5
0
1
2
3
4
Output Current (A)
G77 G1
5 G77 G2
5.1.1 Efficiency Graphs in log scale
Efficiency vs. Output Current Vin = 3.3V
100
100
90
90
80
Efficiency (%)
Efficiency (%)
Efficiency vs. Output Current Vin = 5.0V
3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V
70 60 50 0.01
0.1
1
1.8V 70
1.5V 1.2V
60
1.0V 0.8V
10
Output Current (A)
80
50 0.01
G77 G3
0.1 1 Output Current (A)
10 G77 G4
5.2 Load Regulation Output Voltage vs. Output Current Vout = 1.5V
Output Voltage (V)
1.60
1.55
1.50
1.45
3.3V 5.0V
1.40 0
1
2 3 Output Current (A)
4
5 G77 G5
Copyright © 2007 Marvell October 30, 2007, Advance
Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
Page 35
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
5.3 Dropout Voltage Step-Down Regulator Dropout vs. Load Current Vin = 3.2, Vout = 3.3V 0.200 85C 25C
Buck Dropout (V)
0.150
-40C 0.100
0.050
0.000 0
1
2 3 Output Current (A)
4
5 G77 G6
5.4 RDS (ON) Resistance Bottom Switch Resistance vs. Temperature
Top Switch Resistance vs. Temperature 0.016
Resistance (Ohm)
Resistance (ohm)
0.016 0.014 0.012 0.010 0.008
Vin = 3.0V Vin = 4.0V
0.006
Vin = 5.0V
0.004
0.014
Vin = 3.0V
0.012
Vin = 5.0V
Vin = 4.0V
0.010 0.008 0.006 0.004
-40
-20
0
20
40
60
-40
80
Temperature (C)
-20
0
20
40
60
G77 G8
Top Switch Resistance vs. Input Voltage
Bottom Switch Resistance vs. Input Voltage 0.016
0.014
Resistance (Ohm)
Resistance (ohm)
0.016 Ta = 25C
0.012 0.010 0.008 0.006 0.004
0.014 0.012
Ta = 25C
0.010 0.008 0.006 0.004
3
3.5
4
4.5
5
3
3.5
4
4.5
5
Input Voltage (V)
Input Voltage(V) G77 G9
Doc. No. MV-S103181-00 Rev. B Page 36
80
Input Voltage (V) G77 G7
G77 G10
Copyright © 2007 Marvell Document Classification: Proprietary Information
October 30, 2007, Advance
Typical Characteristics IC Case and Inductor Temperature
5.5 IC Case and Inductor Temperature The following data was taken using a 1.4 square inch PCB 1 oz. copper and L = 1.2 μH. Actual results depend upon the size of the PCB proximity to other heat emitting components.
Input Current vs. Output Current Vin = 5V, Ta = 25°C
Input Current vs. Output Current Vin = 3.3V, Ta = 25°C
6.0
7.0
4.0 3.0 2.0
2.5V
Input Current (A)
Input Current (A)
6.0
3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V
5.0
1.0
5.0
1.8V 1.5V
4.0
1.2V 1.0V
3.0
0.8V
2.0 1.0 0.0
0.0 0
1
2
3
4
0
5
1
2
3
4
5
Output Current (A)
Output Current (A)
G77 G12
G77 G11
IC Case Temperature vs. Output Current Vin = 3.3V, Ta = 25°C
IC Case Temperature vs. Output Current Vin = 5V, Ta = 25°C 80
80
70
Temperature (°C)
60 50 40
Temperature (°C)
3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V
70
50 40 30
30
20 0
20 0
1
2 3 Output Current (A)
4
1
2
3
4
5
Output Current (A)
5
G77 G14
G77 G13
Inductor Temperature vs. Output Current Vin = 5V, Ta = 25°C
Inductor Temperature vs. Output Current Vin = 3.3V, Ta = 25°C
80
80
70
70
3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V
60 50 40
Temperature (°C)
Temperature (°C)
2.5V 1.8V 1.5V 1.2V 1.0V 0.8V
60
2.5V 1.8V 1.5V 1.2V 1.0V 0.8V
60 50 40 30
30
20
20 0
1
2
3
Output Current (A)
4
5
0
G77 G15
Copyright © 2007 Marvell October 30, 2007, Advance
1
2
3
4
5
Output Current (A) G77 G16
Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
Page 37
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
5.6 Input Voltage Graphs
Supply Current vs. Input Voltage
Shutdow n Supply Current vs. Input Voltage 1.0 Shutdown Current (uA)
Supply Current (mA)
2.0 1.5 1.0 0.5 0.0
0.8 0.6 0.4 0.2 0.0
3.0
3.5
4.0
4.5
5.0
5.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
Input Voltage (V) G77 G18
G77 G17
Load = No Load
VIN = 5.0V Load = No Load
Shutdown Threshold vs. Input Voltage 3.0
Shutdown Treshold (V)
UTH - Disable LTH - Enable
2.5
2.0
1.5
1.0 3
3.5
4
4.5
5
Input Voltage (V) G77 G19
Doc. No. MV-S103181-00 Rev. B Page 38
Copyright © 2007 Marvell Document Classification: Proprietary Information
October 30, 2007, Advance
Typical Characteristics Input Voltage Graphs
5.6.1 Step-Down Regulator
Efficiency vs. Input Voltage 100%
1.515
95%
Efficiency
Output Voltage (V)
Output Voltage vs. Input Voltage 1.53
1.5
90%
85%
1.485
80%
1.47 3.0
3.5
4.0
4.5
5.0
3.0
5.5
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Input Voltage (V)
G77 G21
G77 G20
IOUT(BUCK) = 1.25A
VOUT(BUCK) = 1.5V IOUT(BUCK) = 2.5A
Frequency vs. Input Voltage
Load Regulation vs. Input Voltage
1200
1100
0.10%
Frequency (kHz)
Load Regulation
0.20%
0.00%
1000
900
-0.10% 3.0
3.5
4.0
4.5
5.0
5.5
800 3.0
Input Voltage (V)
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
G77 G22
G77 G23
VOUT(BUCK) = 1.5V
VOUT(BUCK) = 1.5V
IOUT(BUCK) = 1.25A - 5.0A
IOUT(BUCK) = 2.5A
Average Output Current Limit vs. Input Voltage 10.0
Current Limit (A)
9.0
8.0
7.0
6.0
5.0 3
3.5
4
4.5
Input Voltage (V)
5
5.5 G77 G24
Copyright © 2007 Marvell October 30, 2007, Advance
Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
Page 39
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
5.7 Temperature Graphs Shutdow n Supply Current vs.Temperature
Supply Current vs. Temperature
3 Shutdown Current (uA)
Supply Current (mA)
2.0
1.5 1.0
0.5 0.0 -40
-20
0
20
40
60
Temperature (°C)
2
1
0 -40
80
-20
0
20
40
60
80
Temperature (°C)
G77 G25
G77 G26
IOUT(BUCK) = No Load IOUT(LDO) = No Load
UVLO vs. Temperature
Shutdown Threshold vs. Temperature
3
Shutdown Treshold (V)
3.0
UVLO (V)
2.9 2.8 HTH
2.7
LTH
2.6 -40
-20
0
20
40
60
80
2.5 2.0 UTH - Disable
1.5
LTH - Enable
1.0 -40
Temperature (°C)
IOUT(BUCK) = 10 mA
0
20
40
60
80 G77 G28
VIN= 5V
Doc. No. MV-S103181-00 Rev. B Page 40
-20
Temperature (°C)
G77 G27
Copyright © 2007 Marvell Document Classification: Proprietary Information
October 30, 2007, Advance
Typical Characteristics Temperature Graphs
5.7.1 Step-Down Regulator
Buck Efficiency vs. Temperature 100%
1.515
95% Efficiency
Output Voltage (V)
Output Voltage vs. Temperature
1.53
1.5
90%
85%
1.485
80%
1.47 -40
-20
0
20
40
60
-40
80
Temperature (°C)
-20
0
20
40
60
80
Temperature (°C)
G77 G29
VIN = 5.0V
VIN = 5.0V
IOUT(LDO) = 1.2A
VOUT(BUCK) = 1.5V
G77 G30
IOUT(BUCK) = 2.5A
Buck Line Regulation vs. Temperature
Buck Load Regulation vs. Temperature 0.20%
0.00%
Line Regulation
Load Regulation
0.10%
0.00%
-0.10%
-0.20%
-0.10%
-0.30% -0.20%
-40 -40
-20
0
20
40
60
-20
0
80
20
40
60
80
Temperature (°C)
Temperature (°C) G77 G31
G77 G32
VIN = 5.0V
VIN = 3.0V - 5.0V
VOUT(BUCK) = 1.5V
VOUT(BUCK) = 1.5V
IOUT(BUCK) = 1.25A
IOUT(BUCK) = 2.5A
Buck Current Limit vs. Temperature
Frequency vs. Temperature
10.0
1100.0 1050.0 Frequency (kHz)
Current Limit (A)
9.0
8.0
7.0
6.0
5.0 -40
1000.0 950.0 900.0 850.0 800.0
-20
0
20
40
60
-40
80
-20
0
20
40
Temperature (°C)
Temperature (°C) G77 G33
60
80 G77 G34
VIN = 5.0V IOUT(BUCK) = 2.5A Copyright © 2007 Marvell October 30, 2007, Advance
Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
Page 41
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Section 6. Applications Information
6.1 PC Board Layout Considerations and Guidelines for 88PG877 1. 2.
3. 4.
5. 6.
7. 8. 9. 10.
11.
12.
13.
This is a 2-layer board with 1 ground plane and 1 routing layer. Copy the routing layer in Figure 43 as much as possible and place on the top layer. The ground plane in Figure 44 can be placed on any other layer. Use the recommend BOM in Table 9. Contact the factory if substitutions are made. Review the recommended solder pad layout and notes on page 51. Do not replace the Ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor as long as the Ceramic input capacitor is placed next to the IC. If Tantalum input capacitor is used, it must be rated for switching regulator applications and the operating voltage be derated by 50%. Any type of capacitor can be placed in parallel with the output capacitor. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide the lowest noise and smallest foot print solution. Use planes for the ground, input and outputs power to maintain good voltage filtering and to keep power losses low. If there is not enough space for a power plane for the input supply, then the input supply trace must be at least 3/8 inch wide. If there is not enough space for a power plane for the output supplies, then place the output as close to the load as possible with a trace of at least 3/8 inch wide. Do not lay out the inductor first. The input capacitor placement is the most critical for proper operation. The AC current circulating through the input capacitor and loop 1 (LP1) are square wave with rise and fall times of 8 ns and slew rates as high as 300 A/µs (Figure 41). At these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3V per inch of PCB trace, VIND = L * di/dt. Therefore, the Ceramic input capacitor must be placed as close as possible to the PVIN and PGND pins with as short and wide a trace as possible. Also, the PVIN and PGND traces must be placed on the top layer. This will isolate the fast AC currents from interfering with the analog ground plane. The 88PG877 has two internal grounds, analog (SGND) and power (PGND). The analog ground ties to all the noise sensitive signals (PSET, VSET, and SVIN) while the power ground ties to the higher current power paths. Noise on an analog ground can cause problems with the IC’s internal control and bias signals. For this reason, separate analog and power ground traces are recommended. The signal ground is connected to the power ground at one point, which is the (-) terminal of the output capacitor. Keep loop 2 (LP2) as small as possible and connect the (-) terminal of the output capacitor as close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors, as shown in Figure 43, is recommended for best results. Keep the switching node (SW) away from the SFB pin and all sensitive signal nodes, minimizing capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a right angle.
14. 15. Try not to route analog or digital lines in close proximity to the power supply especially the VSW node. If this can’t be avoided, shield these lines with a power plane placed between the VSW node and the signal lines. 16. The type of solder paste recommended for QFN packages is “No clean”, due to the difficulty of cleaning flux residues from beneath the QFN package.
Doc. No. MV-S103181-00 Rev. B Page 42
Copyright © 2007 Marvell Document Classification: Proprietary Information
October 30, 2007, Advance
Applications Information PC Board Layout Considerations and Guidelines for 88PG877
Figure 41: PCB Layout U1 R PSET PSET R VSET VSET VBS SVIN R 10
SW
Vin
PVIN PGND
I Cin
SFB
LP2
Cou t
Copyright © 2007 Marvell October 30, 2007, Advance
Vout
SGND
LP1
Ci n
LP1
CBS L1
C 0.1uF
I Cout
LP2
Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
Page 43
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Figure 42: 88PG877 PCB Board Schematic
R1 10 ohm
R3
R5
R2 100K
16
17
SDI
POR
SW
SW
PVIN
PGND
PVIN
PGND
7
6
SGND
88PG877
PGND
5
VBS
15 14 13 12 11 10
L1 1.0uH
9
4
SFB
SW
C2 47nF
EN
SW
3
C1 0.1uF
SVIN
19
2
VSET
PVIN
1
PSET
U1
8
R4 100k
18
POR
Vin 3.0V - 5.5V
Vout C4 22uF/6.3V
C3 22uF/6.3V
C7 4.7uF/6.3V
Doc. No. MV-S103181-00 Rev. B Page 44
C5 22uF/6.3V
C6 22uF/6.3V
Copyright © 2007 Marvell Document Classification: Proprietary Information
October 30, 2007, Advance
Applications Information PC Board Layout Considerations and Guidelines for 88PG877
6.1.1 PC Board Layout Examples for 88PG877 • •
Total copper layers = 2 (Top and Bottom) All the components are on the top layer
Figure 43: Top Silk-Screen, Top Traces, Vias and Copper (Not to scale) Actual board size = 670 mil x 910 mil Total copper layer = 2
Connect to the input voltage plane of the board.
Connect to the input voltage plane of the board.
Connect to the ground plane of the board.
Connect the BUCK output voltage at this point.
Copyright © 2007 Marvell October 30, 2007, Advance
Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
Page 45
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Figure 44: Bottom Silk Screen, Bottom Traces, Vias, and Copper (Not to scale) Connect the POR signal to this via
Connect to the ground plane of the board. Connect to the ground plane of the board. Connect to the ground plane of the board.
Doc. No. MV-S103181-00 Rev. B Page 46
Copyright © 2007 Marvell Document Classification: Proprietary Information
October 30, 2007, Advance
Applications Information PC Board Layout Considerations and Guidelines for 88PG877
6.1.2 Bill of materials for 88PG877 Table 9 lists the components used with the 88PG877. Table 9:
88PG877 BOM
Item
Q ty
Ref
M a n u f a c t u r er P a r t N o.
Ma n u f actu r er
D e s c r i p t io n
1
1
U1
88PG877
Marvell Semiconductor Inc.
1MHz, 7.5A Peak-Current Limit Step-down Regulator
2
1
C1
C1005X5R1A104K
Taiyo-Yuden
0.1 μF, ±10%, X5R, 10V, 0402 Case Size, Ceramic Capacitor.
3
1
C2
0402YD473KAT2A
AVX Corporation
0.047 μF, ±20%, X5R, 16V, 0402 Case Size, Ceramic Capacitor.
4
4
C3,C4, C5,C6
C2012X5R0J226M
TDK
22 μF, ±20%, X5R, 6.3V, 0805 Case Size, Ceramic Capacitor.
5
1
C7
C1608X5R0J475M
TDK
4.7 μF, ±20%, X5R, 6.3V, 0603 Case Size, Ceramic Capacitor.
6
1
L1
FDV0630-1R0M=P3
Toko
1.0 μH, 9.1A, 10 mohm, H=3mm, L=7.7mm, W=7mm, SMD Inductor
7
1
R1
ERJ-2RKF10R0X
Panasonic-ECG
10.0 ohm, 1/16W, 1%, 0402 Case size, SMD Resistor
8
2
R2,R4
ERJ-3GEYJ104V
Panasonic-ECG
100 kohm, 1/10W, 5%, 0603 Case size, SMD Resistor
9
1
R3,R5
See AnyVoltage™ Programming, 1/16W, 1% 0402 Case Size
Copyright © 2007 Marvell October 30, 2007, Advance
Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
Page 47
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Table 10:
Ceramic Capacitor Cross Reference
Manu facturer
Manu factu rer Part #
Des cription
22 μF
Taiyo-Yuden
CE JMK212BJ226MG-T
TDK
C2012X5R0J226MT
Murata
GRM21BR60J226ME39L
Taiyo-Yuden
CE JMK212BJ106MG-T
TDK
C2012X5R0J106MT
Murata
GRM219R60J106KE190
Taiyo-Yuden
RM LMK105 BJ104KV-F
TDK
C1005X5R1A104K
10 μF
0.1 μF
Doc. No. MV-S103181-00 Rev. B Page 48
Copyright © 2007 Marvell Document Classification: Proprietary Information
October 30, 2007, Advance
Mechanical Drawing 88PG877 Mechanical Drawing
Section 7. Mechanical Drawing
7.1 88PG877 Mechanical Drawing 3
INDEX AREA (D/2xE/2)
2x 2x TOP VIEW
NX
SEATING
DETAIL 'A'
PLANE
SIDE VIEW
e 18Xb
Terminal Tip
INDEX AREA
7 ''A''
6
(D/2xE/2)
4
15
1
18
BOTTOM VIEW
17XL
''B''
Copyright © 2007 Marvell October 30, 2007, Advance
DETAIL 'B'
Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
Page 49
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
7.2 88PG877 Mechanical Dimensions Symbol A A1 A3 b D E e L aaa bbb ccc
Dimension in mm MIN --0.00 0.20 2.90 3.90
NOM MAX 1.00 0.90 0.02 0.05 0.20 REF 0.25 0.30 3.10 3.00 4.10 4.00 0.50 BSC
0.40
0.50
-------
-------
0.60 0.15 0.10 0.10
Note: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. 3. The terminal #1 identifier and terminal numbering convention 4. Pin 1 (0.6mm) is longer than other pins (0.5mm)
Doc. No. MV-S103181-00 Rev. B Page 50
Copyright © 2007 Marvell Document Classification: Proprietary Information
October 30, 2007, Advance
Mechanical Drawing Typical Pad Layout Dimensions
7.3 Typical Pad Layout Dimensions 7.3.1 Recommended Solder Pad Layout Package Outline
0.75
1
Package Outline
0.50 3.00 4.30
0.25
1.20 1.00
0.65 3.30
88PG877 4x3 QFN-18 Land Pattern (mm)
0.25 mm
0.25 mm Pad
0.051 mm 2.0 mils
SM
Pad
SM
Pad
0.148 mm
QFN Lead with Non-Solder Mask Defined Terminal (Not to Scale)
Notes: 1. 2. 3. 4. 5. 6. 7.
TOP VIEW DRAWING NOT TO SCALE DIMENSIONS ARE IN MILLIMETERS OVERSIZE SOLDER MASK BY 4 MILS OVER PAD SIZE (2 MIL ANNULAR RING) SOLDER MASK (SM) BETWEEN PADS TOLERANCE ±0.05 mm PIN 1 IS LONGER THAN OTHER PINS BY 0.1 mm
Copyright © 2007 Marvell October 30, 2007, Advance
Doc. No. MV-S103181-00 Rev. B Document Classification: Proprietary Information
Page 51
88PG877 1 MHz, 7.5A Peak Current-Limit Step-Down Regulator with AnyVoltage™ Technology
Section 8. Ordering Information
8.1 Ordering Part Numbers and Package Markings Figure 45 shows the ordering part numbering scheme for the 88PG877 devices. Contact Marvell® FAEs or sales representatives for complete ordering information.
Figure 45: Sample Part Number
88PG877 –xx–xxx–C000–xxxx Custom Code (optional)
Part Number 88PG877
Custom Code
Custom Code Package Code NFB = 18-Pin QFN
Custom Code Environmental Code 1 = RoHS 6/6 compliant – = RoHS 5/6 compliant
8.2 Sample Ordering Part Number The standard ordering part numbers for the respective solutions are as follows: Table 11:
88PG877 Ordering Part Numbers1
Ma rke ting Part Number
Ma rking
88PG877-NFB1
Ambient Tem per atur e Range 2 -40 °C to 85 °C
Packa ge 3
4 X 3 QFN-18
1. Contact Marvell® for details. 2. Specifications over the –40 °C to 85 °C operating temperature range are assured by design, characterization and correlation with statistical process controls. 3. Package dimensions are in mm.
Doc. No. MV-S103181-00, Rev. B Page 52
Copyright © 2007 Marvell Document Classification: Proprietary Information
October 30, 2007, Advance
Ordering Information Package Marking
8.3 Package Marking 8.3.1 88PG877 Package Marking and Pin 1 Locations Figure 46 is an example of the package marking and pin 1 location for the 88PG877 part. Markings for the other variants are similar.
Figure 46: 88PG877 Package Marking and Pin 1 Location
MRVLG77 00XX# YWW$$
M ar k ing Power code, Revision, Assembly code 00 = Power code XX = Revision $$ = Assembly code Year, Work week, Lot Tracking Y = Last digit of year WW = Work week $$ = Lot tracking Pin 1 location
Note: The above example is not drawn to scale. Locations of markings are approximate.
Copyright © 2007 Marvell October 30, 2007, Advance
Doc. No. MV-S103181-00, Rev. B Document Classification: Proprietary Information
Page 53
Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com
Worldwide Corporate Offices
Worldwide Sales Offices
Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500
Western US Marvell 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 Sales Fax: 1.408.752.9029
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For more information, visit our website at: www.marvell.com
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Marvell Rm. 1102/1103, Jintian Fudi Mansion #9 An Ning Zhuang West Rd. Qing He, Haidian District Beijing, PRC 100085 Tel: 86.10.8274.3831 Fax: 86.10.8274.3830
Eastern US/Canada Marvell Parlee Office Park 1 Meeting House Road, Suite 1 Chelmsford, MA 01824 , USA Tel: 1.978.250.0588 Fax: 1.978.250.0589
Japan Marvell Shinjuku Center Bldg. 44F 1-25-1, Nishi-Shinjuku, Shinjuku-ku Tokyo 163-0644, Japan Tel: 81.(0).3.5324.0355 Fax: 81.(0).3.5324.0354
Europe Marvell 5 Marchmont Gate Boundary Way Hemel Hempstead Hertfordshire, HP2 7BF United Kingdom Tel: 44.(0).1442.211668 Fax: 44.(0).1442.211543
Taiwan Marvell 2Fl., No.1, Alley 20, Lane 407, Sec. 2 Ti-Ding Blvd., Nei Hu District Taipei, Taiwan, 114, R.O.C Tel: 886.(0).2.8177.7071 Fax: 886.(0).2.8752.5707
Israel Marvell 6 Hamada Street Mordot HaCarmel Industrial Park Yokneam 20692, Israel Tel: 972.(0).4.909.1500 Fax: 972.(0).4.909.1501
Korea Marvell Rm. 603, Trade Center 159-2 Samsung-Dong, Kangnam-Ku Seoul 135-731, Korea Tel: 82.(0).2.551-6070/6079 Fax: 82.(0).2.551.6080
